1 /**
2 ******************************************************************************
3 * @file rtl8721d_crypto.h
4 * @author
5 * @version V1.0.0
6 * @date 2017-09-15
7 * @brief This file contains all the functions prototypes for the IPsec firmware
8 * library
9 ******************************************************************************
10 * @attention
11 *
12 * This module is a confidential and proprietary property of RealTek and
13 * possession or use of this module requires written permission of RealTek.
14 *
15 * Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved.
16 ******************************************************************************
17 */
18
19 #ifndef _RTL8721D_CRYPTO_H_
20 #define _RTL8721D_CRYPTO_H_
21
22 /** @addtogroup AmebaD_Periph_Driver
23 * @{
24 */
25
26 /** @defgroup CRYPTO
27 * @brief CRYPTO driver modules
28 * @{
29 */
30
31 /** @addtogroup CRYPTO
32 * @verbatim
33 *****************************************************************************************
34 * Introduction
35 *****************************************************************************************
36 * -Authentication or Cipher use hardware to improve data process performance
37 * -Two mode: secure mode and non-secure mode
38 * -Register base address: Secure mode -0x5007xxxx, non-secure mode -0x4007xxxx
39 * -IPclk: 100MHz
40 *****************************************************************************************
41 * Authentication
42 *****************************************************************************************
43 * -MD5
44 * -SHA1
45 * -SHA2
46 * -HMAC-MD5
47 * -HMAC-SHA1
48 * -HMAC-SHA2
49 * -Poly1305
50 * -Sequential hash
51 *
52 *****************************************************************************************
53 * Cipher
54 *****************************************************************************************
55 * -AES-CBC
56 * -AES-ECB
57 * -AES-CFB
58 * -AES-OFB
59 * -AES-CTR
60 * -AES-GCM
61 * -3DES-CBC
62 * -3DES-ECB
63 * -3DES-CFB
64 * -3DES-OFB
65 * -3DES-CTR
66 * -DES-CBC
67 * -DES-ECB
68 * -DES-CFB
69 * -DES-OFB
70 * -DES-CTR
71 *
72 *****************************************************************************************
73 * How to use crypto
74 *****************************************************************************************
75 * Method 1 (use the lowest level API)
76 *****************************************************************************************
77 * -call CRYPTO_Init to open IPSEC function & clock
78 *
79 * -call following API for set key:
80 * -CRYPTO_SetSecurityModeAD
81 *
82 * -call following API for authentication/encrypt/decrypt:
83 * -CRYPTO_ProcessAD
84 *
85 *****************************************************************************************
86 * @endverbatim
87 */
88
89 /* Exported Types --------------------------------------------------------*/
90
91 /** @defgroup CRYPTO_Exported_Types CRYPTO Exported Types
92 * @{
93 */
94
95 /**
96 * @brief CRYPTO source descriptor structure definition
97 */
98 typedef union {
99 struct {
100 u32 key_len:4; /*Offset 0, Bit[3:0], key length */
101 u32 iv_len:4; /*Offset 0, Bit[7:3], IV length */
102 u32 keypad_len:8; /*Offset 0, Bit[15:8], pad length */
103 u32 hash_iv_len:6; /*Offset 0, Bit[21:16], Hash initial value length */
104 u32 ap:2; /*Offset 0, Bit[23:22], auto-padding */
105 u32 cl:2; /*Offset 0, Bit[25:24], Command length */
106 u32 priv_key:1; /*Offset 0, Bit[26], Secure Key */
107 u32 otp_key:1; /*Offset 0, Bit[27], Secure Key */
108 u32 ls:1; /*Offset 0, Bit[28], Last segment descriptor */
109 u32 fs:1; /*Offset 0, Bit[29], First segment descriptor */
110 u32 rs:1; /*Offset 0, Bit[30], Read data source */
111 u32 rsvd:1; /*Offset 0, Bit[31], Reserved */
112 } b;
113
114 struct {
115 u32 apl:8; /*Offset 0, Bit[7:0], Auth padding length */
116 u32 a2eo:5; /*Offset 0, Bit[12:8], Auth to encryption offset */
117 u32 zero:1; /*Offset 0, Bit[13], 0/1 */
118 u32 enl:14; /*Offset 0, Bit[27:14], Encryption data length */
119 u32 ls:1; /*Offset 0, Bit[28], Last segment descriptor */
120 u32 fs:1; /*Offset 0, Bit[29], First segment descriptor */
121 u32 rs:1; /*Offset 0, Bit[30], Read data source */
122 u32 rsvd:1; /*Offset 0, Bit[31], Reserved */
123 } d;
124
125 u32 w;
126 } rtl_crypto_srcdesc_t;
127
128 /**
129 * @brief CRYPTO destination descriptor structure definition
130 */
131 typedef union {
132 struct {
133 u32 adl:8; /*Offset 0, Bit[7:0], Auth data length */
134 u32 rsvd1:19; /*Offset 0, Bit[26:8], Reserved */
135 u32 enc:1; /*Offset 0, Bit[27], Cipher or auth */
136 u32 ls:1; /*Offset 0, Bit[28], Last segment descriptor */
137 u32 fs:1; /*Offset 0, Bit[29], First segment descriptor */
138 u32 ws:1; /*Offset 0, Bit[30], Write data source */
139 u32 rsvd2:1; /*Offset 0, Bit[31], Reserved */
140 } auth;
141
142 struct {
143 u32 enl:24; /*Offset 0, Bit[23:0], Auth padding length */
144 u32 rsvd1:3; /*Offset 0, Bit[26:24], Reserved */
145 u32 enc:1; /*Offset 0, Bit[27], Cipher or auth */
146 u32 ls:1; /*Offset 0, Bit[28], Last segment descriptor */
147 u32 fs:1; /*Offset 0, Bit[29], First segment descriptor */
148 u32 ws:1; /*Offset 0, Bit[30], Write data source */
149 u32 rsvd2:1; /*Offset 0, Bit[31], Reserved */
150 } cipher;
151
152 u32 w;
153 } rtl_crypto_dstdesc_t;
154
155 /**
156 * @brief CRYPTO command buffer structure definition
157 */
158 typedef struct rtl_crypto_cl_struct_s {
159 // offset 0 :
160 u32 cipher_mode:4; /*Offset 0, Bit[3:0], Cipher mode */
161 u32 cipher_eng_sel:2; /*Offset 0, Bit[5:4], Cipher algorithm selected */
162 u32 rsvd1:1; /*Offset 0, Bit[6], Reserved */
163 u32 cipher_encrypt:1; /*Offset 0, Bit[7], Encryption or decryption */
164 u32 aes_key_sel:2; /*Offset 0, Bit[9:8], AES key length */
165 u32 des3_en:1; /*Offset 0, Bit[10], 3DES */
166 u32 des3_type:1; /*Offset 0, Bit[11], 3DES type */
167 u32 ckbs:1; /*Offset 0, Bit[12], Cipher key byte swap */
168 u32 hmac_en:1; /*Offset 0, Bit[13], HMAC */
169 u32 hmac_mode:3; /*Offset 0, Bit[16:14], Hash algorithm */
170 u32 hmac_seq_hash_last:1; /*Offset 0, Bit[17], the last payload(seq hash) */
171 u32 engine_mode:3; /*Offset 0, Bit[20:18], engine mode */
172 u32 hmac_seq_hash_first:1; /*Offset 0, Bit[21], the first payload(seq hash) */
173 u32 hmac_seq_hash:1; /*Offset 0, Bit[22], Seqential hash */
174 u32 hmac_seq_hash_no_wb:1; /*Offset 0, Bit[23], Result hash output */
175 u32 icv_total_length:8; /*Offset 0, Bit[31:24], icv length */
176
177 // offset 4
178 u32 aad_last_data_size:4; /*Offset 4, Bit[3:0], AAD last block data size */
179 u32 enc_last_data_size:4; /*Offset 4, Bit[7:4], Message last block data size */
180 u32 pad_last_data_size:3; /*Offset 4, Bit[10:8], Hash padding last block data size */
181 u32 ckws:1; /*Offset 4, Bit[11], Cipher key word swap */
182 u32 enc_pad_last_data_size:3; /*Offset 4, Bit[14:12], Encryption padding last block data size */
183 u32 hsibs:1; /*Offset 4, Bit[15], Hash sequential initial value byte swap */
184 u32 caws:1; /*Offset 4, Bit[16], Cipher align word swap */
185 u32 cabs:1; /*Offset 4, Bit[17], Cipher align byte swap */
186 u32 ciws:1; /*Offset 4, Bit[18], Cipher input word swap */
187 u32 cibs:1; /*Offset 4, Bit[19], Cipher input byte swap */
188 u32 cows:1; /*Offset 4, Bit[20], Cipher output word swap */
189 u32 cobs:1; /*Offset 4, Bit[21], Cipher output byte swap */
190 u32 codws:1; /*Offset 4, Bit[22], Cipher output double word swap */
191 u32 cidws:1; /*Offset 4, Bit[23], Cipher input double word swap */
192 u32 haws:1; /*Offset 4, Bit[24], Hash align word swap */
193 u32 habs:1; /*Offset 4, Bit[25], Hash align byte swap */
194 u32 hiws:1; /*Offset 4, Bit[26], Hash input word swap */
195 u32 hibs:1; /*Offset 4, Bit[27], Hash input byte swap */
196 u32 hows:1; /*Offset 4, Bit[28], Hash output word swap */
197 u32 hobs:1; /*Offset 4, Bit[29], Hash output byte swap */
198 u32 hkws:1; /*Offset 4, Bit[30], Hash key word swap */
199 u32 hkbs:1; /*Offset 4, Bit[31], Hash key byte swap */
200
201 // offset 8
202 u32 hash_pad_len:8; /*Offset 8, Bit[7:0], Hash padding total length */
203 u32 header_total_len:6; /*Offset 8, Bit[13:8], A2EO total length */
204 u32 apl:2; /*Offset 8, Bit[15:14], Encryption padding total length*/
205 u32 enl:16; /*Offset 8, Bit[15:14], Message total length */
206
207 // offset
208 u32 ap0; /*Offset 12, Bit[31:0], Message length[31:0] */
209 u32 ap1; /*Offset 16, Bit[31:0], Message length[63:32] */
210 u32 ap2; /*Offset 20, Bit[31:0], Message length[95:64] */
211 u32 ap3; /*Offset 24, Bit[31:0], Message length[127:96] */
212 } rtl_crypto_cl_t;
213
214 /**
215 * @brief CRYPTO adapter definition
216 */
217 typedef struct _HAL_CRYPTO_ADAPTER_ {
218 u8 isInit; /*0: not init, 1: init */
219 u8 isIntMode; /*0: disable interrupt mode, 1: enable interrupt mode*/
220
221 u32 cipher_type; /*cipher type */
222 u8 des; /*DES */
223 u8 trides; /*3DES */
224 u8 aes; /*AES */
225 u8 chacha; /*ChaCha */
226 u8 isDecrypt; /*0: encryption, 1: decryption */
227
228 u32 auth_type; /*auth type */
229 u8 isHMAC; /*0: not HMAC, 1: HMAC */
230 u8 isMD5; /*MD5 */
231 u8 isSHA1; /*SHA1 */
232 u8 isSHA2; /*SHA2 */
233 u8 sha2type; /*SHA2 type: SHA2_224/SHA2_256 */
234
235 u32 enc_last_data_size; /*message last data size */
236 u32 aad_last_data_size; /*AAD last data size */
237
238 u32 lenAuthKey; /*Auth key length */
239 const u8* pAuthKey; /*Auth key */
240 u32 digestlen; /*digest */
241
242 // sequential hash
243 u8 hmac_seq_hash_first; /* seq hash the first message payload block */
244 u8 hmac_seq_hash_last; /* seq hash the last message payload block */
245 u32 hmac_seq_hash_total_len; /* seq hash message total length */
246 u8 hmac_seq_is_recorded; /* enter seq hash or not */
247 u8 *hmac_seq_last_message; /* previous message payload */
248 u32 hmac_seq_last_msglen; /* previous message payload length */
249 u8 hmac_seq_buf_is_used_bytes;/* seq buf used bytes(total 64-bytes) */
250
251 u32 lenCipherKey; /*Cipher key length */
252 const u8* pCipherKey; /*Cipher key */
253
254 u32 a2eo, apl_aad, enl, apl; /*length */
255
256 u8 *ipad; /*HMAC ipad */
257 u8 *opad; /*HMAC opad */
258 // crc
259 //int crc_order; /*CRC order */
260
261 volatile u8 g_IOPAD[64*2+4] __attribute__((aligned(4)));
262 volatile u8 gcm_iv[32] __attribute__((aligned(4)));
263 volatile u8 cl_buffer[32] __attribute__((aligned(4)));
264 volatile u8 hmac_seq_buf[64] __attribute__((aligned(4)));
265 } HAL_CRYPTO_ADAPTER, *PHAL_CRYPTO_ADAPTER ;
266 /**
267 * @}
268 */
269
270 /* Exported constants --------------------------------------------------------*/
271 /** @defgroup CRYPTO_Exported_Constants CRYPTO Exported Constants
272 * @{
273 */
274
275 /** @defgroup CRYPTO_LENGTH_definitions
276 * @{
277 */
278 #define CRYPTO_MAX_DIGEST_LENGTH 32 /* SHA256 Digest length : 32 */
279 #define CRYPTO_MAX_KEY_LENGTH 32 /* MAX is AES-256 : 32 byte, 3DES : 24 byte */
280 #define CRYPTO_PADSIZE 64
281 #define CRYPTO_AUTH_PADDING 64
282 #define CRYPTO_MD5_DIGEST_LENGTH 16
283 #define CRYPTO_SHA1_DIGEST_LENGTH 20
284 #define CRYPTO_SHA2_DIGEST_LENGTH 32
285 /**
286 * @}
287 */
288
289 /** @defgroup CRYPTO_ATHENTICATION_TYPE_definitions
290 * @{
291 */
292 #define AUTH_TYPE_NO_AUTH ((u32)-1)
293
294 #define AUTH_TYPE_MASK_FUNC 0x3 /* bit 0, bit 1*/
295 #define AUTH_TYPE_MD5 0x2
296 #define AUTH_TYPE_SHA1 0x0
297 #define AUTH_TYPE_SHA2 0x1
298
299 #define AUTH_TYPE_MASK_HMAC 0x4 /* bit 2 */
300 #define AUTH_TYPE_HMAC_MD5 (AUTH_TYPE_MD5 | AUTH_TYPE_MASK_HMAC)
301 #define AUTH_TYPE_HMAC_SHA1 (AUTH_TYPE_SHA1 | AUTH_TYPE_MASK_HMAC)
302 #define AUTH_TYPE_HMAC_SHA2 (AUTH_TYPE_SHA2 | AUTH_TYPE_MASK_HMAC)
303
304 #define AUTH_TYPE_MASK_FUNC_ALL (AUTH_TYPE_MASK_FUNC| AUTH_TYPE_MASK_HMAC)
305
306 // SHA2
307 #define AUTH_TYPE_MASK_SHA2 0x30 /* bit 3,4 */
308 #define AUTH_TYPE_SHA2_224 0x10
309 #define AUTH_TYPE_SHA2_256 0x20
310
311 #define AUTH_TYPE_SHA2_224_ALL (AUTH_TYPE_SHA2_224|AUTH_TYPE_SHA2)
312 #define AUTH_TYPE_SHA2_256_ALL (AUTH_TYPE_SHA2_256|AUTH_TYPE_SHA2)
313 #define AUTH_TYPE_HMAC_SHA2_224_ALL (AUTH_TYPE_SHA2_224|AUTH_TYPE_HMAC_SHA2)
314 #define AUTH_TYPE_HMAC_SHA2_256_ALL (AUTH_TYPE_SHA2_256|AUTH_TYPE_HMAC_SHA2)
315
316 typedef enum _SHA2_TYPE_ {
317 SHA2_NONE = 0,
318 SHA2_224 = 224/8,
319 SHA2_256 = 256/8,
320 SHA2_384 = 384/8,
321 SHA2_512 = 512/8
322 } SHA2_TYPE;
323 /**
324 * @}
325 */
326
327 /** @defgroup CRYPTO_CIPHER_TYPE_definitions
328 * @{
329 */
330 #define CIPHER_TYPE_NO_CIPHER ((u32)-1)
331
332 #define CIPHER_TYPE_MODE_ENCRYPT 0x80
333
334 #define CIPHER_TYPE_MASK_FUNC 0x30 /* 0x00 : DES, 0x10: 3DES, 0x20: AES */
335 #define CIPHER_TYPE_FUNC_DES 0x00
336 #define CIPHER_TYPE_FUNC_3DES 0x10
337 #define CIPHER_TYPE_FUNC_AES 0x20
338 #define CIPHER_TYPE_FUNC_CHACHA 0x30
339
340 #define CIPHER_TYPE_MASK_BLOCK 0xF /*0x0 : ECB, 0x1: CBC, 0x2: CFB , 0x3 : OFB , 0x4 : CTR, 0x5 : GCTR, 0x6: GMAC, 0x7: GHASH, 0x8: GCM*/
341 #define CIPHER_TYPE_BLOCK_ECB 0x0
342 #define CIPHER_TYPE_BLOCK_CBC 0x1
343 #define CIPHER_TYPE_BLOCK_CFB 0x2
344 #define CIPHER_TYPE_BLOCK_OFB 0x3
345 #define CIPHER_TYPE_BLOCK_CTR 0x4
346 #define CIPHER_TYPE_BLOCK_GCTR 0x5
347 #define CIPHER_TYPE_BLOCK_GMAC 0x6
348 #define CIPHER_TYPE_BLOCK_GHASH 0x7
349 #define CIPHER_TYPE_BLOCK_GCM 0x8
350 #define CIPHER_TYPE_BLOCK_CHACHA 0x1
351 //
352 #define CIPHER_TYPE_DES_ECB 0x0
353 #define CIPHER_TYPE_DES_CBC 0x1
354 #define CIPHER_TYPE_DES_CFB 0x2
355 #define CIPHER_TYPE_DES_OFB 0x3
356 #define CIPHER_TYPE_DES_CTR 0x4
357 #define CIPHER_TYPE_3DES_ECB 0x10
358 #define CIPHER_TYPE_3DES_CBC 0x11
359 #define CIPHER_TYPE_3DES_CFB 0x12
360 #define CIPHER_TYPE_3DES_OFB 0x13
361 #define CIPHER_TYPE_3DES_CTR 0x14
362 #define CIPHER_TYPE_AES_ECB 0x20
363 #define CIPHER_TYPE_AES_CBC 0x21
364 #define CIPHER_TYPE_AES_CFB 0x22
365 #define CIPHER_TYPE_AES_OFB 0x23
366 #define CIPHER_TYPE_AES_CTR 0x24 // 0x29
367 #define CIPHER_TYPE_AES_GCTR 0x25
368 #define CIPHER_TYPE_AES_GMAC 0x26
369 #define CIPHER_TYPE_AES_GHASH 0x27
370 #define CIPHER_TYPE_AES_GCM 0x28
371
372 #define CIPHER_TYPE_CHACHA_POLY1305 0x30 // chacha+poly1305
373 #define CIPHER_TYPE_CHACHA 0x31
374 #define CIPHER_TYPE_POLY1305 0x33 // poly1305 - mode 2
375
376 /**
377 * @}
378 */
379
380 /**
381 * @}
382 */
383
384 /* Exported functions --------------------------------------------------------*/
385 /**************************************************************************//**
386 * @defgroup CRYPTO_Exported_Functions CRYPTO Exported Functions
387 * @{
388 *****************************************************************************/
389
390 /** @defgroup Crypto_Normal_Functions
391 * @{
392 */
393 _LONG_CALL_ void CRYPTO_MemDump(const u8 *start, u32 size, char * strHeader);
394 _LONG_CALL_ void CRYPTO_RegDump(void);
395 _LONG_CALL_ void CRYPTO_CleanCmdOk(void);
396 _LONG_CALL_ void CRYPTO_ClearAllINT(void);
397 _LONG_CALL_ void CRYPTO_Reset(HAL_CRYPTO_ADAPTER *pIE);
398 _LONG_CALL_ int CRYPTO_SetSecurityModeAD(HAL_CRYPTO_ADAPTER *pIE, IN const u32 cipher_type, IN const u32 auth_type,IN const void* pCipherKey, IN const u32 lenCipherKey, IN const void* pAuthKey, IN const u32 lenAuthKey);
399 _LONG_CALL_ int CRYPTO_Init(HAL_CRYPTO_ADAPTER *pIE);
400 _LONG_CALL_ int CRYPTO_ProcessAD(HAL_CRYPTO_ADAPTER *pIE, IN const u8 *message, IN const u32 msglen, IN const u8 *pIv, IN const u32 ivlen, IN const u8 *paad, IN const u32 aadlen, OUT u8 *pResult, OUT u8 *pTag);
401 _LONG_CALL_ int CRYPTO_CipherInit(HAL_CRYPTO_ADAPTER *pIE, IN const u32 cipher_type, IN const u8 *key, IN const u32 keylen);
402 _LONG_CALL_ int CRYPTO_CipherEncryptAD(HAL_CRYPTO_ADAPTER *pIE, IN const u8* message, IN const u32 msglen, IN const u8* piv, IN const u32 ivlen, IN const u8* paad, IN const u32 aadlen, OUT u8* pResult, OUT u8* pTag);
403 _LONG_CALL_ int CRYPTO_CipherDecryptAD(HAL_CRYPTO_ADAPTER *pIE, IN const u8* message, IN const u32 msglen, IN const u8* piv, IN const u32 ivlen, IN const u8* paad, IN const u32 aadlen, OUT u8* pResult, OUT u8* pTag);
404 _LONG_CALL_ int CRYPTO_SendSeqBuf(u8 *pDigest);
405 /**
406 * @}
407 */
408
409 /**
410 * @}
411 */
412
413 /* Registers Definitions --------------------------------------------------------*/
414 /**************************************************************************//**
415 * @defgroup CRYPTO_Register_Definitions CRYPTO Register Definitions
416 * @{
417 *****************************************************************************/
418
419 /**************************************************************************//**
420 * @defgroup CRYPTO_SDSR
421 * @{
422 *****************************************************************************/
423 #define SFIFO_EMPTY_CNT ((u32)0x000000FF) /* Bit[7:0], Source Descriptor FIFO empty counter */
424 #define SWPTR ((u32)0x0000FF00) /* Bit[15:8], Source Descriptor FIFO write pointer */
425 #define SRPTR ((u32)0x00FF0000) /* Bit[23:16], Source Descriptor FIFO read pointer */
426 #define SRC_FAIL ((u32)0x00000001<<24) /* Bit[24], Source Descriptor fail interrupt */
427 #define SRC_FAIL_STATUS ((u32)0x00000003<<25) /* Bit[26:25], Source Descriptor fail status */
428 #define SRC_FAIL_M ((u32)0x00000001<<27) /* Bit[27], Source Descriptor fail interrupt mask */
429 #define PK_UP ((u32)0x00000001<<30) /* Bit[30], packet base update wptr to engine */
430 #define SRC_RST ((u32)0x00000001<<31) /* Bit[31], Source Descriptor reset(only for pk_up=1'b1) */
431 /** @} */
432
433 /**************************************************************************//**
434 * @defgroup CRYPTO_RST_ISR_CON
435 * @{
436 *****************************************************************************/
437 #define SOFT_RST ((u32)0x00000001) /* Bit[0], Software Reset write 1 to reset */
438 #define DMA_BUSY ((u32)0x00000001<<3) /* Bit[3], Ipsec dma busy */
439 #define CMD_OK ((u32)0x00000001<<4) /* Bit[4], Command OK interrupt */
440 #define INTR_MODE ((u32)0x00000001<<7) /* Bit[7], Select ok interrupt mode */
441 #define INTR_NORMAL_MODE ((u32)0x00000000<<7) /* Bit[7], interrupt normal mode */
442 #define INTR_COUNT_MODE ((u32)0x00000001<<7) /* Bit[7], interrupt counter mode */
443 #define OK_INTR_CNT ((u32)0x000000FF<<8) /* Bit[15:8], OK interrupt counter */
444 #define CLEAR_OK_INTR_NUM ((u32)0x000000FF<<16) /* Bit[23:16], Clear OK interrupt number */
445 #define IPSEC_RST ((u32)0x00000001<<31) /* Bit[31], Ipsec engine Reset Write 1 to reset the crypto engine and DMA engine */
446 /** @} */
447
448 /**************************************************************************//**
449 * @defgroup CRYPTO_IMR
450 * @{
451 *****************************************************************************/
452 #define CMD_OK_M ((u32)0x00000001) /* Bit[0], Command OK interrupt Mask */
453 #define SRC_ERR0_M ((u32)0x00000001<<3) /* Bit[3], Source Descriptor Error 0 Interrupt Mask */
454 #define SRC_ERR1_M ((u32)0x00000001<<4) /* Bit[4], Source Descriptor Error 1 Interrupt Mask */
455 #define SRC_ERR2_M ((u32)0x00000001<<5) /* Bit[5], Source Descriptor Error 2 Interrupt Mask */
456 #define SRC_ERR3_M ((u32)0x00000001<<6) /* Bit[6], Source Descriptor Error 3 Interrupt Mask */
457 #define SRC_ERR4_M ((u32)0x00000001<<7) /* Bit[7], Source Descriptor Error 4 Interrupt Mask */
458 #define SRC_ERR5_M ((u32)0x00000001<<8) /* Bit[8], Source Descriptor Error 5 Interrupt Mask */
459 #define SRC_ERR6_M ((u32)0x00000001<<9) /* Bit[9], Source Descriptor Error 6 Interrupt Mask */
460 #define SRC_ERR7_M ((u32)0x00000001<<10) /* Bit[10], Source Descriptor Error 7 Interrupt Mask */
461 #define SRC_ERR8_M ((u32)0x00000001<<11) /* Bit[11], Source Descriptor Error 8 Interrupt Mask */
462 #define SRC_ERR9_M ((u32)0x00000001<<12) /* Bit[12], Source Descriptor Error 9 Interrupt Mask */
463 #define DST_ERR1_M ((u32)0x00000001<<13) /* Bit[13], Destination Descriptor Error 1 Interrupt Mask */
464 #define DST_ERR2_M ((u32)0x00000001<<14) /* Bit[14], Destination Descriptor Error 2 Interrupt Mask */
465 #define DST_ERR3_M ((u32)0x00000001<<15) /* Bit[15], Destination Descriptor Error 3 Interrupt Mask */
466 #define DST_ERR4_M ((u32)0x00000001<<16) /* Bit[16], Destination Descriptor Error 4 Interrupt Mask */
467 #define DST_ERR5_M ((u32)0x00000001<<17) /* Bit[17], Destination Descriptor Error 5 Interrupt Mask */
468 #define DST_ERR6_M ((u32)0x00000001<<18) /* Bit[18], Destination Descriptor Error 6 Interrupt Mask */
469 /** @} */
470
471 /**************************************************************************//**
472 * @defgroup CRYPTO_DEBUG
473 * @{
474 *****************************************************************************/
475 #define DMA_WAIT_CYCLE ((u32)0x0000FFFF) /* Bit[15:0], Wait dma_wait_cycle to assert next dma request */
476 #define ARBITER_MODE ((u32)0x00000001<<16) /* Bit[16], dma arbiter mode */
477 #define DEBUG_PORT_SEL ((u32)0x0000000F<<20) /* Bit[23:20], dma arbiter mode */
478 #define ENGINE_CLK_EN ((u32)0x00000001<<24) /* Bit[24], Ipsec Engine clock enable */
479 #define DEBUG_WB ((u32)0x00000001<<31) /* Bit[31], Debug : write back mode */
480 /** @} */
481 /**************************************************************************//**
482 * @defgroup CRYPTO_ERR_STAT
483 * @{
484 *****************************************************************************/
485 #define SRC_ERR0 ((u32)0x00000001) /* Bit[0], Source Descriptor Error 0 interrupt */
486 #define SRC_ERR1 ((u32)0x00000001<<1) /* Bit[1], Source Descriptor Error 1 interrupt */
487 #define SRC_ERR2 ((u32)0x00000001<<2) /* Bit[2], Source Descriptor Error 2 interrupt */
488 #define SRC_ERR3 ((u32)0x00000001<<3) /* Bit[3], Source Descriptor Error 3 interrupt */
489 #define SRC_ERR4 ((u32)0x00000001<<4) /* Bit[4], Source Descriptor Error 4 interrupt */
490 #define SRC_ERR5 ((u32)0x00000001<<5) /* Bit[5], Source Descriptor Error 5 interrupt */
491 #define SRC_ERR6 ((u32)0x00000001<<6) /* Bit[6], Source Descriptor Error 6 interrupt */
492 #define SRC_ERR7 ((u32)0x00000001<<7) /* Bit[7], Source Descriptor Error 7 interrupt */
493 #define SRC_ERR8 ((u32)0x00000001<<8) /* Bit[8], Source Descriptor Error 8 interrupt */
494 #define SRC_ERR9 ((u32)0x00000001<<9) /* Bit[9], Source Descriptor Error 9 interrupt */
495 #define DST_ERR1 ((u32)0x00000001<<10) /* Bit[10], Destination Descriptor Error 1 interrupt */
496 #define DST_ERR2 ((u32)0x00000001<<11) /* Bit[11], Destination Descriptor Error 2 interrupt */
497 #define DST_ERR3 ((u32)0x00000001<<12) /* Bit[12], Destination Descriptor Error 2 interrupt */
498 #define DST_ERR4 ((u32)0x00000001<<13) /* Bit[13], Destination Descriptor Error 4 interrupt */
499 #define DST_ERR5 ((u32)0x00000001<<14) /* Bit[14], Destination Descriptor Error 5 interrupt */
500 #define DST_ERR6 ((u32)0x00000001<<15) /* Bit[15], Destination Descriptor Error 6 interrupt */
501 /** @} */
502
503 /**************************************************************************//**
504 * @defgroup CRYPTO_SWAP_BURST
505 * @{
506 *****************************************************************************/
507 #define SET_SWAP ((u32)0x00000001) /* Bit[0], Byte swap for command setting data */
508 #define KEY_IV_SWAP ((u32)0x00000001<<1) /* Bit[1], Byte swap for key and iv */
509 #define KEY_PAD_SWAP ((u32)0x00000001<<2) /* Bit[2], Byte swap for hmac key */
510 #define HASH_INITIAL_VALUE_SWAP ((u32)0x00000001<<3) /* Bit[3], Byte swap for sequential hash initial value */
511 #define DMA_IN_LITTLE_ENDIAN ((u32)0x00000001<<4) /* Bit[4], Input data is little endian */
512 #define TX_BYTE_SWAP ((u32)0x00000001<<8) /* Bit[8], Byte swap for dma_tx engine input data */
513 #define DATA_OUT_LITTLE_ENDIAN ((u32)0x00000001<<9) /* Bit[9], Output data is little endian */
514 #define MAC_OUT_LITTLE_ENDIAN ((u32)0x00000001<<10) /* Bit[10], Output mac is little endian */
515 #define RX_WD_SWAP ((u32)0x00000001<<11) /* Bit[11], Word swap for dma_rx engine input data */
516 #define TX_WD_SWAP ((u32)0x00000001<<12) /* Bit[12], Word swap for dma_tx engine input data */
517 #define DMA_BURST_LENGTH ((u32)0x0000003F<<16) /* Bit[21:16], dma burst length */
518 /** @} */
519
520 /**************************************************************************//**
521 * @defgroup CRYPTO_DDSR
522 * @{
523 *****************************************************************************/
524 #define DFIFO_EMPTY_CNT ((u32)0x000000FF) /* Bit[7:0], Destination Descriptor FIFO empty counter */
525 #define DWPTR ((u32)0x0000FF00) /* Bit[15:8], Destination Descriptor FIFO write pointer */
526 #define DRPTR ((u32)0x00FF0000) /* Bit[23:16], Destination Descriptor FIFO read pointer */
527 #define DST_FAIL ((u32)0x00000001<<24) /* Bit[24], Destination Descriptor fail interrupt */
528 #define DST_FAIL_STATUS ((u32)0x00000003<<25) /* Bit[26:25], Destination Descriptor fail status */
529 #define DST_FAIL_M ((u32)0x00000001<<27) /* Bit[27], Destination Descriptor fail interrupt mask */
530 #define DST_RST ((u32)0x00000001<<31) /* Bit[31], Destination Descriptor reset(only for pk_up=1'b1) */
531 /** @} */
532
533 /**************************************************************************//**
534 * @defgroup CRYPTO_DESC_PKT_CONF
535 * @{
536 *****************************************************************************/
537 /******************** Bits definition for register *******************/
538 #define DBG_SPTR (u32)0x000000FF) /* Bit[7:0], Source Descriptor FIFO empty counter */
539 #define DBG_DPTR (u32)0x0000FF00) /* Bit[15:8], Destination Descriptor FIFO write pointer */
540 #define PK_ARBITER ((u32)0x00000003<<16) /* Bit[17:16], Packet arbiter */
541 #define BUS1_PRIORITY_TH ((u32)0x00000003<<24) /* Bit[25:24], Bus1 priority threshold */
542 #define BUS2_PRIORITY_TH ((u32)0x00000003<<26) /* Bit[27:26], Bus2 priority threshold */
543 #define PK_ARBITER_MODE ((u32)0x00000003<<30) /* Bit[31:30], Packet arbiter mode */
544 /** @} */
545
546 /** @} */
547
548 /**
549 * @}
550 */
551
552 /**
553 * @}
554 */
555
556 /* Other Definitions --------------------------------------------------------*/
557 #define FIFOCNT_TIMEOUT 0x100000
558 extern HAL_CRYPTO_ADAPTER crypto_engine;
559
560 __STATIC_INLINE
rtl_cryptoEngine_init(void)561 int rtl_cryptoEngine_init(void)
562 {
563 return CRYPTO_Init(NULL);
564 }
565
566 /* *** dump macro definition *** */
567 #undef crypto_dbg_mem_dump
568 #define crypto_dbg_mem_dump(start, size, str_header) \
569 if (ConfigDebug[LEVEL_INFO] & BIT(MODULE_IPSEC)) { \
570 DiagPrintf("%s(): memdump : address: %08x, size: %d\n", "rtl_cryptoEngine_dbg", start, size); \
571 CRYPTO_MemDump((const u8*)(start), size, (char*)(str_header)); \
572 }
573 #endif
574 /******************* (C) COPYRIGHT 2017 Realtek Semiconductor *****END OF FILE****/
575
576