1 /** 2 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 // ============================================================================= 7 // Register block : SIO 8 // Version : 1 9 // Bus type : apb 10 // Description : Single-cycle IO block 11 // Provides core-local and inter-core hardware for the two 12 // processors, with single-cycle access. 13 // ============================================================================= 14 #ifndef HARDWARE_REGS_SIO_DEFINED 15 #define HARDWARE_REGS_SIO_DEFINED 16 // ============================================================================= 17 // Register : SIO_CPUID 18 // Description : Processor core identifier 19 // Value is 0 when read from processor core 0, and 1 when read 20 // from processor core 1. 21 #define SIO_CPUID_OFFSET 0x00000000 22 #define SIO_CPUID_BITS 0xffffffff 23 #define SIO_CPUID_RESET "-" 24 #define SIO_CPUID_MSB 31 25 #define SIO_CPUID_LSB 0 26 #define SIO_CPUID_ACCESS "RO" 27 // ============================================================================= 28 // Register : SIO_GPIO_IN 29 // Description : Input value for GPIO pins 30 // Input value for GPIO0...29 31 #define SIO_GPIO_IN_OFFSET 0x00000004 32 #define SIO_GPIO_IN_BITS 0x3fffffff 33 #define SIO_GPIO_IN_RESET 0x00000000 34 #define SIO_GPIO_IN_MSB 29 35 #define SIO_GPIO_IN_LSB 0 36 #define SIO_GPIO_IN_ACCESS "RO" 37 // ============================================================================= 38 // Register : SIO_GPIO_HI_IN 39 // Description : Input value for QSPI pins 40 // Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, 41 // SD3 42 #define SIO_GPIO_HI_IN_OFFSET 0x00000008 43 #define SIO_GPIO_HI_IN_BITS 0x0000003f 44 #define SIO_GPIO_HI_IN_RESET 0x00000000 45 #define SIO_GPIO_HI_IN_MSB 5 46 #define SIO_GPIO_HI_IN_LSB 0 47 #define SIO_GPIO_HI_IN_ACCESS "RO" 48 // ============================================================================= 49 // Register : SIO_GPIO_OUT 50 // Description : GPIO output value 51 // Set output level (1/0 -> high/low) for GPIO0...29. 52 // Reading back gives the last value written, NOT the input value 53 // from the pins. 54 // If core 0 and core 1 both write to GPIO_OUT simultaneously (or 55 // to a SET/CLR/XOR alias), 56 // the result is as though the write from core 0 took place first, 57 // and the write from core 1 was then applied to that intermediate 58 // result. 59 #define SIO_GPIO_OUT_OFFSET 0x00000010 60 #define SIO_GPIO_OUT_BITS 0x3fffffff 61 #define SIO_GPIO_OUT_RESET 0x00000000 62 #define SIO_GPIO_OUT_MSB 29 63 #define SIO_GPIO_OUT_LSB 0 64 #define SIO_GPIO_OUT_ACCESS "RW" 65 // ============================================================================= 66 // Register : SIO_GPIO_OUT_SET 67 // Description : GPIO output value set 68 // Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` 69 #define SIO_GPIO_OUT_SET_OFFSET 0x00000014 70 #define SIO_GPIO_OUT_SET_BITS 0x3fffffff 71 #define SIO_GPIO_OUT_SET_RESET 0x00000000 72 #define SIO_GPIO_OUT_SET_MSB 29 73 #define SIO_GPIO_OUT_SET_LSB 0 74 #define SIO_GPIO_OUT_SET_ACCESS "RW" 75 // ============================================================================= 76 // Register : SIO_GPIO_OUT_CLR 77 // Description : GPIO output value clear 78 // Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= 79 // ~wdata` 80 #define SIO_GPIO_OUT_CLR_OFFSET 0x00000018 81 #define SIO_GPIO_OUT_CLR_BITS 0x3fffffff 82 #define SIO_GPIO_OUT_CLR_RESET 0x00000000 83 #define SIO_GPIO_OUT_CLR_MSB 29 84 #define SIO_GPIO_OUT_CLR_LSB 0 85 #define SIO_GPIO_OUT_CLR_ACCESS "RW" 86 // ============================================================================= 87 // Register : SIO_GPIO_OUT_XOR 88 // Description : GPIO output value XOR 89 // Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= 90 // wdata` 91 #define SIO_GPIO_OUT_XOR_OFFSET 0x0000001c 92 #define SIO_GPIO_OUT_XOR_BITS 0x3fffffff 93 #define SIO_GPIO_OUT_XOR_RESET 0x00000000 94 #define SIO_GPIO_OUT_XOR_MSB 29 95 #define SIO_GPIO_OUT_XOR_LSB 0 96 #define SIO_GPIO_OUT_XOR_ACCESS "RW" 97 // ============================================================================= 98 // Register : SIO_GPIO_OE 99 // Description : GPIO output enable 100 // Set output enable (1/0 -> output/input) for GPIO0...29. 101 // Reading back gives the last value written. 102 // If core 0 and core 1 both write to GPIO_OE simultaneously (or 103 // to a SET/CLR/XOR alias), 104 // the result is as though the write from core 0 took place first, 105 // and the write from core 1 was then applied to that intermediate 106 // result. 107 #define SIO_GPIO_OE_OFFSET 0x00000020 108 #define SIO_GPIO_OE_BITS 0x3fffffff 109 #define SIO_GPIO_OE_RESET 0x00000000 110 #define SIO_GPIO_OE_MSB 29 111 #define SIO_GPIO_OE_LSB 0 112 #define SIO_GPIO_OE_ACCESS "RW" 113 // ============================================================================= 114 // Register : SIO_GPIO_OE_SET 115 // Description : GPIO output enable set 116 // Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` 117 #define SIO_GPIO_OE_SET_OFFSET 0x00000024 118 #define SIO_GPIO_OE_SET_BITS 0x3fffffff 119 #define SIO_GPIO_OE_SET_RESET 0x00000000 120 #define SIO_GPIO_OE_SET_MSB 29 121 #define SIO_GPIO_OE_SET_LSB 0 122 #define SIO_GPIO_OE_SET_ACCESS "RW" 123 // ============================================================================= 124 // Register : SIO_GPIO_OE_CLR 125 // Description : GPIO output enable clear 126 // Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= 127 // ~wdata` 128 #define SIO_GPIO_OE_CLR_OFFSET 0x00000028 129 #define SIO_GPIO_OE_CLR_BITS 0x3fffffff 130 #define SIO_GPIO_OE_CLR_RESET 0x00000000 131 #define SIO_GPIO_OE_CLR_MSB 29 132 #define SIO_GPIO_OE_CLR_LSB 0 133 #define SIO_GPIO_OE_CLR_ACCESS "RW" 134 // ============================================================================= 135 // Register : SIO_GPIO_OE_XOR 136 // Description : GPIO output enable XOR 137 // Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= 138 // wdata` 139 #define SIO_GPIO_OE_XOR_OFFSET 0x0000002c 140 #define SIO_GPIO_OE_XOR_BITS 0x3fffffff 141 #define SIO_GPIO_OE_XOR_RESET 0x00000000 142 #define SIO_GPIO_OE_XOR_MSB 29 143 #define SIO_GPIO_OE_XOR_LSB 0 144 #define SIO_GPIO_OE_XOR_ACCESS "RW" 145 // ============================================================================= 146 // Register : SIO_GPIO_HI_OUT 147 // Description : QSPI output value 148 // Set output level (1/0 -> high/low) for QSPI IO0...5. 149 // Reading back gives the last value written, NOT the input value 150 // from the pins. 151 // If core 0 and core 1 both write to GPIO_HI_OUT simultaneously 152 // (or to a SET/CLR/XOR alias), 153 // the result is as though the write from core 0 took place first, 154 // and the write from core 1 was then applied to that intermediate 155 // result. 156 #define SIO_GPIO_HI_OUT_OFFSET 0x00000030 157 #define SIO_GPIO_HI_OUT_BITS 0x0000003f 158 #define SIO_GPIO_HI_OUT_RESET 0x00000000 159 #define SIO_GPIO_HI_OUT_MSB 5 160 #define SIO_GPIO_HI_OUT_LSB 0 161 #define SIO_GPIO_HI_OUT_ACCESS "RW" 162 // ============================================================================= 163 // Register : SIO_GPIO_HI_OUT_SET 164 // Description : QSPI output value set 165 // Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= 166 // wdata` 167 #define SIO_GPIO_HI_OUT_SET_OFFSET 0x00000034 168 #define SIO_GPIO_HI_OUT_SET_BITS 0x0000003f 169 #define SIO_GPIO_HI_OUT_SET_RESET 0x00000000 170 #define SIO_GPIO_HI_OUT_SET_MSB 5 171 #define SIO_GPIO_HI_OUT_SET_LSB 0 172 #define SIO_GPIO_HI_OUT_SET_ACCESS "RW" 173 // ============================================================================= 174 // Register : SIO_GPIO_HI_OUT_CLR 175 // Description : QSPI output value clear 176 // Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT 177 // &= ~wdata` 178 #define SIO_GPIO_HI_OUT_CLR_OFFSET 0x00000038 179 #define SIO_GPIO_HI_OUT_CLR_BITS 0x0000003f 180 #define SIO_GPIO_HI_OUT_CLR_RESET 0x00000000 181 #define SIO_GPIO_HI_OUT_CLR_MSB 5 182 #define SIO_GPIO_HI_OUT_CLR_LSB 0 183 #define SIO_GPIO_HI_OUT_CLR_ACCESS "RW" 184 // ============================================================================= 185 // Register : SIO_GPIO_HI_OUT_XOR 186 // Description : QSPI output value XOR 187 // Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT 188 // ^= wdata` 189 #define SIO_GPIO_HI_OUT_XOR_OFFSET 0x0000003c 190 #define SIO_GPIO_HI_OUT_XOR_BITS 0x0000003f 191 #define SIO_GPIO_HI_OUT_XOR_RESET 0x00000000 192 #define SIO_GPIO_HI_OUT_XOR_MSB 5 193 #define SIO_GPIO_HI_OUT_XOR_LSB 0 194 #define SIO_GPIO_HI_OUT_XOR_ACCESS "RW" 195 // ============================================================================= 196 // Register : SIO_GPIO_HI_OE 197 // Description : QSPI output enable 198 // Set output enable (1/0 -> output/input) for QSPI IO0...5. 199 // Reading back gives the last value written. 200 // If core 0 and core 1 both write to GPIO_HI_OE simultaneously 201 // (or to a SET/CLR/XOR alias), 202 // the result is as though the write from core 0 took place first, 203 // and the write from core 1 was then applied to that intermediate 204 // result. 205 #define SIO_GPIO_HI_OE_OFFSET 0x00000040 206 #define SIO_GPIO_HI_OE_BITS 0x0000003f 207 #define SIO_GPIO_HI_OE_RESET 0x00000000 208 #define SIO_GPIO_HI_OE_MSB 5 209 #define SIO_GPIO_HI_OE_LSB 0 210 #define SIO_GPIO_HI_OE_ACCESS "RW" 211 // ============================================================================= 212 // Register : SIO_GPIO_HI_OE_SET 213 // Description : QSPI output enable set 214 // Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= 215 // wdata` 216 #define SIO_GPIO_HI_OE_SET_OFFSET 0x00000044 217 #define SIO_GPIO_HI_OE_SET_BITS 0x0000003f 218 #define SIO_GPIO_HI_OE_SET_RESET 0x00000000 219 #define SIO_GPIO_HI_OE_SET_MSB 5 220 #define SIO_GPIO_HI_OE_SET_LSB 0 221 #define SIO_GPIO_HI_OE_SET_ACCESS "RW" 222 // ============================================================================= 223 // Register : SIO_GPIO_HI_OE_CLR 224 // Description : QSPI output enable clear 225 // Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= 226 // ~wdata` 227 #define SIO_GPIO_HI_OE_CLR_OFFSET 0x00000048 228 #define SIO_GPIO_HI_OE_CLR_BITS 0x0000003f 229 #define SIO_GPIO_HI_OE_CLR_RESET 0x00000000 230 #define SIO_GPIO_HI_OE_CLR_MSB 5 231 #define SIO_GPIO_HI_OE_CLR_LSB 0 232 #define SIO_GPIO_HI_OE_CLR_ACCESS "RW" 233 // ============================================================================= 234 // Register : SIO_GPIO_HI_OE_XOR 235 // Description : QSPI output enable XOR 236 // Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE 237 // ^= wdata` 238 #define SIO_GPIO_HI_OE_XOR_OFFSET 0x0000004c 239 #define SIO_GPIO_HI_OE_XOR_BITS 0x0000003f 240 #define SIO_GPIO_HI_OE_XOR_RESET 0x00000000 241 #define SIO_GPIO_HI_OE_XOR_MSB 5 242 #define SIO_GPIO_HI_OE_XOR_LSB 0 243 #define SIO_GPIO_HI_OE_XOR_ACCESS "RW" 244 // ============================================================================= 245 // Register : SIO_FIFO_ST 246 // Description : Status register for inter-core FIFOs (mailboxes). 247 // There is one FIFO in the core 0 -> core 1 direction, and one 248 // core 1 -> core 0. Both are 32 bits wide and 8 words deep. 249 // Core 0 can see the read side of the 1->0 FIFO (RX), and the 250 // write side of 0->1 FIFO (TX). 251 // Core 1 can see the read side of the 0->1 FIFO (RX), and the 252 // write side of 1->0 FIFO (TX). 253 // The SIO IRQ for each core is the logical OR of the VLD, WOF and 254 // ROE fields of its FIFO_ST register. 255 #define SIO_FIFO_ST_OFFSET 0x00000050 256 #define SIO_FIFO_ST_BITS 0x0000000f 257 #define SIO_FIFO_ST_RESET 0x00000002 258 // ----------------------------------------------------------------------------- 259 // Field : SIO_FIFO_ST_ROE 260 // Description : Sticky flag indicating the RX FIFO was read when empty. This 261 // read was ignored by the FIFO. 262 #define SIO_FIFO_ST_ROE_RESET 0x0 263 #define SIO_FIFO_ST_ROE_BITS 0x00000008 264 #define SIO_FIFO_ST_ROE_MSB 3 265 #define SIO_FIFO_ST_ROE_LSB 3 266 #define SIO_FIFO_ST_ROE_ACCESS "WC" 267 // ----------------------------------------------------------------------------- 268 // Field : SIO_FIFO_ST_WOF 269 // Description : Sticky flag indicating the TX FIFO was written when full. This 270 // write was ignored by the FIFO. 271 #define SIO_FIFO_ST_WOF_RESET 0x0 272 #define SIO_FIFO_ST_WOF_BITS 0x00000004 273 #define SIO_FIFO_ST_WOF_MSB 2 274 #define SIO_FIFO_ST_WOF_LSB 2 275 #define SIO_FIFO_ST_WOF_ACCESS "WC" 276 // ----------------------------------------------------------------------------- 277 // Field : SIO_FIFO_ST_RDY 278 // Description : Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR 279 // is ready for more data) 280 #define SIO_FIFO_ST_RDY_RESET 0x1 281 #define SIO_FIFO_ST_RDY_BITS 0x00000002 282 #define SIO_FIFO_ST_RDY_MSB 1 283 #define SIO_FIFO_ST_RDY_LSB 1 284 #define SIO_FIFO_ST_RDY_ACCESS "RO" 285 // ----------------------------------------------------------------------------- 286 // Field : SIO_FIFO_ST_VLD 287 // Description : Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD 288 // is valid) 289 #define SIO_FIFO_ST_VLD_RESET 0x0 290 #define SIO_FIFO_ST_VLD_BITS 0x00000001 291 #define SIO_FIFO_ST_VLD_MSB 0 292 #define SIO_FIFO_ST_VLD_LSB 0 293 #define SIO_FIFO_ST_VLD_ACCESS "RO" 294 // ============================================================================= 295 // Register : SIO_FIFO_WR 296 // Description : Write access to this core's TX FIFO 297 #define SIO_FIFO_WR_OFFSET 0x00000054 298 #define SIO_FIFO_WR_BITS 0xffffffff 299 #define SIO_FIFO_WR_RESET 0x00000000 300 #define SIO_FIFO_WR_MSB 31 301 #define SIO_FIFO_WR_LSB 0 302 #define SIO_FIFO_WR_ACCESS "WF" 303 // ============================================================================= 304 // Register : SIO_FIFO_RD 305 // Description : Read access to this core's RX FIFO 306 #define SIO_FIFO_RD_OFFSET 0x00000058 307 #define SIO_FIFO_RD_BITS 0xffffffff 308 #define SIO_FIFO_RD_RESET "-" 309 #define SIO_FIFO_RD_MSB 31 310 #define SIO_FIFO_RD_LSB 0 311 #define SIO_FIFO_RD_ACCESS "RF" 312 // ============================================================================= 313 // Register : SIO_SPINLOCK_ST 314 // Description : Spinlock state 315 // A bitmap containing the state of all 32 spinlocks (1=locked). 316 // Mainly intended for debugging. 317 #define SIO_SPINLOCK_ST_OFFSET 0x0000005c 318 #define SIO_SPINLOCK_ST_BITS 0xffffffff 319 #define SIO_SPINLOCK_ST_RESET 0x00000000 320 #define SIO_SPINLOCK_ST_MSB 31 321 #define SIO_SPINLOCK_ST_LSB 0 322 #define SIO_SPINLOCK_ST_ACCESS "RO" 323 // ============================================================================= 324 // Register : SIO_DIV_UDIVIDEND 325 // Description : Divider unsigned dividend 326 // Write to the DIVIDEND operand of the divider, i.e. the p in `p 327 // / q`. 328 // Any operand write starts a new calculation. The results appear 329 // in QUOTIENT, REMAINDER. 330 // UDIVIDEND/SDIVIDEND are aliases of the same internal register. 331 // The U alias starts an 332 // unsigned calculation, and the S alias starts a signed 333 // calculation. 334 #define SIO_DIV_UDIVIDEND_OFFSET 0x00000060 335 #define SIO_DIV_UDIVIDEND_BITS 0xffffffff 336 #define SIO_DIV_UDIVIDEND_RESET 0x00000000 337 #define SIO_DIV_UDIVIDEND_MSB 31 338 #define SIO_DIV_UDIVIDEND_LSB 0 339 #define SIO_DIV_UDIVIDEND_ACCESS "RW" 340 // ============================================================================= 341 // Register : SIO_DIV_UDIVISOR 342 // Description : Divider unsigned divisor 343 // Write to the DIVISOR operand of the divider, i.e. the q in `p / 344 // q`. 345 // Any operand write starts a new calculation. The results appear 346 // in QUOTIENT, REMAINDER. 347 // UDIVIDEND/SDIVIDEND are aliases of the same internal register. 348 // The U alias starts an 349 // unsigned calculation, and the S alias starts a signed 350 // calculation. 351 #define SIO_DIV_UDIVISOR_OFFSET 0x00000064 352 #define SIO_DIV_UDIVISOR_BITS 0xffffffff 353 #define SIO_DIV_UDIVISOR_RESET 0x00000000 354 #define SIO_DIV_UDIVISOR_MSB 31 355 #define SIO_DIV_UDIVISOR_LSB 0 356 #define SIO_DIV_UDIVISOR_ACCESS "RW" 357 // ============================================================================= 358 // Register : SIO_DIV_SDIVIDEND 359 // Description : Divider signed dividend 360 // The same as UDIVIDEND, but starts a signed calculation, rather 361 // than unsigned. 362 #define SIO_DIV_SDIVIDEND_OFFSET 0x00000068 363 #define SIO_DIV_SDIVIDEND_BITS 0xffffffff 364 #define SIO_DIV_SDIVIDEND_RESET 0x00000000 365 #define SIO_DIV_SDIVIDEND_MSB 31 366 #define SIO_DIV_SDIVIDEND_LSB 0 367 #define SIO_DIV_SDIVIDEND_ACCESS "RW" 368 // ============================================================================= 369 // Register : SIO_DIV_SDIVISOR 370 // Description : Divider signed divisor 371 // The same as UDIVISOR, but starts a signed calculation, rather 372 // than unsigned. 373 #define SIO_DIV_SDIVISOR_OFFSET 0x0000006c 374 #define SIO_DIV_SDIVISOR_BITS 0xffffffff 375 #define SIO_DIV_SDIVISOR_RESET 0x00000000 376 #define SIO_DIV_SDIVISOR_MSB 31 377 #define SIO_DIV_SDIVISOR_LSB 0 378 #define SIO_DIV_SDIVISOR_ACCESS "RW" 379 // ============================================================================= 380 // Register : SIO_DIV_QUOTIENT 381 // Description : Divider result quotient 382 // The result of `DIVIDEND / DIVISOR` (division). Contents 383 // undefined while CSR_READY is low. 384 // For signed calculations, QUOTIENT is negative when the signs of 385 // DIVIDEND and DIVISOR differ. 386 // This register can be written to directly, for context 387 // save/restore purposes. This halts any 388 // in-progress calculation and sets the CSR_READY and CSR_DIRTY 389 // flags. 390 // Reading from QUOTIENT clears the CSR_DIRTY flag, so should read 391 // results in the order 392 // REMAINDER, QUOTIENT if CSR_DIRTY is used. 393 #define SIO_DIV_QUOTIENT_OFFSET 0x00000070 394 #define SIO_DIV_QUOTIENT_BITS 0xffffffff 395 #define SIO_DIV_QUOTIENT_RESET 0x00000000 396 #define SIO_DIV_QUOTIENT_MSB 31 397 #define SIO_DIV_QUOTIENT_LSB 0 398 #define SIO_DIV_QUOTIENT_ACCESS "RW" 399 // ============================================================================= 400 // Register : SIO_DIV_REMAINDER 401 // Description : Divider result remainder 402 // The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined 403 // while CSR_READY is low. 404 // For signed calculations, REMAINDER is negative only when 405 // DIVIDEND is negative. 406 // This register can be written to directly, for context 407 // save/restore purposes. This halts any 408 // in-progress calculation and sets the CSR_READY and CSR_DIRTY 409 // flags. 410 #define SIO_DIV_REMAINDER_OFFSET 0x00000074 411 #define SIO_DIV_REMAINDER_BITS 0xffffffff 412 #define SIO_DIV_REMAINDER_RESET 0x00000000 413 #define SIO_DIV_REMAINDER_MSB 31 414 #define SIO_DIV_REMAINDER_LSB 0 415 #define SIO_DIV_REMAINDER_ACCESS "RW" 416 // ============================================================================= 417 // Register : SIO_DIV_CSR 418 // Description : Control and status register for divider. 419 #define SIO_DIV_CSR_OFFSET 0x00000078 420 #define SIO_DIV_CSR_BITS 0x00000003 421 #define SIO_DIV_CSR_RESET 0x00000001 422 // ----------------------------------------------------------------------------- 423 // Field : SIO_DIV_CSR_DIRTY 424 // Description : Changes to 1 when any register is written, and back to 0 when 425 // QUOTIENT is read. 426 // Software can use this flag to make save/restore more efficient 427 // (skip if not DIRTY). 428 // If the flag is used in this way, it's recommended to either 429 // read QUOTIENT only, 430 // or REMAINDER and then QUOTIENT, to prevent data loss on context 431 // switch. 432 #define SIO_DIV_CSR_DIRTY_RESET 0x0 433 #define SIO_DIV_CSR_DIRTY_BITS 0x00000002 434 #define SIO_DIV_CSR_DIRTY_MSB 1 435 #define SIO_DIV_CSR_DIRTY_LSB 1 436 #define SIO_DIV_CSR_DIRTY_ACCESS "RO" 437 // ----------------------------------------------------------------------------- 438 // Field : SIO_DIV_CSR_READY 439 // Description : Reads as 0 when a calculation is in progress, 1 otherwise. 440 // Writing an operand (xDIVIDEND, xDIVISOR) will immediately start 441 // a new calculation, no 442 // matter if one is already in progress. 443 // Writing to a result register will immediately terminate any 444 // in-progress calculation 445 // and set the READY and DIRTY flags. 446 #define SIO_DIV_CSR_READY_RESET 0x1 447 #define SIO_DIV_CSR_READY_BITS 0x00000001 448 #define SIO_DIV_CSR_READY_MSB 0 449 #define SIO_DIV_CSR_READY_LSB 0 450 #define SIO_DIV_CSR_READY_ACCESS "RO" 451 // ============================================================================= 452 // Register : SIO_INTERP0_ACCUM0 453 // Description : Read/write access to accumulator 0 454 #define SIO_INTERP0_ACCUM0_OFFSET 0x00000080 455 #define SIO_INTERP0_ACCUM0_BITS 0xffffffff 456 #define SIO_INTERP0_ACCUM0_RESET 0x00000000 457 #define SIO_INTERP0_ACCUM0_MSB 31 458 #define SIO_INTERP0_ACCUM0_LSB 0 459 #define SIO_INTERP0_ACCUM0_ACCESS "RW" 460 // ============================================================================= 461 // Register : SIO_INTERP0_ACCUM1 462 // Description : Read/write access to accumulator 1 463 #define SIO_INTERP0_ACCUM1_OFFSET 0x00000084 464 #define SIO_INTERP0_ACCUM1_BITS 0xffffffff 465 #define SIO_INTERP0_ACCUM1_RESET 0x00000000 466 #define SIO_INTERP0_ACCUM1_MSB 31 467 #define SIO_INTERP0_ACCUM1_LSB 0 468 #define SIO_INTERP0_ACCUM1_ACCESS "RW" 469 // ============================================================================= 470 // Register : SIO_INTERP0_BASE0 471 // Description : Read/write access to BASE0 register. 472 #define SIO_INTERP0_BASE0_OFFSET 0x00000088 473 #define SIO_INTERP0_BASE0_BITS 0xffffffff 474 #define SIO_INTERP0_BASE0_RESET 0x00000000 475 #define SIO_INTERP0_BASE0_MSB 31 476 #define SIO_INTERP0_BASE0_LSB 0 477 #define SIO_INTERP0_BASE0_ACCESS "RW" 478 // ============================================================================= 479 // Register : SIO_INTERP0_BASE1 480 // Description : Read/write access to BASE1 register. 481 #define SIO_INTERP0_BASE1_OFFSET 0x0000008c 482 #define SIO_INTERP0_BASE1_BITS 0xffffffff 483 #define SIO_INTERP0_BASE1_RESET 0x00000000 484 #define SIO_INTERP0_BASE1_MSB 31 485 #define SIO_INTERP0_BASE1_LSB 0 486 #define SIO_INTERP0_BASE1_ACCESS "RW" 487 // ============================================================================= 488 // Register : SIO_INTERP0_BASE2 489 // Description : Read/write access to BASE2 register. 490 #define SIO_INTERP0_BASE2_OFFSET 0x00000090 491 #define SIO_INTERP0_BASE2_BITS 0xffffffff 492 #define SIO_INTERP0_BASE2_RESET 0x00000000 493 #define SIO_INTERP0_BASE2_MSB 31 494 #define SIO_INTERP0_BASE2_LSB 0 495 #define SIO_INTERP0_BASE2_ACCESS "RW" 496 // ============================================================================= 497 // Register : SIO_INTERP0_POP_LANE0 498 // Description : Read LANE0 result, and simultaneously write lane results to 499 // both accumulators (POP). 500 #define SIO_INTERP0_POP_LANE0_OFFSET 0x00000094 501 #define SIO_INTERP0_POP_LANE0_BITS 0xffffffff 502 #define SIO_INTERP0_POP_LANE0_RESET 0x00000000 503 #define SIO_INTERP0_POP_LANE0_MSB 31 504 #define SIO_INTERP0_POP_LANE0_LSB 0 505 #define SIO_INTERP0_POP_LANE0_ACCESS "RO" 506 // ============================================================================= 507 // Register : SIO_INTERP0_POP_LANE1 508 // Description : Read LANE1 result, and simultaneously write lane results to 509 // both accumulators (POP). 510 #define SIO_INTERP0_POP_LANE1_OFFSET 0x00000098 511 #define SIO_INTERP0_POP_LANE1_BITS 0xffffffff 512 #define SIO_INTERP0_POP_LANE1_RESET 0x00000000 513 #define SIO_INTERP0_POP_LANE1_MSB 31 514 #define SIO_INTERP0_POP_LANE1_LSB 0 515 #define SIO_INTERP0_POP_LANE1_ACCESS "RO" 516 // ============================================================================= 517 // Register : SIO_INTERP0_POP_FULL 518 // Description : Read FULL result, and simultaneously write lane results to both 519 // accumulators (POP). 520 #define SIO_INTERP0_POP_FULL_OFFSET 0x0000009c 521 #define SIO_INTERP0_POP_FULL_BITS 0xffffffff 522 #define SIO_INTERP0_POP_FULL_RESET 0x00000000 523 #define SIO_INTERP0_POP_FULL_MSB 31 524 #define SIO_INTERP0_POP_FULL_LSB 0 525 #define SIO_INTERP0_POP_FULL_ACCESS "RO" 526 // ============================================================================= 527 // Register : SIO_INTERP0_PEEK_LANE0 528 // Description : Read LANE0 result, without altering any internal state (PEEK). 529 #define SIO_INTERP0_PEEK_LANE0_OFFSET 0x000000a0 530 #define SIO_INTERP0_PEEK_LANE0_BITS 0xffffffff 531 #define SIO_INTERP0_PEEK_LANE0_RESET 0x00000000 532 #define SIO_INTERP0_PEEK_LANE0_MSB 31 533 #define SIO_INTERP0_PEEK_LANE0_LSB 0 534 #define SIO_INTERP0_PEEK_LANE0_ACCESS "RO" 535 // ============================================================================= 536 // Register : SIO_INTERP0_PEEK_LANE1 537 // Description : Read LANE1 result, without altering any internal state (PEEK). 538 #define SIO_INTERP0_PEEK_LANE1_OFFSET 0x000000a4 539 #define SIO_INTERP0_PEEK_LANE1_BITS 0xffffffff 540 #define SIO_INTERP0_PEEK_LANE1_RESET 0x00000000 541 #define SIO_INTERP0_PEEK_LANE1_MSB 31 542 #define SIO_INTERP0_PEEK_LANE1_LSB 0 543 #define SIO_INTERP0_PEEK_LANE1_ACCESS "RO" 544 // ============================================================================= 545 // Register : SIO_INTERP0_PEEK_FULL 546 // Description : Read FULL result, without altering any internal state (PEEK). 547 #define SIO_INTERP0_PEEK_FULL_OFFSET 0x000000a8 548 #define SIO_INTERP0_PEEK_FULL_BITS 0xffffffff 549 #define SIO_INTERP0_PEEK_FULL_RESET 0x00000000 550 #define SIO_INTERP0_PEEK_FULL_MSB 31 551 #define SIO_INTERP0_PEEK_FULL_LSB 0 552 #define SIO_INTERP0_PEEK_FULL_ACCESS "RO" 553 // ============================================================================= 554 // Register : SIO_INTERP0_CTRL_LANE0 555 // Description : Control register for lane 0 556 #define SIO_INTERP0_CTRL_LANE0_OFFSET 0x000000ac 557 #define SIO_INTERP0_CTRL_LANE0_BITS 0x03bfffff 558 #define SIO_INTERP0_CTRL_LANE0_RESET 0x00000000 559 // ----------------------------------------------------------------------------- 560 // Field : SIO_INTERP0_CTRL_LANE0_OVERF 561 // Description : Set if either OVERF0 or OVERF1 is set. 562 #define SIO_INTERP0_CTRL_LANE0_OVERF_RESET 0x0 563 #define SIO_INTERP0_CTRL_LANE0_OVERF_BITS 0x02000000 564 #define SIO_INTERP0_CTRL_LANE0_OVERF_MSB 25 565 #define SIO_INTERP0_CTRL_LANE0_OVERF_LSB 25 566 #define SIO_INTERP0_CTRL_LANE0_OVERF_ACCESS "RO" 567 // ----------------------------------------------------------------------------- 568 // Field : SIO_INTERP0_CTRL_LANE0_OVERF1 569 // Description : Indicates if any masked-off MSBs in ACCUM1 are set. 570 #define SIO_INTERP0_CTRL_LANE0_OVERF1_RESET 0x0 571 #define SIO_INTERP0_CTRL_LANE0_OVERF1_BITS 0x01000000 572 #define SIO_INTERP0_CTRL_LANE0_OVERF1_MSB 24 573 #define SIO_INTERP0_CTRL_LANE0_OVERF1_LSB 24 574 #define SIO_INTERP0_CTRL_LANE0_OVERF1_ACCESS "RO" 575 // ----------------------------------------------------------------------------- 576 // Field : SIO_INTERP0_CTRL_LANE0_OVERF0 577 // Description : Indicates if any masked-off MSBs in ACCUM0 are set. 578 #define SIO_INTERP0_CTRL_LANE0_OVERF0_RESET 0x0 579 #define SIO_INTERP0_CTRL_LANE0_OVERF0_BITS 0x00800000 580 #define SIO_INTERP0_CTRL_LANE0_OVERF0_MSB 23 581 #define SIO_INTERP0_CTRL_LANE0_OVERF0_LSB 23 582 #define SIO_INTERP0_CTRL_LANE0_OVERF0_ACCESS "RO" 583 // ----------------------------------------------------------------------------- 584 // Field : SIO_INTERP0_CTRL_LANE0_BLEND 585 // Description : Only present on INTERP0 on each core. If BLEND mode is enabled: 586 // - LANE1 result is a linear interpolation between BASE0 and 587 // BASE1, controlled 588 // by the 8 LSBs of lane 1 shift and mask value (a fractional 589 // number between 590 // 0 and 255/256ths) 591 // - LANE0 result does not have BASE0 added (yields only the 8 592 // LSBs of lane 1 shift+mask value) 593 // - FULL result does not have lane 1 shift+mask value added 594 // (BASE2 + lane 0 shift+mask) 595 // LANE1 SIGNED flag controls whether the interpolation is signed 596 // or unsigned. 597 #define SIO_INTERP0_CTRL_LANE0_BLEND_RESET 0x0 598 #define SIO_INTERP0_CTRL_LANE0_BLEND_BITS 0x00200000 599 #define SIO_INTERP0_CTRL_LANE0_BLEND_MSB 21 600 #define SIO_INTERP0_CTRL_LANE0_BLEND_LSB 21 601 #define SIO_INTERP0_CTRL_LANE0_BLEND_ACCESS "RW" 602 // ----------------------------------------------------------------------------- 603 // Field : SIO_INTERP0_CTRL_LANE0_FORCE_MSB 604 // Description : ORed into bits 29:28 of the lane result presented to the 605 // processor on the bus. 606 // No effect on the internal 32-bit datapath. Handy for using a 607 // lane to generate sequence 608 // of pointers into flash or SRAM. 609 #define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_RESET 0x0 610 #define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS 0x00180000 611 #define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_MSB 20 612 #define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB 19 613 #define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_ACCESS "RW" 614 // ----------------------------------------------------------------------------- 615 // Field : SIO_INTERP0_CTRL_LANE0_ADD_RAW 616 // Description : If 1, mask + shift is bypassed for LANE0 result. This does not 617 // affect FULL result. 618 #define SIO_INTERP0_CTRL_LANE0_ADD_RAW_RESET 0x0 619 #define SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS 0x00040000 620 #define SIO_INTERP0_CTRL_LANE0_ADD_RAW_MSB 18 621 #define SIO_INTERP0_CTRL_LANE0_ADD_RAW_LSB 18 622 #define SIO_INTERP0_CTRL_LANE0_ADD_RAW_ACCESS "RW" 623 // ----------------------------------------------------------------------------- 624 // Field : SIO_INTERP0_CTRL_LANE0_CROSS_RESULT 625 // Description : If 1, feed the opposite lane's result into this lane's 626 // accumulator on POP. 627 #define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_RESET 0x0 628 #define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS 0x00020000 629 #define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_MSB 17 630 #define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_LSB 17 631 #define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_ACCESS "RW" 632 // ----------------------------------------------------------------------------- 633 // Field : SIO_INTERP0_CTRL_LANE0_CROSS_INPUT 634 // Description : If 1, feed the opposite lane's accumulator into this lane's 635 // shift + mask hardware. 636 // Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is 637 // before the shift+mask bypass) 638 #define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_RESET 0x0 639 #define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS 0x00010000 640 #define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_MSB 16 641 #define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_LSB 16 642 #define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_ACCESS "RW" 643 // ----------------------------------------------------------------------------- 644 // Field : SIO_INTERP0_CTRL_LANE0_SIGNED 645 // Description : If SIGNED is set, the shifted and masked accumulator value is 646 // sign-extended to 32 bits 647 // before adding to BASE0, and LANE0 PEEK/POP appear extended to 648 // 32 bits when read by processor. 649 #define SIO_INTERP0_CTRL_LANE0_SIGNED_RESET 0x0 650 #define SIO_INTERP0_CTRL_LANE0_SIGNED_BITS 0x00008000 651 #define SIO_INTERP0_CTRL_LANE0_SIGNED_MSB 15 652 #define SIO_INTERP0_CTRL_LANE0_SIGNED_LSB 15 653 #define SIO_INTERP0_CTRL_LANE0_SIGNED_ACCESS "RW" 654 // ----------------------------------------------------------------------------- 655 // Field : SIO_INTERP0_CTRL_LANE0_MASK_MSB 656 // Description : The most-significant bit allowed to pass by the mask 657 // (inclusive) 658 // Setting MSB < LSB may cause chip to turn inside-out 659 #define SIO_INTERP0_CTRL_LANE0_MASK_MSB_RESET 0x00 660 #define SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS 0x00007c00 661 #define SIO_INTERP0_CTRL_LANE0_MASK_MSB_MSB 14 662 #define SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB 10 663 #define SIO_INTERP0_CTRL_LANE0_MASK_MSB_ACCESS "RW" 664 // ----------------------------------------------------------------------------- 665 // Field : SIO_INTERP0_CTRL_LANE0_MASK_LSB 666 // Description : The least-significant bit allowed to pass by the mask 667 // (inclusive) 668 #define SIO_INTERP0_CTRL_LANE0_MASK_LSB_RESET 0x00 669 #define SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS 0x000003e0 670 #define SIO_INTERP0_CTRL_LANE0_MASK_LSB_MSB 9 671 #define SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB 5 672 #define SIO_INTERP0_CTRL_LANE0_MASK_LSB_ACCESS "RW" 673 // ----------------------------------------------------------------------------- 674 // Field : SIO_INTERP0_CTRL_LANE0_SHIFT 675 // Description : Logical right-shift applied to accumulator before masking 676 #define SIO_INTERP0_CTRL_LANE0_SHIFT_RESET 0x00 677 #define SIO_INTERP0_CTRL_LANE0_SHIFT_BITS 0x0000001f 678 #define SIO_INTERP0_CTRL_LANE0_SHIFT_MSB 4 679 #define SIO_INTERP0_CTRL_LANE0_SHIFT_LSB 0 680 #define SIO_INTERP0_CTRL_LANE0_SHIFT_ACCESS "RW" 681 // ============================================================================= 682 // Register : SIO_INTERP0_CTRL_LANE1 683 // Description : Control register for lane 1 684 #define SIO_INTERP0_CTRL_LANE1_OFFSET 0x000000b0 685 #define SIO_INTERP0_CTRL_LANE1_BITS 0x001fffff 686 #define SIO_INTERP0_CTRL_LANE1_RESET 0x00000000 687 // ----------------------------------------------------------------------------- 688 // Field : SIO_INTERP0_CTRL_LANE1_FORCE_MSB 689 // Description : ORed into bits 29:28 of the lane result presented to the 690 // processor on the bus. 691 // No effect on the internal 32-bit datapath. Handy for using a 692 // lane to generate sequence 693 // of pointers into flash or SRAM. 694 #define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_RESET 0x0 695 #define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_BITS 0x00180000 696 #define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_MSB 20 697 #define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_LSB 19 698 #define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_ACCESS "RW" 699 // ----------------------------------------------------------------------------- 700 // Field : SIO_INTERP0_CTRL_LANE1_ADD_RAW 701 // Description : If 1, mask + shift is bypassed for LANE1 result. This does not 702 // affect FULL result. 703 #define SIO_INTERP0_CTRL_LANE1_ADD_RAW_RESET 0x0 704 #define SIO_INTERP0_CTRL_LANE1_ADD_RAW_BITS 0x00040000 705 #define SIO_INTERP0_CTRL_LANE1_ADD_RAW_MSB 18 706 #define SIO_INTERP0_CTRL_LANE1_ADD_RAW_LSB 18 707 #define SIO_INTERP0_CTRL_LANE1_ADD_RAW_ACCESS "RW" 708 // ----------------------------------------------------------------------------- 709 // Field : SIO_INTERP0_CTRL_LANE1_CROSS_RESULT 710 // Description : If 1, feed the opposite lane's result into this lane's 711 // accumulator on POP. 712 #define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_RESET 0x0 713 #define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_BITS 0x00020000 714 #define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_MSB 17 715 #define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_LSB 17 716 #define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_ACCESS "RW" 717 // ----------------------------------------------------------------------------- 718 // Field : SIO_INTERP0_CTRL_LANE1_CROSS_INPUT 719 // Description : If 1, feed the opposite lane's accumulator into this lane's 720 // shift + mask hardware. 721 // Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is 722 // before the shift+mask bypass) 723 #define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_RESET 0x0 724 #define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_BITS 0x00010000 725 #define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_MSB 16 726 #define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_LSB 16 727 #define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_ACCESS "RW" 728 // ----------------------------------------------------------------------------- 729 // Field : SIO_INTERP0_CTRL_LANE1_SIGNED 730 // Description : If SIGNED is set, the shifted and masked accumulator value is 731 // sign-extended to 32 bits 732 // before adding to BASE1, and LANE1 PEEK/POP appear extended to 733 // 32 bits when read by processor. 734 #define SIO_INTERP0_CTRL_LANE1_SIGNED_RESET 0x0 735 #define SIO_INTERP0_CTRL_LANE1_SIGNED_BITS 0x00008000 736 #define SIO_INTERP0_CTRL_LANE1_SIGNED_MSB 15 737 #define SIO_INTERP0_CTRL_LANE1_SIGNED_LSB 15 738 #define SIO_INTERP0_CTRL_LANE1_SIGNED_ACCESS "RW" 739 // ----------------------------------------------------------------------------- 740 // Field : SIO_INTERP0_CTRL_LANE1_MASK_MSB 741 // Description : The most-significant bit allowed to pass by the mask 742 // (inclusive) 743 // Setting MSB < LSB may cause chip to turn inside-out 744 #define SIO_INTERP0_CTRL_LANE1_MASK_MSB_RESET 0x00 745 #define SIO_INTERP0_CTRL_LANE1_MASK_MSB_BITS 0x00007c00 746 #define SIO_INTERP0_CTRL_LANE1_MASK_MSB_MSB 14 747 #define SIO_INTERP0_CTRL_LANE1_MASK_MSB_LSB 10 748 #define SIO_INTERP0_CTRL_LANE1_MASK_MSB_ACCESS "RW" 749 // ----------------------------------------------------------------------------- 750 // Field : SIO_INTERP0_CTRL_LANE1_MASK_LSB 751 // Description : The least-significant bit allowed to pass by the mask 752 // (inclusive) 753 #define SIO_INTERP0_CTRL_LANE1_MASK_LSB_RESET 0x00 754 #define SIO_INTERP0_CTRL_LANE1_MASK_LSB_BITS 0x000003e0 755 #define SIO_INTERP0_CTRL_LANE1_MASK_LSB_MSB 9 756 #define SIO_INTERP0_CTRL_LANE1_MASK_LSB_LSB 5 757 #define SIO_INTERP0_CTRL_LANE1_MASK_LSB_ACCESS "RW" 758 // ----------------------------------------------------------------------------- 759 // Field : SIO_INTERP0_CTRL_LANE1_SHIFT 760 // Description : Logical right-shift applied to accumulator before masking 761 #define SIO_INTERP0_CTRL_LANE1_SHIFT_RESET 0x00 762 #define SIO_INTERP0_CTRL_LANE1_SHIFT_BITS 0x0000001f 763 #define SIO_INTERP0_CTRL_LANE1_SHIFT_MSB 4 764 #define SIO_INTERP0_CTRL_LANE1_SHIFT_LSB 0 765 #define SIO_INTERP0_CTRL_LANE1_SHIFT_ACCESS "RW" 766 // ============================================================================= 767 // Register : SIO_INTERP0_ACCUM0_ADD 768 // Description : Values written here are atomically added to ACCUM0 769 // Reading yields lane 0's raw shift and mask value (BASE0 not 770 // added). 771 #define SIO_INTERP0_ACCUM0_ADD_OFFSET 0x000000b4 772 #define SIO_INTERP0_ACCUM0_ADD_BITS 0x00ffffff 773 #define SIO_INTERP0_ACCUM0_ADD_RESET 0x00000000 774 #define SIO_INTERP0_ACCUM0_ADD_MSB 23 775 #define SIO_INTERP0_ACCUM0_ADD_LSB 0 776 #define SIO_INTERP0_ACCUM0_ADD_ACCESS "RW" 777 // ============================================================================= 778 // Register : SIO_INTERP0_ACCUM1_ADD 779 // Description : Values written here are atomically added to ACCUM1 780 // Reading yields lane 1's raw shift and mask value (BASE1 not 781 // added). 782 #define SIO_INTERP0_ACCUM1_ADD_OFFSET 0x000000b8 783 #define SIO_INTERP0_ACCUM1_ADD_BITS 0x00ffffff 784 #define SIO_INTERP0_ACCUM1_ADD_RESET 0x00000000 785 #define SIO_INTERP0_ACCUM1_ADD_MSB 23 786 #define SIO_INTERP0_ACCUM1_ADD_LSB 0 787 #define SIO_INTERP0_ACCUM1_ADD_ACCESS "RW" 788 // ============================================================================= 789 // Register : SIO_INTERP0_BASE_1AND0 790 // Description : On write, the lower 16 bits go to BASE0, upper bits to BASE1 791 // simultaneously. 792 // Each half is sign-extended to 32 bits if that lane's SIGNED 793 // flag is set. 794 #define SIO_INTERP0_BASE_1AND0_OFFSET 0x000000bc 795 #define SIO_INTERP0_BASE_1AND0_BITS 0xffffffff 796 #define SIO_INTERP0_BASE_1AND0_RESET 0x00000000 797 #define SIO_INTERP0_BASE_1AND0_MSB 31 798 #define SIO_INTERP0_BASE_1AND0_LSB 0 799 #define SIO_INTERP0_BASE_1AND0_ACCESS "WO" 800 // ============================================================================= 801 // Register : SIO_INTERP1_ACCUM0 802 // Description : Read/write access to accumulator 0 803 #define SIO_INTERP1_ACCUM0_OFFSET 0x000000c0 804 #define SIO_INTERP1_ACCUM0_BITS 0xffffffff 805 #define SIO_INTERP1_ACCUM0_RESET 0x00000000 806 #define SIO_INTERP1_ACCUM0_MSB 31 807 #define SIO_INTERP1_ACCUM0_LSB 0 808 #define SIO_INTERP1_ACCUM0_ACCESS "RW" 809 // ============================================================================= 810 // Register : SIO_INTERP1_ACCUM1 811 // Description : Read/write access to accumulator 1 812 #define SIO_INTERP1_ACCUM1_OFFSET 0x000000c4 813 #define SIO_INTERP1_ACCUM1_BITS 0xffffffff 814 #define SIO_INTERP1_ACCUM1_RESET 0x00000000 815 #define SIO_INTERP1_ACCUM1_MSB 31 816 #define SIO_INTERP1_ACCUM1_LSB 0 817 #define SIO_INTERP1_ACCUM1_ACCESS "RW" 818 // ============================================================================= 819 // Register : SIO_INTERP1_BASE0 820 // Description : Read/write access to BASE0 register. 821 #define SIO_INTERP1_BASE0_OFFSET 0x000000c8 822 #define SIO_INTERP1_BASE0_BITS 0xffffffff 823 #define SIO_INTERP1_BASE0_RESET 0x00000000 824 #define SIO_INTERP1_BASE0_MSB 31 825 #define SIO_INTERP1_BASE0_LSB 0 826 #define SIO_INTERP1_BASE0_ACCESS "RW" 827 // ============================================================================= 828 // Register : SIO_INTERP1_BASE1 829 // Description : Read/write access to BASE1 register. 830 #define SIO_INTERP1_BASE1_OFFSET 0x000000cc 831 #define SIO_INTERP1_BASE1_BITS 0xffffffff 832 #define SIO_INTERP1_BASE1_RESET 0x00000000 833 #define SIO_INTERP1_BASE1_MSB 31 834 #define SIO_INTERP1_BASE1_LSB 0 835 #define SIO_INTERP1_BASE1_ACCESS "RW" 836 // ============================================================================= 837 // Register : SIO_INTERP1_BASE2 838 // Description : Read/write access to BASE2 register. 839 #define SIO_INTERP1_BASE2_OFFSET 0x000000d0 840 #define SIO_INTERP1_BASE2_BITS 0xffffffff 841 #define SIO_INTERP1_BASE2_RESET 0x00000000 842 #define SIO_INTERP1_BASE2_MSB 31 843 #define SIO_INTERP1_BASE2_LSB 0 844 #define SIO_INTERP1_BASE2_ACCESS "RW" 845 // ============================================================================= 846 // Register : SIO_INTERP1_POP_LANE0 847 // Description : Read LANE0 result, and simultaneously write lane results to 848 // both accumulators (POP). 849 #define SIO_INTERP1_POP_LANE0_OFFSET 0x000000d4 850 #define SIO_INTERP1_POP_LANE0_BITS 0xffffffff 851 #define SIO_INTERP1_POP_LANE0_RESET 0x00000000 852 #define SIO_INTERP1_POP_LANE0_MSB 31 853 #define SIO_INTERP1_POP_LANE0_LSB 0 854 #define SIO_INTERP1_POP_LANE0_ACCESS "RO" 855 // ============================================================================= 856 // Register : SIO_INTERP1_POP_LANE1 857 // Description : Read LANE1 result, and simultaneously write lane results to 858 // both accumulators (POP). 859 #define SIO_INTERP1_POP_LANE1_OFFSET 0x000000d8 860 #define SIO_INTERP1_POP_LANE1_BITS 0xffffffff 861 #define SIO_INTERP1_POP_LANE1_RESET 0x00000000 862 #define SIO_INTERP1_POP_LANE1_MSB 31 863 #define SIO_INTERP1_POP_LANE1_LSB 0 864 #define SIO_INTERP1_POP_LANE1_ACCESS "RO" 865 // ============================================================================= 866 // Register : SIO_INTERP1_POP_FULL 867 // Description : Read FULL result, and simultaneously write lane results to both 868 // accumulators (POP). 869 #define SIO_INTERP1_POP_FULL_OFFSET 0x000000dc 870 #define SIO_INTERP1_POP_FULL_BITS 0xffffffff 871 #define SIO_INTERP1_POP_FULL_RESET 0x00000000 872 #define SIO_INTERP1_POP_FULL_MSB 31 873 #define SIO_INTERP1_POP_FULL_LSB 0 874 #define SIO_INTERP1_POP_FULL_ACCESS "RO" 875 // ============================================================================= 876 // Register : SIO_INTERP1_PEEK_LANE0 877 // Description : Read LANE0 result, without altering any internal state (PEEK). 878 #define SIO_INTERP1_PEEK_LANE0_OFFSET 0x000000e0 879 #define SIO_INTERP1_PEEK_LANE0_BITS 0xffffffff 880 #define SIO_INTERP1_PEEK_LANE0_RESET 0x00000000 881 #define SIO_INTERP1_PEEK_LANE0_MSB 31 882 #define SIO_INTERP1_PEEK_LANE0_LSB 0 883 #define SIO_INTERP1_PEEK_LANE0_ACCESS "RO" 884 // ============================================================================= 885 // Register : SIO_INTERP1_PEEK_LANE1 886 // Description : Read LANE1 result, without altering any internal state (PEEK). 887 #define SIO_INTERP1_PEEK_LANE1_OFFSET 0x000000e4 888 #define SIO_INTERP1_PEEK_LANE1_BITS 0xffffffff 889 #define SIO_INTERP1_PEEK_LANE1_RESET 0x00000000 890 #define SIO_INTERP1_PEEK_LANE1_MSB 31 891 #define SIO_INTERP1_PEEK_LANE1_LSB 0 892 #define SIO_INTERP1_PEEK_LANE1_ACCESS "RO" 893 // ============================================================================= 894 // Register : SIO_INTERP1_PEEK_FULL 895 // Description : Read FULL result, without altering any internal state (PEEK). 896 #define SIO_INTERP1_PEEK_FULL_OFFSET 0x000000e8 897 #define SIO_INTERP1_PEEK_FULL_BITS 0xffffffff 898 #define SIO_INTERP1_PEEK_FULL_RESET 0x00000000 899 #define SIO_INTERP1_PEEK_FULL_MSB 31 900 #define SIO_INTERP1_PEEK_FULL_LSB 0 901 #define SIO_INTERP1_PEEK_FULL_ACCESS "RO" 902 // ============================================================================= 903 // Register : SIO_INTERP1_CTRL_LANE0 904 // Description : Control register for lane 0 905 #define SIO_INTERP1_CTRL_LANE0_OFFSET 0x000000ec 906 #define SIO_INTERP1_CTRL_LANE0_BITS 0x03dfffff 907 #define SIO_INTERP1_CTRL_LANE0_RESET 0x00000000 908 // ----------------------------------------------------------------------------- 909 // Field : SIO_INTERP1_CTRL_LANE0_OVERF 910 // Description : Set if either OVERF0 or OVERF1 is set. 911 #define SIO_INTERP1_CTRL_LANE0_OVERF_RESET 0x0 912 #define SIO_INTERP1_CTRL_LANE0_OVERF_BITS 0x02000000 913 #define SIO_INTERP1_CTRL_LANE0_OVERF_MSB 25 914 #define SIO_INTERP1_CTRL_LANE0_OVERF_LSB 25 915 #define SIO_INTERP1_CTRL_LANE0_OVERF_ACCESS "RO" 916 // ----------------------------------------------------------------------------- 917 // Field : SIO_INTERP1_CTRL_LANE0_OVERF1 918 // Description : Indicates if any masked-off MSBs in ACCUM1 are set. 919 #define SIO_INTERP1_CTRL_LANE0_OVERF1_RESET 0x0 920 #define SIO_INTERP1_CTRL_LANE0_OVERF1_BITS 0x01000000 921 #define SIO_INTERP1_CTRL_LANE0_OVERF1_MSB 24 922 #define SIO_INTERP1_CTRL_LANE0_OVERF1_LSB 24 923 #define SIO_INTERP1_CTRL_LANE0_OVERF1_ACCESS "RO" 924 // ----------------------------------------------------------------------------- 925 // Field : SIO_INTERP1_CTRL_LANE0_OVERF0 926 // Description : Indicates if any masked-off MSBs in ACCUM0 are set. 927 #define SIO_INTERP1_CTRL_LANE0_OVERF0_RESET 0x0 928 #define SIO_INTERP1_CTRL_LANE0_OVERF0_BITS 0x00800000 929 #define SIO_INTERP1_CTRL_LANE0_OVERF0_MSB 23 930 #define SIO_INTERP1_CTRL_LANE0_OVERF0_LSB 23 931 #define SIO_INTERP1_CTRL_LANE0_OVERF0_ACCESS "RO" 932 // ----------------------------------------------------------------------------- 933 // Field : SIO_INTERP1_CTRL_LANE0_CLAMP 934 // Description : Only present on INTERP1 on each core. If CLAMP mode is enabled: 935 // - LANE0 result is shifted and masked ACCUM0, clamped by a lower 936 // bound of 937 // BASE0 and an upper bound of BASE1. 938 // - Signedness of these comparisons is determined by 939 // LANE0_CTRL_SIGNED 940 #define SIO_INTERP1_CTRL_LANE0_CLAMP_RESET 0x0 941 #define SIO_INTERP1_CTRL_LANE0_CLAMP_BITS 0x00400000 942 #define SIO_INTERP1_CTRL_LANE0_CLAMP_MSB 22 943 #define SIO_INTERP1_CTRL_LANE0_CLAMP_LSB 22 944 #define SIO_INTERP1_CTRL_LANE0_CLAMP_ACCESS "RW" 945 // ----------------------------------------------------------------------------- 946 // Field : SIO_INTERP1_CTRL_LANE0_FORCE_MSB 947 // Description : ORed into bits 29:28 of the lane result presented to the 948 // processor on the bus. 949 // No effect on the internal 32-bit datapath. Handy for using a 950 // lane to generate sequence 951 // of pointers into flash or SRAM. 952 #define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_RESET 0x0 953 #define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_BITS 0x00180000 954 #define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_MSB 20 955 #define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_LSB 19 956 #define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_ACCESS "RW" 957 // ----------------------------------------------------------------------------- 958 // Field : SIO_INTERP1_CTRL_LANE0_ADD_RAW 959 // Description : If 1, mask + shift is bypassed for LANE0 result. This does not 960 // affect FULL result. 961 #define SIO_INTERP1_CTRL_LANE0_ADD_RAW_RESET 0x0 962 #define SIO_INTERP1_CTRL_LANE0_ADD_RAW_BITS 0x00040000 963 #define SIO_INTERP1_CTRL_LANE0_ADD_RAW_MSB 18 964 #define SIO_INTERP1_CTRL_LANE0_ADD_RAW_LSB 18 965 #define SIO_INTERP1_CTRL_LANE0_ADD_RAW_ACCESS "RW" 966 // ----------------------------------------------------------------------------- 967 // Field : SIO_INTERP1_CTRL_LANE0_CROSS_RESULT 968 // Description : If 1, feed the opposite lane's result into this lane's 969 // accumulator on POP. 970 #define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_RESET 0x0 971 #define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_BITS 0x00020000 972 #define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_MSB 17 973 #define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_LSB 17 974 #define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_ACCESS "RW" 975 // ----------------------------------------------------------------------------- 976 // Field : SIO_INTERP1_CTRL_LANE0_CROSS_INPUT 977 // Description : If 1, feed the opposite lane's accumulator into this lane's 978 // shift + mask hardware. 979 // Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is 980 // before the shift+mask bypass) 981 #define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_RESET 0x0 982 #define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_BITS 0x00010000 983 #define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_MSB 16 984 #define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_LSB 16 985 #define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_ACCESS "RW" 986 // ----------------------------------------------------------------------------- 987 // Field : SIO_INTERP1_CTRL_LANE0_SIGNED 988 // Description : If SIGNED is set, the shifted and masked accumulator value is 989 // sign-extended to 32 bits 990 // before adding to BASE0, and LANE0 PEEK/POP appear extended to 991 // 32 bits when read by processor. 992 #define SIO_INTERP1_CTRL_LANE0_SIGNED_RESET 0x0 993 #define SIO_INTERP1_CTRL_LANE0_SIGNED_BITS 0x00008000 994 #define SIO_INTERP1_CTRL_LANE0_SIGNED_MSB 15 995 #define SIO_INTERP1_CTRL_LANE0_SIGNED_LSB 15 996 #define SIO_INTERP1_CTRL_LANE0_SIGNED_ACCESS "RW" 997 // ----------------------------------------------------------------------------- 998 // Field : SIO_INTERP1_CTRL_LANE0_MASK_MSB 999 // Description : The most-significant bit allowed to pass by the mask 1000 // (inclusive) 1001 // Setting MSB < LSB may cause chip to turn inside-out 1002 #define SIO_INTERP1_CTRL_LANE0_MASK_MSB_RESET 0x00 1003 #define SIO_INTERP1_CTRL_LANE0_MASK_MSB_BITS 0x00007c00 1004 #define SIO_INTERP1_CTRL_LANE0_MASK_MSB_MSB 14 1005 #define SIO_INTERP1_CTRL_LANE0_MASK_MSB_LSB 10 1006 #define SIO_INTERP1_CTRL_LANE0_MASK_MSB_ACCESS "RW" 1007 // ----------------------------------------------------------------------------- 1008 // Field : SIO_INTERP1_CTRL_LANE0_MASK_LSB 1009 // Description : The least-significant bit allowed to pass by the mask 1010 // (inclusive) 1011 #define SIO_INTERP1_CTRL_LANE0_MASK_LSB_RESET 0x00 1012 #define SIO_INTERP1_CTRL_LANE0_MASK_LSB_BITS 0x000003e0 1013 #define SIO_INTERP1_CTRL_LANE0_MASK_LSB_MSB 9 1014 #define SIO_INTERP1_CTRL_LANE0_MASK_LSB_LSB 5 1015 #define SIO_INTERP1_CTRL_LANE0_MASK_LSB_ACCESS "RW" 1016 // ----------------------------------------------------------------------------- 1017 // Field : SIO_INTERP1_CTRL_LANE0_SHIFT 1018 // Description : Logical right-shift applied to accumulator before masking 1019 #define SIO_INTERP1_CTRL_LANE0_SHIFT_RESET 0x00 1020 #define SIO_INTERP1_CTRL_LANE0_SHIFT_BITS 0x0000001f 1021 #define SIO_INTERP1_CTRL_LANE0_SHIFT_MSB 4 1022 #define SIO_INTERP1_CTRL_LANE0_SHIFT_LSB 0 1023 #define SIO_INTERP1_CTRL_LANE0_SHIFT_ACCESS "RW" 1024 // ============================================================================= 1025 // Register : SIO_INTERP1_CTRL_LANE1 1026 // Description : Control register for lane 1 1027 #define SIO_INTERP1_CTRL_LANE1_OFFSET 0x000000f0 1028 #define SIO_INTERP1_CTRL_LANE1_BITS 0x001fffff 1029 #define SIO_INTERP1_CTRL_LANE1_RESET 0x00000000 1030 // ----------------------------------------------------------------------------- 1031 // Field : SIO_INTERP1_CTRL_LANE1_FORCE_MSB 1032 // Description : ORed into bits 29:28 of the lane result presented to the 1033 // processor on the bus. 1034 // No effect on the internal 32-bit datapath. Handy for using a 1035 // lane to generate sequence 1036 // of pointers into flash or SRAM. 1037 #define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_RESET 0x0 1038 #define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_BITS 0x00180000 1039 #define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_MSB 20 1040 #define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_LSB 19 1041 #define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_ACCESS "RW" 1042 // ----------------------------------------------------------------------------- 1043 // Field : SIO_INTERP1_CTRL_LANE1_ADD_RAW 1044 // Description : If 1, mask + shift is bypassed for LANE1 result. This does not 1045 // affect FULL result. 1046 #define SIO_INTERP1_CTRL_LANE1_ADD_RAW_RESET 0x0 1047 #define SIO_INTERP1_CTRL_LANE1_ADD_RAW_BITS 0x00040000 1048 #define SIO_INTERP1_CTRL_LANE1_ADD_RAW_MSB 18 1049 #define SIO_INTERP1_CTRL_LANE1_ADD_RAW_LSB 18 1050 #define SIO_INTERP1_CTRL_LANE1_ADD_RAW_ACCESS "RW" 1051 // ----------------------------------------------------------------------------- 1052 // Field : SIO_INTERP1_CTRL_LANE1_CROSS_RESULT 1053 // Description : If 1, feed the opposite lane's result into this lane's 1054 // accumulator on POP. 1055 #define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_RESET 0x0 1056 #define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_BITS 0x00020000 1057 #define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_MSB 17 1058 #define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_LSB 17 1059 #define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_ACCESS "RW" 1060 // ----------------------------------------------------------------------------- 1061 // Field : SIO_INTERP1_CTRL_LANE1_CROSS_INPUT 1062 // Description : If 1, feed the opposite lane's accumulator into this lane's 1063 // shift + mask hardware. 1064 // Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is 1065 // before the shift+mask bypass) 1066 #define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_RESET 0x0 1067 #define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_BITS 0x00010000 1068 #define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_MSB 16 1069 #define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_LSB 16 1070 #define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_ACCESS "RW" 1071 // ----------------------------------------------------------------------------- 1072 // Field : SIO_INTERP1_CTRL_LANE1_SIGNED 1073 // Description : If SIGNED is set, the shifted and masked accumulator value is 1074 // sign-extended to 32 bits 1075 // before adding to BASE1, and LANE1 PEEK/POP appear extended to 1076 // 32 bits when read by processor. 1077 #define SIO_INTERP1_CTRL_LANE1_SIGNED_RESET 0x0 1078 #define SIO_INTERP1_CTRL_LANE1_SIGNED_BITS 0x00008000 1079 #define SIO_INTERP1_CTRL_LANE1_SIGNED_MSB 15 1080 #define SIO_INTERP1_CTRL_LANE1_SIGNED_LSB 15 1081 #define SIO_INTERP1_CTRL_LANE1_SIGNED_ACCESS "RW" 1082 // ----------------------------------------------------------------------------- 1083 // Field : SIO_INTERP1_CTRL_LANE1_MASK_MSB 1084 // Description : The most-significant bit allowed to pass by the mask 1085 // (inclusive) 1086 // Setting MSB < LSB may cause chip to turn inside-out 1087 #define SIO_INTERP1_CTRL_LANE1_MASK_MSB_RESET 0x00 1088 #define SIO_INTERP1_CTRL_LANE1_MASK_MSB_BITS 0x00007c00 1089 #define SIO_INTERP1_CTRL_LANE1_MASK_MSB_MSB 14 1090 #define SIO_INTERP1_CTRL_LANE1_MASK_MSB_LSB 10 1091 #define SIO_INTERP1_CTRL_LANE1_MASK_MSB_ACCESS "RW" 1092 // ----------------------------------------------------------------------------- 1093 // Field : SIO_INTERP1_CTRL_LANE1_MASK_LSB 1094 // Description : The least-significant bit allowed to pass by the mask 1095 // (inclusive) 1096 #define SIO_INTERP1_CTRL_LANE1_MASK_LSB_RESET 0x00 1097 #define SIO_INTERP1_CTRL_LANE1_MASK_LSB_BITS 0x000003e0 1098 #define SIO_INTERP1_CTRL_LANE1_MASK_LSB_MSB 9 1099 #define SIO_INTERP1_CTRL_LANE1_MASK_LSB_LSB 5 1100 #define SIO_INTERP1_CTRL_LANE1_MASK_LSB_ACCESS "RW" 1101 // ----------------------------------------------------------------------------- 1102 // Field : SIO_INTERP1_CTRL_LANE1_SHIFT 1103 // Description : Logical right-shift applied to accumulator before masking 1104 #define SIO_INTERP1_CTRL_LANE1_SHIFT_RESET 0x00 1105 #define SIO_INTERP1_CTRL_LANE1_SHIFT_BITS 0x0000001f 1106 #define SIO_INTERP1_CTRL_LANE1_SHIFT_MSB 4 1107 #define SIO_INTERP1_CTRL_LANE1_SHIFT_LSB 0 1108 #define SIO_INTERP1_CTRL_LANE1_SHIFT_ACCESS "RW" 1109 // ============================================================================= 1110 // Register : SIO_INTERP1_ACCUM0_ADD 1111 // Description : Values written here are atomically added to ACCUM0 1112 // Reading yields lane 0's raw shift and mask value (BASE0 not 1113 // added). 1114 #define SIO_INTERP1_ACCUM0_ADD_OFFSET 0x000000f4 1115 #define SIO_INTERP1_ACCUM0_ADD_BITS 0x00ffffff 1116 #define SIO_INTERP1_ACCUM0_ADD_RESET 0x00000000 1117 #define SIO_INTERP1_ACCUM0_ADD_MSB 23 1118 #define SIO_INTERP1_ACCUM0_ADD_LSB 0 1119 #define SIO_INTERP1_ACCUM0_ADD_ACCESS "RW" 1120 // ============================================================================= 1121 // Register : SIO_INTERP1_ACCUM1_ADD 1122 // Description : Values written here are atomically added to ACCUM1 1123 // Reading yields lane 1's raw shift and mask value (BASE1 not 1124 // added). 1125 #define SIO_INTERP1_ACCUM1_ADD_OFFSET 0x000000f8 1126 #define SIO_INTERP1_ACCUM1_ADD_BITS 0x00ffffff 1127 #define SIO_INTERP1_ACCUM1_ADD_RESET 0x00000000 1128 #define SIO_INTERP1_ACCUM1_ADD_MSB 23 1129 #define SIO_INTERP1_ACCUM1_ADD_LSB 0 1130 #define SIO_INTERP1_ACCUM1_ADD_ACCESS "RW" 1131 // ============================================================================= 1132 // Register : SIO_INTERP1_BASE_1AND0 1133 // Description : On write, the lower 16 bits go to BASE0, upper bits to BASE1 1134 // simultaneously. 1135 // Each half is sign-extended to 32 bits if that lane's SIGNED 1136 // flag is set. 1137 #define SIO_INTERP1_BASE_1AND0_OFFSET 0x000000fc 1138 #define SIO_INTERP1_BASE_1AND0_BITS 0xffffffff 1139 #define SIO_INTERP1_BASE_1AND0_RESET 0x00000000 1140 #define SIO_INTERP1_BASE_1AND0_MSB 31 1141 #define SIO_INTERP1_BASE_1AND0_LSB 0 1142 #define SIO_INTERP1_BASE_1AND0_ACCESS "WO" 1143 // ============================================================================= 1144 // Register : SIO_SPINLOCK0 1145 // Description : Reading from a spinlock address will: 1146 // - Return 0 if lock is already locked 1147 // - Otherwise return nonzero, and simultaneously claim the lock 1148 // 1149 // Writing (any value) releases the lock. 1150 // If core 0 and core 1 attempt to claim the same lock 1151 // simultaneously, core 0 wins. 1152 // The value returned on success is 0x1 << lock number. 1153 #define SIO_SPINLOCK0_OFFSET 0x00000100 1154 #define SIO_SPINLOCK0_BITS 0xffffffff 1155 #define SIO_SPINLOCK0_RESET 0x00000000 1156 #define SIO_SPINLOCK0_MSB 31 1157 #define SIO_SPINLOCK0_LSB 0 1158 #define SIO_SPINLOCK0_ACCESS "RO" 1159 // ============================================================================= 1160 // Register : SIO_SPINLOCK1 1161 // Description : Reading from a spinlock address will: 1162 // - Return 0 if lock is already locked 1163 // - Otherwise return nonzero, and simultaneously claim the lock 1164 // 1165 // Writing (any value) releases the lock. 1166 // If core 0 and core 1 attempt to claim the same lock 1167 // simultaneously, core 0 wins. 1168 // The value returned on success is 0x1 << lock number. 1169 #define SIO_SPINLOCK1_OFFSET 0x00000104 1170 #define SIO_SPINLOCK1_BITS 0xffffffff 1171 #define SIO_SPINLOCK1_RESET 0x00000000 1172 #define SIO_SPINLOCK1_MSB 31 1173 #define SIO_SPINLOCK1_LSB 0 1174 #define SIO_SPINLOCK1_ACCESS "RO" 1175 // ============================================================================= 1176 // Register : SIO_SPINLOCK2 1177 // Description : Reading from a spinlock address will: 1178 // - Return 0 if lock is already locked 1179 // - Otherwise return nonzero, and simultaneously claim the lock 1180 // 1181 // Writing (any value) releases the lock. 1182 // If core 0 and core 1 attempt to claim the same lock 1183 // simultaneously, core 0 wins. 1184 // The value returned on success is 0x1 << lock number. 1185 #define SIO_SPINLOCK2_OFFSET 0x00000108 1186 #define SIO_SPINLOCK2_BITS 0xffffffff 1187 #define SIO_SPINLOCK2_RESET 0x00000000 1188 #define SIO_SPINLOCK2_MSB 31 1189 #define SIO_SPINLOCK2_LSB 0 1190 #define SIO_SPINLOCK2_ACCESS "RO" 1191 // ============================================================================= 1192 // Register : SIO_SPINLOCK3 1193 // Description : Reading from a spinlock address will: 1194 // - Return 0 if lock is already locked 1195 // - Otherwise return nonzero, and simultaneously claim the lock 1196 // 1197 // Writing (any value) releases the lock. 1198 // If core 0 and core 1 attempt to claim the same lock 1199 // simultaneously, core 0 wins. 1200 // The value returned on success is 0x1 << lock number. 1201 #define SIO_SPINLOCK3_OFFSET 0x0000010c 1202 #define SIO_SPINLOCK3_BITS 0xffffffff 1203 #define SIO_SPINLOCK3_RESET 0x00000000 1204 #define SIO_SPINLOCK3_MSB 31 1205 #define SIO_SPINLOCK3_LSB 0 1206 #define SIO_SPINLOCK3_ACCESS "RO" 1207 // ============================================================================= 1208 // Register : SIO_SPINLOCK4 1209 // Description : Reading from a spinlock address will: 1210 // - Return 0 if lock is already locked 1211 // - Otherwise return nonzero, and simultaneously claim the lock 1212 // 1213 // Writing (any value) releases the lock. 1214 // If core 0 and core 1 attempt to claim the same lock 1215 // simultaneously, core 0 wins. 1216 // The value returned on success is 0x1 << lock number. 1217 #define SIO_SPINLOCK4_OFFSET 0x00000110 1218 #define SIO_SPINLOCK4_BITS 0xffffffff 1219 #define SIO_SPINLOCK4_RESET 0x00000000 1220 #define SIO_SPINLOCK4_MSB 31 1221 #define SIO_SPINLOCK4_LSB 0 1222 #define SIO_SPINLOCK4_ACCESS "RO" 1223 // ============================================================================= 1224 // Register : SIO_SPINLOCK5 1225 // Description : Reading from a spinlock address will: 1226 // - Return 0 if lock is already locked 1227 // - Otherwise return nonzero, and simultaneously claim the lock 1228 // 1229 // Writing (any value) releases the lock. 1230 // If core 0 and core 1 attempt to claim the same lock 1231 // simultaneously, core 0 wins. 1232 // The value returned on success is 0x1 << lock number. 1233 #define SIO_SPINLOCK5_OFFSET 0x00000114 1234 #define SIO_SPINLOCK5_BITS 0xffffffff 1235 #define SIO_SPINLOCK5_RESET 0x00000000 1236 #define SIO_SPINLOCK5_MSB 31 1237 #define SIO_SPINLOCK5_LSB 0 1238 #define SIO_SPINLOCK5_ACCESS "RO" 1239 // ============================================================================= 1240 // Register : SIO_SPINLOCK6 1241 // Description : Reading from a spinlock address will: 1242 // - Return 0 if lock is already locked 1243 // - Otherwise return nonzero, and simultaneously claim the lock 1244 // 1245 // Writing (any value) releases the lock. 1246 // If core 0 and core 1 attempt to claim the same lock 1247 // simultaneously, core 0 wins. 1248 // The value returned on success is 0x1 << lock number. 1249 #define SIO_SPINLOCK6_OFFSET 0x00000118 1250 #define SIO_SPINLOCK6_BITS 0xffffffff 1251 #define SIO_SPINLOCK6_RESET 0x00000000 1252 #define SIO_SPINLOCK6_MSB 31 1253 #define SIO_SPINLOCK6_LSB 0 1254 #define SIO_SPINLOCK6_ACCESS "RO" 1255 // ============================================================================= 1256 // Register : SIO_SPINLOCK7 1257 // Description : Reading from a spinlock address will: 1258 // - Return 0 if lock is already locked 1259 // - Otherwise return nonzero, and simultaneously claim the lock 1260 // 1261 // Writing (any value) releases the lock. 1262 // If core 0 and core 1 attempt to claim the same lock 1263 // simultaneously, core 0 wins. 1264 // The value returned on success is 0x1 << lock number. 1265 #define SIO_SPINLOCK7_OFFSET 0x0000011c 1266 #define SIO_SPINLOCK7_BITS 0xffffffff 1267 #define SIO_SPINLOCK7_RESET 0x00000000 1268 #define SIO_SPINLOCK7_MSB 31 1269 #define SIO_SPINLOCK7_LSB 0 1270 #define SIO_SPINLOCK7_ACCESS "RO" 1271 // ============================================================================= 1272 // Register : SIO_SPINLOCK8 1273 // Description : Reading from a spinlock address will: 1274 // - Return 0 if lock is already locked 1275 // - Otherwise return nonzero, and simultaneously claim the lock 1276 // 1277 // Writing (any value) releases the lock. 1278 // If core 0 and core 1 attempt to claim the same lock 1279 // simultaneously, core 0 wins. 1280 // The value returned on success is 0x1 << lock number. 1281 #define SIO_SPINLOCK8_OFFSET 0x00000120 1282 #define SIO_SPINLOCK8_BITS 0xffffffff 1283 #define SIO_SPINLOCK8_RESET 0x00000000 1284 #define SIO_SPINLOCK8_MSB 31 1285 #define SIO_SPINLOCK8_LSB 0 1286 #define SIO_SPINLOCK8_ACCESS "RO" 1287 // ============================================================================= 1288 // Register : SIO_SPINLOCK9 1289 // Description : Reading from a spinlock address will: 1290 // - Return 0 if lock is already locked 1291 // - Otherwise return nonzero, and simultaneously claim the lock 1292 // 1293 // Writing (any value) releases the lock. 1294 // If core 0 and core 1 attempt to claim the same lock 1295 // simultaneously, core 0 wins. 1296 // The value returned on success is 0x1 << lock number. 1297 #define SIO_SPINLOCK9_OFFSET 0x00000124 1298 #define SIO_SPINLOCK9_BITS 0xffffffff 1299 #define SIO_SPINLOCK9_RESET 0x00000000 1300 #define SIO_SPINLOCK9_MSB 31 1301 #define SIO_SPINLOCK9_LSB 0 1302 #define SIO_SPINLOCK9_ACCESS "RO" 1303 // ============================================================================= 1304 // Register : SIO_SPINLOCK10 1305 // Description : Reading from a spinlock address will: 1306 // - Return 0 if lock is already locked 1307 // - Otherwise return nonzero, and simultaneously claim the lock 1308 // 1309 // Writing (any value) releases the lock. 1310 // If core 0 and core 1 attempt to claim the same lock 1311 // simultaneously, core 0 wins. 1312 // The value returned on success is 0x1 << lock number. 1313 #define SIO_SPINLOCK10_OFFSET 0x00000128 1314 #define SIO_SPINLOCK10_BITS 0xffffffff 1315 #define SIO_SPINLOCK10_RESET 0x00000000 1316 #define SIO_SPINLOCK10_MSB 31 1317 #define SIO_SPINLOCK10_LSB 0 1318 #define SIO_SPINLOCK10_ACCESS "RO" 1319 // ============================================================================= 1320 // Register : SIO_SPINLOCK11 1321 // Description : Reading from a spinlock address will: 1322 // - Return 0 if lock is already locked 1323 // - Otherwise return nonzero, and simultaneously claim the lock 1324 // 1325 // Writing (any value) releases the lock. 1326 // If core 0 and core 1 attempt to claim the same lock 1327 // simultaneously, core 0 wins. 1328 // The value returned on success is 0x1 << lock number. 1329 #define SIO_SPINLOCK11_OFFSET 0x0000012c 1330 #define SIO_SPINLOCK11_BITS 0xffffffff 1331 #define SIO_SPINLOCK11_RESET 0x00000000 1332 #define SIO_SPINLOCK11_MSB 31 1333 #define SIO_SPINLOCK11_LSB 0 1334 #define SIO_SPINLOCK11_ACCESS "RO" 1335 // ============================================================================= 1336 // Register : SIO_SPINLOCK12 1337 // Description : Reading from a spinlock address will: 1338 // - Return 0 if lock is already locked 1339 // - Otherwise return nonzero, and simultaneously claim the lock 1340 // 1341 // Writing (any value) releases the lock. 1342 // If core 0 and core 1 attempt to claim the same lock 1343 // simultaneously, core 0 wins. 1344 // The value returned on success is 0x1 << lock number. 1345 #define SIO_SPINLOCK12_OFFSET 0x00000130 1346 #define SIO_SPINLOCK12_BITS 0xffffffff 1347 #define SIO_SPINLOCK12_RESET 0x00000000 1348 #define SIO_SPINLOCK12_MSB 31 1349 #define SIO_SPINLOCK12_LSB 0 1350 #define SIO_SPINLOCK12_ACCESS "RO" 1351 // ============================================================================= 1352 // Register : SIO_SPINLOCK13 1353 // Description : Reading from a spinlock address will: 1354 // - Return 0 if lock is already locked 1355 // - Otherwise return nonzero, and simultaneously claim the lock 1356 // 1357 // Writing (any value) releases the lock. 1358 // If core 0 and core 1 attempt to claim the same lock 1359 // simultaneously, core 0 wins. 1360 // The value returned on success is 0x1 << lock number. 1361 #define SIO_SPINLOCK13_OFFSET 0x00000134 1362 #define SIO_SPINLOCK13_BITS 0xffffffff 1363 #define SIO_SPINLOCK13_RESET 0x00000000 1364 #define SIO_SPINLOCK13_MSB 31 1365 #define SIO_SPINLOCK13_LSB 0 1366 #define SIO_SPINLOCK13_ACCESS "RO" 1367 // ============================================================================= 1368 // Register : SIO_SPINLOCK14 1369 // Description : Reading from a spinlock address will: 1370 // - Return 0 if lock is already locked 1371 // - Otherwise return nonzero, and simultaneously claim the lock 1372 // 1373 // Writing (any value) releases the lock. 1374 // If core 0 and core 1 attempt to claim the same lock 1375 // simultaneously, core 0 wins. 1376 // The value returned on success is 0x1 << lock number. 1377 #define SIO_SPINLOCK14_OFFSET 0x00000138 1378 #define SIO_SPINLOCK14_BITS 0xffffffff 1379 #define SIO_SPINLOCK14_RESET 0x00000000 1380 #define SIO_SPINLOCK14_MSB 31 1381 #define SIO_SPINLOCK14_LSB 0 1382 #define SIO_SPINLOCK14_ACCESS "RO" 1383 // ============================================================================= 1384 // Register : SIO_SPINLOCK15 1385 // Description : Reading from a spinlock address will: 1386 // - Return 0 if lock is already locked 1387 // - Otherwise return nonzero, and simultaneously claim the lock 1388 // 1389 // Writing (any value) releases the lock. 1390 // If core 0 and core 1 attempt to claim the same lock 1391 // simultaneously, core 0 wins. 1392 // The value returned on success is 0x1 << lock number. 1393 #define SIO_SPINLOCK15_OFFSET 0x0000013c 1394 #define SIO_SPINLOCK15_BITS 0xffffffff 1395 #define SIO_SPINLOCK15_RESET 0x00000000 1396 #define SIO_SPINLOCK15_MSB 31 1397 #define SIO_SPINLOCK15_LSB 0 1398 #define SIO_SPINLOCK15_ACCESS "RO" 1399 // ============================================================================= 1400 // Register : SIO_SPINLOCK16 1401 // Description : Reading from a spinlock address will: 1402 // - Return 0 if lock is already locked 1403 // - Otherwise return nonzero, and simultaneously claim the lock 1404 // 1405 // Writing (any value) releases the lock. 1406 // If core 0 and core 1 attempt to claim the same lock 1407 // simultaneously, core 0 wins. 1408 // The value returned on success is 0x1 << lock number. 1409 #define SIO_SPINLOCK16_OFFSET 0x00000140 1410 #define SIO_SPINLOCK16_BITS 0xffffffff 1411 #define SIO_SPINLOCK16_RESET 0x00000000 1412 #define SIO_SPINLOCK16_MSB 31 1413 #define SIO_SPINLOCK16_LSB 0 1414 #define SIO_SPINLOCK16_ACCESS "RO" 1415 // ============================================================================= 1416 // Register : SIO_SPINLOCK17 1417 // Description : Reading from a spinlock address will: 1418 // - Return 0 if lock is already locked 1419 // - Otherwise return nonzero, and simultaneously claim the lock 1420 // 1421 // Writing (any value) releases the lock. 1422 // If core 0 and core 1 attempt to claim the same lock 1423 // simultaneously, core 0 wins. 1424 // The value returned on success is 0x1 << lock number. 1425 #define SIO_SPINLOCK17_OFFSET 0x00000144 1426 #define SIO_SPINLOCK17_BITS 0xffffffff 1427 #define SIO_SPINLOCK17_RESET 0x00000000 1428 #define SIO_SPINLOCK17_MSB 31 1429 #define SIO_SPINLOCK17_LSB 0 1430 #define SIO_SPINLOCK17_ACCESS "RO" 1431 // ============================================================================= 1432 // Register : SIO_SPINLOCK18 1433 // Description : Reading from a spinlock address will: 1434 // - Return 0 if lock is already locked 1435 // - Otherwise return nonzero, and simultaneously claim the lock 1436 // 1437 // Writing (any value) releases the lock. 1438 // If core 0 and core 1 attempt to claim the same lock 1439 // simultaneously, core 0 wins. 1440 // The value returned on success is 0x1 << lock number. 1441 #define SIO_SPINLOCK18_OFFSET 0x00000148 1442 #define SIO_SPINLOCK18_BITS 0xffffffff 1443 #define SIO_SPINLOCK18_RESET 0x00000000 1444 #define SIO_SPINLOCK18_MSB 31 1445 #define SIO_SPINLOCK18_LSB 0 1446 #define SIO_SPINLOCK18_ACCESS "RO" 1447 // ============================================================================= 1448 // Register : SIO_SPINLOCK19 1449 // Description : Reading from a spinlock address will: 1450 // - Return 0 if lock is already locked 1451 // - Otherwise return nonzero, and simultaneously claim the lock 1452 // 1453 // Writing (any value) releases the lock. 1454 // If core 0 and core 1 attempt to claim the same lock 1455 // simultaneously, core 0 wins. 1456 // The value returned on success is 0x1 << lock number. 1457 #define SIO_SPINLOCK19_OFFSET 0x0000014c 1458 #define SIO_SPINLOCK19_BITS 0xffffffff 1459 #define SIO_SPINLOCK19_RESET 0x00000000 1460 #define SIO_SPINLOCK19_MSB 31 1461 #define SIO_SPINLOCK19_LSB 0 1462 #define SIO_SPINLOCK19_ACCESS "RO" 1463 // ============================================================================= 1464 // Register : SIO_SPINLOCK20 1465 // Description : Reading from a spinlock address will: 1466 // - Return 0 if lock is already locked 1467 // - Otherwise return nonzero, and simultaneously claim the lock 1468 // 1469 // Writing (any value) releases the lock. 1470 // If core 0 and core 1 attempt to claim the same lock 1471 // simultaneously, core 0 wins. 1472 // The value returned on success is 0x1 << lock number. 1473 #define SIO_SPINLOCK20_OFFSET 0x00000150 1474 #define SIO_SPINLOCK20_BITS 0xffffffff 1475 #define SIO_SPINLOCK20_RESET 0x00000000 1476 #define SIO_SPINLOCK20_MSB 31 1477 #define SIO_SPINLOCK20_LSB 0 1478 #define SIO_SPINLOCK20_ACCESS "RO" 1479 // ============================================================================= 1480 // Register : SIO_SPINLOCK21 1481 // Description : Reading from a spinlock address will: 1482 // - Return 0 if lock is already locked 1483 // - Otherwise return nonzero, and simultaneously claim the lock 1484 // 1485 // Writing (any value) releases the lock. 1486 // If core 0 and core 1 attempt to claim the same lock 1487 // simultaneously, core 0 wins. 1488 // The value returned on success is 0x1 << lock number. 1489 #define SIO_SPINLOCK21_OFFSET 0x00000154 1490 #define SIO_SPINLOCK21_BITS 0xffffffff 1491 #define SIO_SPINLOCK21_RESET 0x00000000 1492 #define SIO_SPINLOCK21_MSB 31 1493 #define SIO_SPINLOCK21_LSB 0 1494 #define SIO_SPINLOCK21_ACCESS "RO" 1495 // ============================================================================= 1496 // Register : SIO_SPINLOCK22 1497 // Description : Reading from a spinlock address will: 1498 // - Return 0 if lock is already locked 1499 // - Otherwise return nonzero, and simultaneously claim the lock 1500 // 1501 // Writing (any value) releases the lock. 1502 // If core 0 and core 1 attempt to claim the same lock 1503 // simultaneously, core 0 wins. 1504 // The value returned on success is 0x1 << lock number. 1505 #define SIO_SPINLOCK22_OFFSET 0x00000158 1506 #define SIO_SPINLOCK22_BITS 0xffffffff 1507 #define SIO_SPINLOCK22_RESET 0x00000000 1508 #define SIO_SPINLOCK22_MSB 31 1509 #define SIO_SPINLOCK22_LSB 0 1510 #define SIO_SPINLOCK22_ACCESS "RO" 1511 // ============================================================================= 1512 // Register : SIO_SPINLOCK23 1513 // Description : Reading from a spinlock address will: 1514 // - Return 0 if lock is already locked 1515 // - Otherwise return nonzero, and simultaneously claim the lock 1516 // 1517 // Writing (any value) releases the lock. 1518 // If core 0 and core 1 attempt to claim the same lock 1519 // simultaneously, core 0 wins. 1520 // The value returned on success is 0x1 << lock number. 1521 #define SIO_SPINLOCK23_OFFSET 0x0000015c 1522 #define SIO_SPINLOCK23_BITS 0xffffffff 1523 #define SIO_SPINLOCK23_RESET 0x00000000 1524 #define SIO_SPINLOCK23_MSB 31 1525 #define SIO_SPINLOCK23_LSB 0 1526 #define SIO_SPINLOCK23_ACCESS "RO" 1527 // ============================================================================= 1528 // Register : SIO_SPINLOCK24 1529 // Description : Reading from a spinlock address will: 1530 // - Return 0 if lock is already locked 1531 // - Otherwise return nonzero, and simultaneously claim the lock 1532 // 1533 // Writing (any value) releases the lock. 1534 // If core 0 and core 1 attempt to claim the same lock 1535 // simultaneously, core 0 wins. 1536 // The value returned on success is 0x1 << lock number. 1537 #define SIO_SPINLOCK24_OFFSET 0x00000160 1538 #define SIO_SPINLOCK24_BITS 0xffffffff 1539 #define SIO_SPINLOCK24_RESET 0x00000000 1540 #define SIO_SPINLOCK24_MSB 31 1541 #define SIO_SPINLOCK24_LSB 0 1542 #define SIO_SPINLOCK24_ACCESS "RO" 1543 // ============================================================================= 1544 // Register : SIO_SPINLOCK25 1545 // Description : Reading from a spinlock address will: 1546 // - Return 0 if lock is already locked 1547 // - Otherwise return nonzero, and simultaneously claim the lock 1548 // 1549 // Writing (any value) releases the lock. 1550 // If core 0 and core 1 attempt to claim the same lock 1551 // simultaneously, core 0 wins. 1552 // The value returned on success is 0x1 << lock number. 1553 #define SIO_SPINLOCK25_OFFSET 0x00000164 1554 #define SIO_SPINLOCK25_BITS 0xffffffff 1555 #define SIO_SPINLOCK25_RESET 0x00000000 1556 #define SIO_SPINLOCK25_MSB 31 1557 #define SIO_SPINLOCK25_LSB 0 1558 #define SIO_SPINLOCK25_ACCESS "RO" 1559 // ============================================================================= 1560 // Register : SIO_SPINLOCK26 1561 // Description : Reading from a spinlock address will: 1562 // - Return 0 if lock is already locked 1563 // - Otherwise return nonzero, and simultaneously claim the lock 1564 // 1565 // Writing (any value) releases the lock. 1566 // If core 0 and core 1 attempt to claim the same lock 1567 // simultaneously, core 0 wins. 1568 // The value returned on success is 0x1 << lock number. 1569 #define SIO_SPINLOCK26_OFFSET 0x00000168 1570 #define SIO_SPINLOCK26_BITS 0xffffffff 1571 #define SIO_SPINLOCK26_RESET 0x00000000 1572 #define SIO_SPINLOCK26_MSB 31 1573 #define SIO_SPINLOCK26_LSB 0 1574 #define SIO_SPINLOCK26_ACCESS "RO" 1575 // ============================================================================= 1576 // Register : SIO_SPINLOCK27 1577 // Description : Reading from a spinlock address will: 1578 // - Return 0 if lock is already locked 1579 // - Otherwise return nonzero, and simultaneously claim the lock 1580 // 1581 // Writing (any value) releases the lock. 1582 // If core 0 and core 1 attempt to claim the same lock 1583 // simultaneously, core 0 wins. 1584 // The value returned on success is 0x1 << lock number. 1585 #define SIO_SPINLOCK27_OFFSET 0x0000016c 1586 #define SIO_SPINLOCK27_BITS 0xffffffff 1587 #define SIO_SPINLOCK27_RESET 0x00000000 1588 #define SIO_SPINLOCK27_MSB 31 1589 #define SIO_SPINLOCK27_LSB 0 1590 #define SIO_SPINLOCK27_ACCESS "RO" 1591 // ============================================================================= 1592 // Register : SIO_SPINLOCK28 1593 // Description : Reading from a spinlock address will: 1594 // - Return 0 if lock is already locked 1595 // - Otherwise return nonzero, and simultaneously claim the lock 1596 // 1597 // Writing (any value) releases the lock. 1598 // If core 0 and core 1 attempt to claim the same lock 1599 // simultaneously, core 0 wins. 1600 // The value returned on success is 0x1 << lock number. 1601 #define SIO_SPINLOCK28_OFFSET 0x00000170 1602 #define SIO_SPINLOCK28_BITS 0xffffffff 1603 #define SIO_SPINLOCK28_RESET 0x00000000 1604 #define SIO_SPINLOCK28_MSB 31 1605 #define SIO_SPINLOCK28_LSB 0 1606 #define SIO_SPINLOCK28_ACCESS "RO" 1607 // ============================================================================= 1608 // Register : SIO_SPINLOCK29 1609 // Description : Reading from a spinlock address will: 1610 // - Return 0 if lock is already locked 1611 // - Otherwise return nonzero, and simultaneously claim the lock 1612 // 1613 // Writing (any value) releases the lock. 1614 // If core 0 and core 1 attempt to claim the same lock 1615 // simultaneously, core 0 wins. 1616 // The value returned on success is 0x1 << lock number. 1617 #define SIO_SPINLOCK29_OFFSET 0x00000174 1618 #define SIO_SPINLOCK29_BITS 0xffffffff 1619 #define SIO_SPINLOCK29_RESET 0x00000000 1620 #define SIO_SPINLOCK29_MSB 31 1621 #define SIO_SPINLOCK29_LSB 0 1622 #define SIO_SPINLOCK29_ACCESS "RO" 1623 // ============================================================================= 1624 // Register : SIO_SPINLOCK30 1625 // Description : Reading from a spinlock address will: 1626 // - Return 0 if lock is already locked 1627 // - Otherwise return nonzero, and simultaneously claim the lock 1628 // 1629 // Writing (any value) releases the lock. 1630 // If core 0 and core 1 attempt to claim the same lock 1631 // simultaneously, core 0 wins. 1632 // The value returned on success is 0x1 << lock number. 1633 #define SIO_SPINLOCK30_OFFSET 0x00000178 1634 #define SIO_SPINLOCK30_BITS 0xffffffff 1635 #define SIO_SPINLOCK30_RESET 0x00000000 1636 #define SIO_SPINLOCK30_MSB 31 1637 #define SIO_SPINLOCK30_LSB 0 1638 #define SIO_SPINLOCK30_ACCESS "RO" 1639 // ============================================================================= 1640 // Register : SIO_SPINLOCK31 1641 // Description : Reading from a spinlock address will: 1642 // - Return 0 if lock is already locked 1643 // - Otherwise return nonzero, and simultaneously claim the lock 1644 // 1645 // Writing (any value) releases the lock. 1646 // If core 0 and core 1 attempt to claim the same lock 1647 // simultaneously, core 0 wins. 1648 // The value returned on success is 0x1 << lock number. 1649 #define SIO_SPINLOCK31_OFFSET 0x0000017c 1650 #define SIO_SPINLOCK31_BITS 0xffffffff 1651 #define SIO_SPINLOCK31_RESET 0x00000000 1652 #define SIO_SPINLOCK31_MSB 31 1653 #define SIO_SPINLOCK31_LSB 0 1654 #define SIO_SPINLOCK31_ACCESS "RO" 1655 // ============================================================================= 1656 #endif // HARDWARE_REGS_SIO_DEFINED 1657