1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef INTERNAL_REG_DMA330_H 9 #define INTERNAL_REG_DMA330_H 10 11 #include <stdbool.h> 12 #include <stdint.h> 13 14 #ifdef RESERVED_AREA_BYTE 15 #undef RESERVED_AREA_BYTE 16 #endif 17 #define RESERVED_AREA_BYTE(var1, var2) \ 18 unsigned char reserved_##var1_##var2 \ 19 [(((var2) + 1) - (var1)) / sizeof(unsigned char)] 20 21 #ifdef RESERVED_AREA_HALF 22 #undef RESERVED_AREA_HALF 23 #endif 24 #define RESERVED_AREA_HALF(var1, var2) \ 25 unsigned short reserved_##var1_##var2 \ 26 [(((var2) + 1) - (var1)) / sizeof(unsigned short)] 27 28 #ifdef RESERVED_AREA_WORD 29 #undef RESERVED_AREA_WORD 30 #endif 31 #define RESERVED_AREA_WORD(var1, var2) \ 32 unsigned long reserved_##var1_##var2 \ 33 [(((var2) + 1) - (var1)) / sizeof(unsigned long)] 34 35 typedef struct { 36 uint32_t CSR; /* 0x100,...,0x138 Channel status for DMA channel 0~7 */ 37 uint32_t CPC; /* 0x104,...,0x13C Channel PC for DMA channel 0~7 */ 38 } REG_ST_DMA330_CT_t; 39 40 typedef struct { 41 uint32_t SAR; /* 0x400,...,0x4E0 Source address for DMA channel 0~7 */ 42 uint32_t DAR; /* 0x404,...,0x4E4 Destination address for DMA channel 0~7 */ 43 uint32_t CCR; /* 0x408,...,0x4E8 Channel control for DMA channel 0~7 */ 44 uint32_t LC0; /* 0x40C,...,0x4EC Loop counter 0 for DMA channel 0~7 */ 45 uint32_t LC1; /* 0x410,...,0x4F0 Loop counter 1 for DMA channel 0~7 */ 46 uint32_t reserved[3]; 47 } REG_ST_DMA330_AS_t; 48 49 typedef union { 50 uint32_t DATA; 51 struct { 52 uint32_t SRC_INC : 1; /* B00 */ 53 uint32_t SRC_BURST_SIZE : 3; /* B01-B03 */ 54 uint32_t SRC_BURST_LEN : 4; /* B04-B07 */ 55 uint32_t SRC_PROT_CTRL : 3; /* B08-B10 */ 56 uint32_t SRC_CACHE_CTRL : 3; /* B11-B13 */ 57 uint32_t DST_INC : 1; /* B14 */ 58 uint32_t DST_BURST_SIZE : 3; /* B15-B17 */ 59 uint32_t DST_BURST_LEN : 4; /* B18-B21 */ 60 uint32_t DST_PROT_CTRL : 3; /* B22-B24 */ 61 uint32_t DST_CACHE_CTRL : 3; /* B25-B27 */ 62 uint32_t ENDIAN_SWAP_SIZE : 3; /* B28-B30 */ 63 uint32_t reserved1 : 1; /* B31 Reserved */ 64 } bit; 65 } DMA330_UN_CCR_t; 66 67 #define DMA330_MAKE_CCR(ES, DC, DP, DL, DS, DI, SC, SP, SL, SS, SI) \ 68 (((ES) << 28) | ((DC) << 25) | ((DP) << 22) | ((DL) << 18) | \ 69 ((DS) << 15) | ((DI) << 14) | ((SC) << 11) | ((SP) << 8) | ((SL) << 4) | \ 70 ((SS) << 1) | ((SI) << 0)) 71 72 typedef union { 73 uint32_t DATA; 74 struct { 75 uint32_t FS_MGR : 1; /* B00 */ 76 uint32_t reserved1 : 31; /* B01-B31 Reserved */ 77 } bit; 78 } DMA330_UN_FSRD_t; 79 80 typedef union { 81 uint32_t DATA; 82 struct { 83 uint32_t CH0 : 1; /* B00 */ 84 uint32_t CH1 : 1; /* B01 */ 85 uint32_t CH2 : 1; /* B02 */ 86 uint32_t CH3 : 1; /* B03 */ 87 uint32_t CH4 : 1; /* B04 */ 88 uint32_t CH5 : 1; /* B05 */ 89 uint32_t CH6 : 1; /* B06 */ 90 uint32_t CH7 : 1; /* B07 */ 91 uint32_t reserved1 : 24; /* B08-B31 Reserved */ 92 } bit; 93 } DMA330_UN_FSRC_t; 94 95 // 3.3.9 Fault Type DMA Manager Register 96 typedef union { 97 uint32_t DATA; 98 struct { 99 uint32_t UNDEF_INSTR : 1; /* B00 */ 100 uint32_t OPERAND_INVALID : 1; /* B01 */ 101 uint32_t reserved1 : 2; /* B02-B03 Reserved */ 102 uint32_t DMAGO_ERR : 1; /* B04 */ 103 uint32_t MGR_EVNT_ERR : 1; /* B05 */ 104 uint32_t reserved2 : 10; /* B06-B15 Reserved */ 105 uint32_t INSTR_FETCH_ERR : 1; /* B16 */ 106 uint32_t reserved3 : 13; /* B17-B29 Reserved */ 107 uint32_t DBG_INSTR : 1; /* B30 */ 108 uint32_t reserved4 : 1; /* B31 Reserved */ 109 } bit; 110 } DMA330_UN_FTRD_t; 111 112 // Fault Type DMA Channel Registers 113 typedef union { 114 uint32_t DATA; 115 struct { 116 uint32_t UNDEF_INSTR : 1; /* B00 */ 117 uint32_t OPERAND_INVALID : 1; /* B01 */ 118 uint32_t reserved1 : 3; /* B02-B04 Reserved */ 119 uint32_t CH_EVNT_ERR : 1; /* B05 */ 120 uint32_t CH_PERIPH_ERR : 1; /* B06 */ 121 uint32_t CH_RDWR_ERR : 1; /* B07 */ 122 uint32_t reserved2 : 4; /* B08-B11 Reserved */ 123 uint32_t MFIFO_ERR : 1; /* B12 */ 124 uint32_t ST_DATA_UNAVAILABLE : 1; /* B13 */ 125 uint32_t reserved3 : 2; /* B14-B15 Reserved */ 126 uint32_t INSTR_FETCH_ERR : 1; /* B16 */ 127 uint32_t DATA_WRITE_ERR : 1; /* B17 */ 128 uint32_t DATA_READ_ERR : 1; /* B18 */ 129 uint32_t reserved4 : 11; /* B19-B29 Reserved */ 130 uint32_t DBG_INSTR : 1; /* B30 */ 131 uint32_t LOCKUP_ERR : 1; /* B31 */ 132 } bit; 133 } DMA330_UN_FTR_t; 134 135 typedef struct { 136 uint32_t DSR; /* +0x000 DMA Manager Status Register */ 137 uint32_t DPC; /* +0x004 DMA Program Counter Register */ 138 RESERVED_AREA_WORD(0x008, 0x01F); 139 uint32_t INTEN; /* +0x020 Interrupt Enable Register */ 140 uint32_t INT_EVENT_RIS; /* +0x024 Event-Interrupt Raw Status Register */ 141 uint32_t INTMIS; /* +0x028 Interrupt Status Register */ 142 uint32_t INTCLR; /* +0x02C Interrupt Clear Register */ 143 uint32_t FSRD; /* +0x030 Fault Status DMA Manager Register */ 144 uint32_t FSRC; /* +0x034 Fault Status DMA Channel Register */ 145 uint32_t FTRD; /* +0x038 Fault Type DMA Manager Register */ 146 RESERVED_AREA_WORD(0x03C, 0x03F); 147 uint32_t FTR[8]; /* +0x040-0x05C Fault Type DMA Channel Registers */ 148 RESERVED_AREA_WORD(0x060, 0x0FF); 149 REG_ST_DMA330_CT_t 150 CT[8]; /* +0x100-0x13C DMA Channel Thread Status Register */ 151 RESERVED_AREA_WORD(0x140, 0x3FF); 152 REG_ST_DMA330_AS_t 153 AS[8]; /* +0x400-0x4FC AXI Status And Loop Counter Register */ 154 RESERVED_AREA_WORD(0x500, 0xCFF); 155 uint32_t DBGSTATUS; /* +0xD00 Debug Status Register */ 156 uint32_t DBGCMD; /* +0xD04 Debug Command Register */ 157 uint32_t DBGINST[2]; /* +0xD08-0xD0C Debug Instruction-0,1 Register */ 158 RESERVED_AREA_WORD(0xD10, 0xDFF); 159 uint32_t CR[5]; /* +0xE00-0xE10 Configuration Register 0~4 */ 160 uint32_t CRD; /* +0xE14 DMA Configuration Register */ 161 RESERVED_AREA_WORD(0xE18, 0xE7F); 162 uint32_t WD; /* +0xE80 Watchdog Register */ 163 RESERVED_AREA_WORD(0xE84, 0xFDF); 164 uint32_t 165 PERIPH_ID[4]; /* +0xFE0-0xFEC Peripheral Identification Registers */ 166 uint32_t 167 PCELL_ID[4]; /* +0xFF0-0xFFC Component Identification Registers 0-3 */ 168 } REG_ST_DMA330_S_t; 169 170 typedef struct { 171 uint32_t DSR; /* +0x000 */ 172 uint32_t DPC; /* +0x004 */ 173 RESERVED_AREA_WORD(0x008, 0x01F); 174 uint32_t INTEN; /* +0x020 */ 175 uint32_t INT_EVENT_RIS; /* +0x024 */ 176 uint32_t INTMIS; /* +0x028 */ 177 uint32_t INTCLR; /* +0x02C */ 178 uint32_t FSRD; /* +0x030 */ 179 uint32_t FSRC; /* +0x034 */ 180 uint32_t FTRD; /* +0x038 */ 181 RESERVED_AREA_WORD(0x03C, 0x03F); 182 uint32_t FTR[8]; /* +0x040-0x05C */ 183 RESERVED_AREA_WORD(0x060, 0x0FF); 184 REG_ST_DMA330_CT_t CT[8]; /* +0x100-0x13C */ 185 RESERVED_AREA_WORD(0x140, 0x3FF); 186 REG_ST_DMA330_AS_t AS[8]; /* +0x400-0x4FC */ 187 RESERVED_AREA_WORD(0x500, 0xCFF); 188 uint32_t DBGSTATUS; /* +0xD00 */ 189 uint32_t DBGCMD; /* +0xD04 */ 190 uint32_t DBGINST[2]; /* +0xD08-0xD0C */ 191 RESERVED_AREA_WORD(0xD10, 0xDFF); 192 uint32_t CR[5]; /* +0xE00-0xE10 */ 193 uint32_t CRD; /* +0xE14 */ 194 RESERVED_AREA_WORD(0xE18, 0xE7F); 195 uint32_t WD; /* +0xE80 */ 196 RESERVED_AREA_WORD(0xE84, 0xFDF); 197 uint32_t PERIPH_ID[4]; /* +0xFE0-0xFEC */ 198 uint32_t PCELL_ID[4]; /* +0xFF0-0xFFC */ 199 200 } REG_ST_DMA330_NS_t; 201 202 #endif /* INTERNAL_REG_DMA330_H */ 203