1ENTRY(Reset_Handler) 2 3MEMORY 4{ 5 IROM (rx) : ORIGIN = 0x10100000, LENGTH = 0x1010A000 - 0x10100000 /* ROM: 40k */ 6 IROM_NS (rx) : ORIGIN = 0x1010A000, LENGTH = 0x10140000 - 0x1010A000 /* ROM: 216k */ 7 DROM_NS (rx) : ORIGIN = 0x101C0000, LENGTH = 0x101D4000 - 0x101C0000 /* ROM: 80k */ 8 DROM (rx) : ORIGIN = 0x101D4000, LENGTH = 0x101D8000 - 0x101D4000 /* ROM: 16k */ 9 ROMBSS_RAM_COM (rw) : ORIGIN = 0x10000000, LENGTH = 0x10001000 - 0x10000000 /* ROM BSS COMMON(S & NS both used) RAM: 4K */ 10 ROMBSS_RAM_NS (rw) : ORIGIN = 0x10001000, LENGTH = 0x10002000 - 0x10001000 /* ROM BSS NS RAM: 4K */ 11 RSVD_RAM_NS (rw) : ORIGIN = 0x10002000, LENGTH = 0x10004000 - 0x10002000 /* RSVD RAM: 8K */ 12 MSP_RAM_NS (rw) : ORIGIN = 0x10004000, LENGTH = 0x10005000 - 0x10004000 /* MSP_NS RAM: 4K */ 13 14 BD_RAM_NS (rwx) : ORIGIN = 0x10005000, LENGTH = 0x1007C000 - 0x10005000 /* MAIN RAM NS: 456K */ 15 ROMBSS_RAM_S (rwx) : ORIGIN = 0x1007C000, LENGTH = 0x1007D000 - 0x1007C000 /* ROM BSS RAM S: 4K */ 16 BOOTLOADER_RAM_S (rwx) : ORIGIN = 0x1007D000, LENGTH = 0x1007F000 - 0x1007D000 /* BOOT Loader RAM: 8K */ 17 MSP_RAM_S (rwx) : ORIGIN = 0x1007F000, LENGTH = 0x10080000 - 0x1007F000 /* MSP_S RAM: 4k */ 18 EXTENTION_SRAM (rwx) : ORIGIN = 0x100E0000, LENGTH = 0x10100000 - 0x100E0000 /* EXTENTION SRAM: 128k */ 19 20 PSRAM_NS (rwx) : ORIGIN = 0x02000000 + 0x20, LENGTH = 0x02400000 - 0x02000000 - 0x20 /* PSRAM_NS: 4M */ 21 22 /* Flash */ 23 KM0_BOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x02000-0x20 /* XIPBOOT: 8k, 32 Bytes resvd for header*/ 24 BACKUP (r) : ORIGIN = 0x08002000, LENGTH = 0x1000 /* BACKUP: 4K system data in flash */ 25 XIPSYS (r) : ORIGIN = 0x08003000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */ 26 KM4_BOOT (rx) : ORIGIN = 0x08004000+0x20, LENGTH = 0x02000-0x20 /* XIPBOOT: 8k, 32 Bytes resvd for header*/ 27 KM0_IMG2 (rx) : ORIGIN = 0x0C000000+0x20, LENGTH = 0x02000000-0x20 /* KM0_IMG2: 32MB, 32 Bytes resvd for header, virtual address */ 28 KM4_IMG2 (rx) : ORIGIN = 0x0E000000+0x20, LENGTH = 0x02000000-0x20 /* KM4_IMG2 OTA1: 32MB, 32 Bytes resvd for header, virtual address */ 29 BTRACE (rx) : ORIGIN = 0x00800000, LENGTH = 0x00C00000 -0x00800000 /* Bluetooth Trace */ 30 31 /* KM0 RAM*/ 32 KM0_SRAM (rwx) : ORIGIN = 0x00080000, LENGTH = 0x00090000 - 0x00080000 /* KM0 SRAM: 64k */ 33 RETENTION_RAM (rwx) : ORIGIN = 0x000C0000, LENGTH = 0x000C0400 - 0x000C0000 /* KM0 Retention SRAM: 1k */ 34} 35 36SECTIONS 37{ 38 .rom.text : { } > IROM_NS 39 .rom.rodata : { } > DROM_NS 40 .hal.rom.bss : { } > ROMBSS_RAM_COM 41 .hal.ns_rom.bss : { } > ROMBSS_RAM_NS 42 43 /* image2: normal image start */ 44 .ram_image2.entry : 45 { 46 __ram_image2_text_start__ = .; 47 __image2_entry_func__ = .; 48 KEEP(*(SORT(.image2.entry.data*))) 49 50 __image2_validate_code__ = .; 51 KEEP(*(.image2.validate.rodata*)) 52 53 } > BD_RAM_NS 54 55 .ram_image2.text : 56 { 57 __ram_text_start__ = .; 58 *(.image2.ram.text*) 59 *(.image2.net.ram.text*) 60 __ram_text_end__ = .; 61 } > BD_RAM_NS 62 63 .ram_image2.data : 64 { 65 __data_start__ = .; 66 *(.data*) 67 __data_end__ = .; 68 __ram_image2_text_end__ = .; 69 . = ALIGN(16); 70 } > BD_RAM_NS 71 72 .ram_image2.bss : 73 { 74 __bss_start__ = .; 75 *(.bss*) 76 *(COMMON) 77 __bss_end__ = .; 78 } > BD_RAM_NS 79 80 .ram_image2.nocache.data : 81 { 82 . = ALIGN (32); 83 __ram_nocache_start__ = .; 84 *(.bdsram.data*) 85 . = ALIGN (32); 86 __ram_nocache_end__ = .; 87 } > BD_RAM_NS 88 89 .ram_heap.data : 90 { 91 . = ALIGN (32); 92 *(.bfsram.data*) 93 end = .; 94 *(.heap.stdlib*) 95 . = . + 4096; 96 __bfsram_end__ = .; 97 } > BD_RAM_NS 98 99 . = ALIGN(8); 100 PROVIDE(heap_start = .); 101 PROVIDE(heap_end = 0x1007A000); 102 PROVIDE(heap_len = heap_end - heap_start); 103 104 .xip_image2.text : 105 { 106 __flash_text_start__ = .; 107 108 *(.img2_custom_signature*) 109 110 *(.text*) 111 /* *(.image2.net.ram.text*) */ 112 *(.rodata*) 113 114 /* Add This for C++ support */ 115 . = ALIGN(4); 116 PROVIDE_HIDDEN (__preinit_array_start = .); 117 KEEP(*(.preinit_array)) 118 PROVIDE_HIDDEN (__preinit_array_end = .); 119 . = ALIGN(4); 120 PROVIDE(__ctors_start__ = .); 121 PROVIDE_HIDDEN (__init_array_start = .); 122 KEEP(*(SORT(.init_array.*))) 123 KEEP(*(.init_array)) 124 PROVIDE_HIDDEN (__init_array_end = .); 125 PROVIDE(__ctors_end__ = .); 126 . = ALIGN(4); 127 PROVIDE(__dtors_start__ = .); 128 PROVIDE_HIDDEN (__fini_array_start = .); 129 KEEP(*(SORT(.fini_array.*))) 130 KEEP(*(.fini_array)) 131 PROVIDE_HIDDEN (__fini_array_end = .); 132 PROVIDE(__dtors_end__ = .); 133 /*-----------------*/ 134 135 . = ALIGN (4); 136 __cmd_table_start__ = .; 137 KEEP(*(.cmd.table.data*)) 138 __cmd_table_end__ = .; 139 140 /************** added drivers **************/ 141 _cli_region_begin = .; 142 KEEP(*(CliRegion)) 143 . = ALIGN(4); 144 _cli_region_end = .; 145 146 __core_driver_start__ = .; 147 KEEP(*(.core_driver_entry)) 148 . = ALIGN(4); 149 __core_driver_end__ = .; 150 151 __bus_driver_start__ = .; 152 KEEP(*(*.bus_driver_entry)) 153 __bus_driver_end__ = .; 154 155 __early_driver_start__ = .; 156 KEEP(*(*.early_driver_entry)) 157 __early_driver_end__ = .; 158 159 __vfs_driver_start__ = .; 160 KEEP(*(*.vfs_driver_entry)) 161 __vfs_driver_end__ = .; 162 163 __level0_driver_start__ = .; 164 KEEP(*(*.level0_driver_entry)) 165 __level0_driver_end__ = .; 166 167 __level1_driver_start__ = .; 168 KEEP(*(*.level1_driver_entry)) 169 __level1_driver_end__ = .; 170 171 __level2_driver_start__ = .; 172 KEEP(*(*.level2_driver_entry)) 173 __level2_driver_end__ = .; 174 175 __level3_driver_start__ = .; 176 KEEP(*(*.level3_driver_entry)) 177 __level3_driver_end__ = .; 178 179 __post_driver_start__ = .; 180 KEEP(*(*.post_driver_entry)) 181 __post_driver_end__ = .; 182/************** end of drivers *********/ 183 184 __flash_text_end__ = .; 185 186 . = ALIGN (16); 187 } > KM4_IMG2 188 189 /* Add This for C++ support */ 190 .ARM.extab : 191 { 192 *(.ARM.extab* .gnu.linkonce.armextab.*) 193 194 } > KM4_IMG2 195 196 .ARM.exidx : 197 { 198 __exidx_start = .; 199 *(.ARM.exidx* .gnu.linkonce.armexidx.*) 200 __exidx_end = .; 201 } > KM4_IMG2 202 /*-----------------*/ 203 204 .bluetooth_trace.text : 205 { 206 __btrace_start__ = .; 207 *(.BTTRACE) 208 __btrace_end__ = .; 209 } > BTRACE 210 211 /* PSRAM_NS image start */ 212 .psram_image2.text : 213 { 214 __psram_image2_text_start__ = .; 215 *(.psram.text*) 216 __psram_image2_text_end__ = .; 217 } > PSRAM_NS 218 219 .psram_image2.data : 220 { 221 . = ALIGN (32); 222 *(.psram.data*) 223 . = ALIGN (32); 224 *(.psram.rodata*) 225 } > PSRAM_NS 226 227 .psram_image2.bss : 228 { 229 . = ALIGN (32); 230 __psram_bss_start__ = .; 231 *(.psram.bss*) 232 __psram_bss_end__ = .; 233 } > PSRAM_NS 234 235 .psram_heap.data : 236 { 237 . = ALIGN (32); 238 *(.psram.heap*) 239 } > PSRAM_NS 240} 241 242__sram_end__ = ORIGIN(BD_RAM_NS) + LENGTH(BD_RAM_NS); 243SECTIONS 244{ 245 __rom_bss_start__ = 0x10000000; 246 ConfigDebugClose = 0x10000000; 247 ConfigDebugBuffer = 0x10000004; 248 ConfigDebugBufferGet = 0x10000008; 249 ConfigDebug = 0x1000000c; 250 rand_first = 0x1000001c; 251 rand_seed = 0x10000020; 252 RBSS_UDELAY_DIV = 0x10000034; 253 flash_init_para = 0x10000038; 254 GDMA_Reg = 0x10000098; 255 PortA_IrqHandler = 0x1000009c; 256 PortA_IrqData = 0x1000011c; 257 PortB_IrqHandler = 0x1000019c; 258 PortB_IrqData = 0x1000021c; 259 IPC_IrqHandler = 0x1000029c; 260 IPC_IrqData = 0x1000031c; 261 IS_FPGA_VERIF = 0x1000039c; 262 crypto_engine = 0x100003a0; 263 __rom_bss_end__ = 0x10000564; 264 __rom_bss_start_ns__ = 0x10001000; 265 NewVectorTable = 0x10001000; 266 UserIrqFunTable = 0x10001140; 267 UserIrqDataTable = 0x10001240; 268 mpu_entry_register = 0x10001340; 269 p_rom_ssl_ram_map = 0x10001348; 270 rom_ssl_ram_map = 0x1000134c; 271 __rom_bss_end_ns__ = 0x1000138c; 272 __rom_bss_start_s__ = 0x1007c000; 273 __ram_start_table_start__ = 0x1007d000; 274 STACK_TOP = 0x1007effc; 275 __vectors_table = 0x1010a000; 276 Reset_Handler = 0x1010a101; 277 NMI_Handler = 0x1010a111; 278 SecureFault_Handler = 0x1010a125; 279 DiagVSprintf = 0x1010a12d; 280 DiagPrintf = 0x1010a3f5; 281 DiagPrintfD = 0x1010a445; 282 DiagSPrintf = 0x1010a471; 283 DiagSnPrintf = 0x1010a49d; 284 Rand = 0x1010a765; 285 Rand_Arc4 = 0x1010a7f1; 286 RandBytes_Get = 0x1010a825; 287 io_assert_failed = 0x1010a871; 288 BKUP_Write = 0x1010a891; 289 BKUP_Read = 0x1010a8b5; 290 BKUP_Set = 0x1010a8d5; 291 BKUP_Clear = 0x1010a8fd; 292 BOOT_Reason = 0x1010a929; 293 DelayNop = 0x1010a939; 294 DelayUs = 0x1010a949; 295 DelayMs = 0x1010a995; 296 EFUSEPowerSwitch = 0x1010a9a9; 297 EFUSERead8 = 0x1010aa31; 298 EFUSEWrite8 = 0x1010ab1d; 299 EFUSE_PG_Packet = 0x1010ac21; 300 EFUSE_LogicalMap_Read = 0x1010ae99; 301 EFUSE_LogicalMap_Write = 0x1010afad; 302 FLASH_RxData = 0x1010b195; 303 FLASH_TxCmd = 0x1010b29d; 304 FLASH_SW_CS_Control = 0x1010b329; 305 FLASH_SetSpiMode = 0x1010b37d; 306 FLASH_RxCmd = 0x1010b415; 307 FLASH_WaitBusy = 0x1010b479; 308 FLASH_WriteEn = 0x1010b4f9; 309 FLASH_TxData256B = 0x1010b51d; 310 FLASH_TxData12B = 0x1010b60d; 311 FLASH_SetStatus = 0x1010b6ed; 312 FLASH_Erase = 0x1010b70d; 313 FLASH_DeepPowerDown = 0x1010b7b9; 314 FLASH_SetStatusBits = 0x1010b809; 315 FLASH_StructInit_Micron = 0x1010b8dd; 316 FLASH_StructInit_MXIC = 0x1010b98d; 317 FLASH_StructInit_GD = 0x1010ba39; 318 FLASH_StructInit = 0x1010baed; 319 FLASH_Init = 0x1010bba1; 320 GDMA_StructInit = 0x1010bc25; 321 GDMA_SetLLP = 0x1010bc45; 322 GDMA_ClearINTPendingBit = 0x1010bcd9; 323 GDMA_ClearINT = 0x1010bda5; 324 GDMA_INTConfig = 0x1010be75; 325 GDMA_Cmd = 0x1010bf91; 326 GDMA_Init = 0x1010bff9; 327 GDMA_ChCleanAutoReload = 0x1010c14d; 328 GDMA_SetSrcAddr = 0x1010c1d1; 329 GDMA_GetSrcAddr = 0x1010c221; 330 GDMA_GetDstAddr = 0x1010c26d; 331 GDMA_SetDstAddr = 0x1010c2b9; 332 GDMA_SetBlkSize = 0x1010c309; 333 GDMA_GetBlkSize = 0x1010c369; 334 GDMA_ChnlRegister = 0x1010c3b9; 335 GDMA_ChnlUnRegister = 0x1010c401; 336 GDMA_ChnlAlloc = 0x1010c43d; 337 GDMA_ChnlFree = 0x1010c4d9; 338 GDMA_GetIrqNum = 0x1010c565; 339 GPIO_INTMode = 0x1010c5a9; 340 GPIO_INTConfig = 0x1010c641; 341 GPIO_INTHandler = 0x1010c679; 342 GPIO_Direction = 0x1010c721; 343 GPIO_Init = 0x1010c755; 344 GPIO_DeInit = 0x1010c7e1; 345 GPIO_ReadDataBit = 0x1010c84d; 346 GPIO_WriteBit = 0x1010c871; 347 GPIO_PortDirection = 0x1010c8a1; 348 GPIO_PortRead = 0x1010c8c5; 349 GPIO_PortWrite = 0x1010c8d5; 350 GPIO_UserRegIrq = 0x1010c8ed; 351 IPC_INTConfig = 0x1010c925; 352 IPC_IERSet = 0x1010c939; 353 IPC_IERGet = 0x1010c93d; 354 IPC_INTRequest = 0x1010c941; 355 IPC_INTClear = 0x1010c94d; 356 IPC_INTGet = 0x1010c959; 357 IPC_CPUID = 0x1010c95d; 358 IPC_SEMGet = 0x1010c969; 359 IPC_SEMFree = 0x1010c9b9; 360 IPC_INTHandler = 0x1010ca21; 361 IPC_INTUserHandler = 0x1010ca61; 362 LOGUART_StructInit = 0x1010ca9d; 363 LOGUART_Init = 0x1010cab5; 364 LOGUART_PutChar = 0x1010caf5; 365 LOGUART_GetChar = 0x1010cb29; 366 LOGUART_Readable = 0x1010cb45; 367 LOGUART_GetIMR = 0x1010cb59; 368 LOGUART_SetIMR = 0x1010cb65; 369 LOGUART_WaitBusy = 0x1010cb71; 370 LOGUART_SetBaud = 0x1010cb91; 371 mpu_enable = 0x1010cbd5; 372 mpu_disable = 0x1010cbed; 373 mpu_init = 0x1010cc01; 374 mpu_set_mem_attr = 0x1010cc3d; 375 mpu_region_cfg = 0x1010ccb1; 376 mpu_entry_free = 0x1010cdb5; 377 mpu_entry_alloc = 0x1010cdc1; 378 RSIP_Cmd = 0x1010cde9; 379 RSIP_OTF_init = 0x1010ce05; 380 RSIP_OTF_Cmd = 0x1010ce6d; 381 RSIP_OTF_Mask = 0x1010ce81; 382 RSIP_KEY_Request = 0x1010cec9; 383 RSIP_MMU_Config = 0x1010cf0d; 384 RSIP_MMU_Cmd = 0x1010cf31; 385 PAD_DrvStrength = 0x1010cf51; 386 PAD_PullCtrl = 0x1010cf6d; 387 PAD_CMD = 0x1010cf99; 388 Pinmux_Config = 0x1010cfb9; 389 Pinmux_ConfigGet = 0x1010cfd9; 390 Pinmux_UartLogCtrl = 0x1010cfe9; 391 Pinmux_SpicCtrl = 0x1010d03d; 392 simulation_bit_index = 0x1010d181; 393 simulation_stage_set = 0x1010d199; 394 SYSTIMER_Init = 0x1010d1c5; 395 SYSTIMER_TickGet = 0x1010d215; 396 SYSTIMER_GetPassTime = 0x1010d225; 397 RTIM_TimeBaseStructInit = 0x1010d255; 398 RTIM_Cmd = 0x1010d26d; 399 RTIM_GetCount = 0x1010d2f5; 400 RTIM_INTConfig = 0x1010d361; 401 RTIM_INTClear = 0x1010d3f1; 402 RTIM_TimeBaseInit = 0x1010d45d; 403 RTIM_DeInit = 0x1010d595; 404 RTIM_INTClearPendingBit = 0x1010d611; 405 RTIM_GetFlagStatus = 0x1010d685; 406 RTIM_GetINTStatus = 0x1010d75d; 407 UART_DeInit = 0x1010d83d; 408 UART_StructInit = 0x1010d845; 409 UART_BaudParaGetFull = 0x1010d861; 410 UART_BaudParaGet = 0x1010d899; 411 UART_SetBaud = 0x1010d8bd; 412 UART_SetBaudExt = 0x1010d955; 413 UART_SetRxLevel = 0x1010d9cd; 414 UART_RxCmd = 0x1010d9f5; 415 UART_Writable = 0x1010da09; 416 UART_Readable = 0x1010da11; 417 UART_CharPut = 0x1010da19; 418 UART_CharGet = 0x1010da1d; 419 UART_ReceiveData = 0x1010da25; 420 UART_SendData = 0x1010da4d; 421 UART_ReceiveDataTO = 0x1010da75; 422 UART_SendDataTO = 0x1010dab5; 423 UART_RxByteCntClear = 0x1010daf5; 424 UART_RxByteCntGet = 0x1010db01; 425 UART_BreakCtl = 0x1010db09; 426 UART_ClearRxFifo = 0x1010db1d; 427 UART_Init = 0x1010db3d; 428 UART_ClearTxFifo = 0x1010dbe5; 429 UART_INTConfig = 0x1010dbf1; 430 UART_IntStatus = 0x1010dc01; 431 UART_ModemStatusGet = 0x1010dc05; 432 UART_LineStatusGet = 0x1010dc09; 433 UART_WaitBusy = 0x1010dc0d; 434 BOOT_ROM_SignatureCheck = 0x1010e1a9; 435 BOOT_ROM_FromFlash = 0x1010e281; 436 BOOT_ROM_InitDebugFlg = 0x1010e38d; 437 BOOT_ROM_ResetVsr = 0x1010e3a9; 438 EXT32K_Cmd = 0x1010e4c9; 439 XTAL_ClkGet = 0x1010e4e9; 440 CPU_ClkSet = 0x1010e501; 441 CPU_ClkGet = 0x1010e515; 442 clear_ns_rom_bss = 0x10110021; 443 RCC_PeriphClockCmd = 0x10110039; 444 RCC_PeriphClockSource_RTC = 0x101100d1; 445 RCC_PeriphClockSource_I2C = 0x1011011d; 446 RCC_PeriphClockSource_QDEC = 0x1011013d; 447 RCC_PeriphClockSource_UART = 0x1011015d; 448 SYSCFG_GetChipInfo = 0x101101d1; 449 INT_HardFault = 0x101101dd; 450 INT_MemManage = 0x101101fd; 451 INT_BusFault = 0x1011021d; 452 INT_UsageFault = 0x1011023d; 453 INT_SecureFault = 0x1011025d; 454 INT_HardFault_C = 0x1011027d; 455 INT_NMI = 0x1011064d; 456 irq_table_init = 0x10110795; 457 irq_enable = 0x101109d1; 458 irq_disable = 0x101109ed; 459 irq_set_priority = 0x10110a11; 460 irq_get_priority = 0x10110a3d; 461 irq_set_pending = 0x10110a65; 462 irq_get_pending = 0x10110a81; 463 irq_clear_pending = 0x10110aa5; 464 irq_register = 0x10110ac1; 465 irq_unregister = 0x10110b0d; 466 _char2num = 0x10110b2d; 467 _2char2dec = 0x10110b5d; 468 _2char2hex = 0x10110bd1; 469 _memchr = 0x10110c39; 470 _memcmp = 0x10110cc9; 471 _memcpy = 0x10110d2d; 472 _memmove = 0x10110dd9; 473 _memset = 0x10110ea1; 474 _vsscanf = 0x10110ffd; 475 _sscanf = 0x101115c1; 476 _stratoi = 0x101115e1; 477 _strcat = 0x10111635; 478 _strchr = 0x10111675; 479 _strcmp = 0x10111745; 480 _strcpy = 0x101117b9; 481 _stricmp = 0x10111805; 482 _strlen = 0x10111839; 483 _strncat = 0x1011189d; 484 _strncmp = 0x101118f9; 485 _strncpy = 0x1011199d; 486 _strnlen = 0x10111a05; 487 _strpbrk = 0x10111a39; 488 _strsep = 0x10111a65; 489 _strstr = 0x10111d25; 490 _strtoull = 0x10111f3d; 491 _strtoll = 0x10111ffd; 492 _strtok = 0x1011201d; 493 _strtok_r = 0x1011208d; 494 _strtol = 0x101121b1; 495 _strtoul = 0x101122e9; 496 _strupr = 0x101122ed; 497 CRYPTO_chacha_20 = 0x10112309; 498 rom_ed25519_gen_keypair = 0x101125c5; 499 rom_ed25519_gen_signature = 0x101125c9; 500 rom_ed25519_verify_signature = 0x101125df; 501 rom_ed25519_ge_double_scalarmult_vartime = 0x10113e89; 502 rom_ed25519_ge_frombytes_negate_vartime = 0x10114195; 503 rom_ed25519_ge_p3_tobytes = 0x10114695; 504 rom_ed25519_ge_scalarmult_base = 0x101146df; 505 rom_ed25519_ge_tobytes = 0x10114807; 506 rom_ed25519_crypto_sign_seed_keypair = 0x10114851; 507 rom_ed25519_crypto_sign_verify_detached = 0x101148a9; 508 rom_ed25519_sc_muladd = 0x10114ad5; 509 rom_ed25519_sc_reduce = 0x1011b265; 510 rom_ed25519_crypto_sign_detached = 0x1011c6dd; 511 CRYPTO_poly1305_init = 0x1011ca99; 512 CRYPTO_poly1305_update = 0x1011cb31; 513 CRYPTO_poly1305_finish = 0x1011cba7; 514 rom_sha512_starts = 0x1011cd4d; 515 rom_sha512_update = 0x1011cd51; 516 rom_sha512_finish = 0x1011cd55; 517 rom_sha512 = 0x1011cd59; 518 rom_sha512_hmac_starts = 0x1011cd5d; 519 rom_sha512_hmac_update = 0x1011cdf1; 520 rom_sha512_hmac_finish = 0x1011cdf5; 521 rom_sha512_hmac_reset = 0x1011ce49; 522 rom_sha512_hmac = 0x1011ce65; 523 rom_sha512_hkdf = 0x1011cea1; 524 curve25519_donna = 0x1011dce5; 525 __rom_entry_ns_start__ = 0x101c0000; 526 rom_sec_call_ns_entry = 0x101c0000; 527 __rom_entry_ns_end__ = 0x101c0008; 528 SPIC_CALIB_PATTERN = 0x101c0008; 529 PORT_AB = 0x101c0024; 530 armBitRevIndexTable1024 = 0x101c004c; 531 twiddleCoef_1024 = 0x101c0e5c; 532 __rom_bss_end_s__ = 0x200f9000; 533} 534