1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Macros for accessing system registers with older binutils.
4  *
5  * Copyright (C) 2014 ARM Ltd.
6  * Author: Catalin Marinas <catalin.marinas@arm.com>
7  */
8 
9 #ifndef __ASM_SYSREG_H
10 #define __ASM_SYSREG_H
11 
12 #include <linux/bits.h>
13 #include <linux/stringify.h>
14 #include <linux/kasan-tags.h>
15 
16 #include <asm/gpr-num.h>
17 
18 /*
19  * ARMv8 ARM reserves the following encoding for system registers:
20  * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
21  *  C5.2, version:ARM DDI 0487A.f)
22  *	[20-19] : Op0
23  *	[18-16] : Op1
24  *	[15-12] : CRn
25  *	[11-8]  : CRm
26  *	[7-5]   : Op2
27  */
28 #define Op0_shift	19
29 #define Op0_mask	0x3
30 #define Op1_shift	16
31 #define Op1_mask	0x7
32 #define CRn_shift	12
33 #define CRn_mask	0xf
34 #define CRm_shift	8
35 #define CRm_mask	0xf
36 #define Op2_shift	5
37 #define Op2_mask	0x7
38 
39 #define sys_reg(op0, op1, crn, crm, op2) \
40 	(((op0) << Op0_shift) | ((op1) << Op1_shift) | \
41 	 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
42 	 ((op2) << Op2_shift))
43 
44 #define sys_insn	sys_reg
45 
46 #define sys_reg_Op0(id)	(((id) >> Op0_shift) & Op0_mask)
47 #define sys_reg_Op1(id)	(((id) >> Op1_shift) & Op1_mask)
48 #define sys_reg_CRn(id)	(((id) >> CRn_shift) & CRn_mask)
49 #define sys_reg_CRm(id)	(((id) >> CRm_shift) & CRm_mask)
50 #define sys_reg_Op2(id)	(((id) >> Op2_shift) & Op2_mask)
51 
52 #ifndef CONFIG_BROKEN_GAS_INST
53 
54 #ifdef __ASSEMBLY__
55 // The space separator is omitted so that __emit_inst(x) can be parsed as
56 // either an assembler directive or an assembler macro argument.
57 #define __emit_inst(x)			.inst(x)
58 #else
59 #define __emit_inst(x)			".inst " __stringify((x)) "\n\t"
60 #endif
61 
62 #else  /* CONFIG_BROKEN_GAS_INST */
63 
64 #ifndef CONFIG_CPU_BIG_ENDIAN
65 #define __INSTR_BSWAP(x)		(x)
66 #else  /* CONFIG_CPU_BIG_ENDIAN */
67 #define __INSTR_BSWAP(x)		((((x) << 24) & 0xff000000)	| \
68 					 (((x) <<  8) & 0x00ff0000)	| \
69 					 (((x) >>  8) & 0x0000ff00)	| \
70 					 (((x) >> 24) & 0x000000ff))
71 #endif	/* CONFIG_CPU_BIG_ENDIAN */
72 
73 #ifdef __ASSEMBLY__
74 #define __emit_inst(x)			.long __INSTR_BSWAP(x)
75 #else  /* __ASSEMBLY__ */
76 #define __emit_inst(x)			".long " __stringify(__INSTR_BSWAP(x)) "\n\t"
77 #endif	/* __ASSEMBLY__ */
78 
79 #endif	/* CONFIG_BROKEN_GAS_INST */
80 
81 /*
82  * Instructions for modifying PSTATE fields.
83  * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
84  * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions
85  * for accessing PSTATE fields have the following encoding:
86  *	Op0 = 0, CRn = 4
87  *	Op1, Op2 encodes the PSTATE field modified and defines the constraints.
88  *	CRm = Imm4 for the instruction.
89  *	Rt = 0x1f
90  */
91 #define pstate_field(op1, op2)		((op1) << Op1_shift | (op2) << Op2_shift)
92 #define PSTATE_Imm_shift		CRm_shift
93 #define SET_PSTATE(x, r)		__emit_inst(0xd500401f | PSTATE_ ## r | ((!!x) << PSTATE_Imm_shift))
94 
95 #define PSTATE_PAN			pstate_field(0, 4)
96 #define PSTATE_UAO			pstate_field(0, 3)
97 #define PSTATE_SSBS			pstate_field(3, 1)
98 #define PSTATE_DIT			pstate_field(3, 2)
99 #define PSTATE_TCO			pstate_field(3, 4)
100 
101 #define SET_PSTATE_PAN(x)		SET_PSTATE((x), PAN)
102 #define SET_PSTATE_UAO(x)		SET_PSTATE((x), UAO)
103 #define SET_PSTATE_SSBS(x)		SET_PSTATE((x), SSBS)
104 #define SET_PSTATE_DIT(x)		SET_PSTATE((x), DIT)
105 #define SET_PSTATE_TCO(x)		SET_PSTATE((x), TCO)
106 
107 #define set_pstate_pan(x)		asm volatile(SET_PSTATE_PAN(x))
108 #define set_pstate_uao(x)		asm volatile(SET_PSTATE_UAO(x))
109 #define set_pstate_ssbs(x)		asm volatile(SET_PSTATE_SSBS(x))
110 #define set_pstate_dit(x)		asm volatile(SET_PSTATE_DIT(x))
111 
112 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \
113 	__emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
114 
115 #define SB_BARRIER_INSN			__SYS_BARRIER_INSN(0, 7, 31)
116 
117 #define SYS_DC_ISW			sys_insn(1, 0, 7, 6, 2)
118 #define SYS_DC_CSW			sys_insn(1, 0, 7, 10, 2)
119 #define SYS_DC_CISW			sys_insn(1, 0, 7, 14, 2)
120 
121 /*
122  * Automatically generated definitions for system registers, the
123  * manual encodings below are in the process of being converted to
124  * come from here. The header relies on the definition of sys_reg()
125  * earlier in this file.
126  */
127 #include "asm/sysreg-defs.h"
128 
129 /*
130  * System registers, organised loosely by encoding but grouped together
131  * where the architected name contains an index. e.g. ID_MMFR<n>_EL1.
132  */
133 #define SYS_SVCR_SMSTOP_SM_EL0		sys_reg(0, 3, 4, 2, 3)
134 #define SYS_SVCR_SMSTART_SM_EL0		sys_reg(0, 3, 4, 3, 3)
135 #define SYS_SVCR_SMSTOP_SMZA_EL0	sys_reg(0, 3, 4, 6, 3)
136 
137 #define SYS_OSDTRRX_EL1			sys_reg(2, 0, 0, 0, 2)
138 #define SYS_MDCCINT_EL1			sys_reg(2, 0, 0, 2, 0)
139 #define SYS_MDSCR_EL1			sys_reg(2, 0, 0, 2, 2)
140 #define SYS_OSDTRTX_EL1			sys_reg(2, 0, 0, 3, 2)
141 #define SYS_OSECCR_EL1			sys_reg(2, 0, 0, 6, 2)
142 #define SYS_DBGBVRn_EL1(n)		sys_reg(2, 0, 0, n, 4)
143 #define SYS_DBGBCRn_EL1(n)		sys_reg(2, 0, 0, n, 5)
144 #define SYS_DBGWVRn_EL1(n)		sys_reg(2, 0, 0, n, 6)
145 #define SYS_DBGWCRn_EL1(n)		sys_reg(2, 0, 0, n, 7)
146 #define SYS_MDRAR_EL1			sys_reg(2, 0, 1, 0, 0)
147 
148 #define SYS_OSLAR_EL1			sys_reg(2, 0, 1, 0, 4)
149 #define SYS_OSLAR_OSLK			BIT(0)
150 
151 #define SYS_OSLSR_EL1			sys_reg(2, 0, 1, 1, 4)
152 #define SYS_OSLSR_OSLM_MASK		(BIT(3) | BIT(0))
153 #define SYS_OSLSR_OSLM_NI		0
154 #define SYS_OSLSR_OSLM_IMPLEMENTED	BIT(3)
155 #define SYS_OSLSR_OSLK			BIT(1)
156 
157 #define SYS_OSDLR_EL1			sys_reg(2, 0, 1, 3, 4)
158 #define SYS_DBGPRCR_EL1			sys_reg(2, 0, 1, 4, 4)
159 #define SYS_DBGCLAIMSET_EL1		sys_reg(2, 0, 7, 8, 6)
160 #define SYS_DBGCLAIMCLR_EL1		sys_reg(2, 0, 7, 9, 6)
161 #define SYS_DBGAUTHSTATUS_EL1		sys_reg(2, 0, 7, 14, 6)
162 #define SYS_MDCCSR_EL0			sys_reg(2, 3, 0, 1, 0)
163 #define SYS_DBGDTR_EL0			sys_reg(2, 3, 0, 4, 0)
164 #define SYS_DBGDTRRX_EL0		sys_reg(2, 3, 0, 5, 0)
165 #define SYS_DBGDTRTX_EL0		sys_reg(2, 3, 0, 5, 0)
166 #define SYS_DBGVCR32_EL2		sys_reg(2, 4, 0, 7, 0)
167 
168 #define SYS_MIDR_EL1			sys_reg(3, 0, 0, 0, 0)
169 #define SYS_MPIDR_EL1			sys_reg(3, 0, 0, 0, 5)
170 #define SYS_REVIDR_EL1			sys_reg(3, 0, 0, 0, 6)
171 
172 #define SYS_ACTLR_EL1			sys_reg(3, 0, 1, 0, 1)
173 #define SYS_RGSR_EL1			sys_reg(3, 0, 1, 0, 5)
174 #define SYS_GCR_EL1			sys_reg(3, 0, 1, 0, 6)
175 
176 #define SYS_TRFCR_EL1			sys_reg(3, 0, 1, 2, 1)
177 
178 #define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)
179 
180 #define SYS_APIAKEYLO_EL1		sys_reg(3, 0, 2, 1, 0)
181 #define SYS_APIAKEYHI_EL1		sys_reg(3, 0, 2, 1, 1)
182 #define SYS_APIBKEYLO_EL1		sys_reg(3, 0, 2, 1, 2)
183 #define SYS_APIBKEYHI_EL1		sys_reg(3, 0, 2, 1, 3)
184 
185 #define SYS_APDAKEYLO_EL1		sys_reg(3, 0, 2, 2, 0)
186 #define SYS_APDAKEYHI_EL1		sys_reg(3, 0, 2, 2, 1)
187 #define SYS_APDBKEYLO_EL1		sys_reg(3, 0, 2, 2, 2)
188 #define SYS_APDBKEYHI_EL1		sys_reg(3, 0, 2, 2, 3)
189 
190 #define SYS_APGAKEYLO_EL1		sys_reg(3, 0, 2, 3, 0)
191 #define SYS_APGAKEYHI_EL1		sys_reg(3, 0, 2, 3, 1)
192 
193 #define SYS_SPSR_EL1			sys_reg(3, 0, 4, 0, 0)
194 #define SYS_ELR_EL1			sys_reg(3, 0, 4, 0, 1)
195 
196 #define SYS_ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)
197 
198 #define SYS_AFSR0_EL1			sys_reg(3, 0, 5, 1, 0)
199 #define SYS_AFSR1_EL1			sys_reg(3, 0, 5, 1, 1)
200 #define SYS_ESR_EL1			sys_reg(3, 0, 5, 2, 0)
201 
202 #define SYS_ERRIDR_EL1			sys_reg(3, 0, 5, 3, 0)
203 #define SYS_ERRSELR_EL1			sys_reg(3, 0, 5, 3, 1)
204 #define SYS_ERXFR_EL1			sys_reg(3, 0, 5, 4, 0)
205 #define SYS_ERXCTLR_EL1			sys_reg(3, 0, 5, 4, 1)
206 #define SYS_ERXSTATUS_EL1		sys_reg(3, 0, 5, 4, 2)
207 #define SYS_ERXADDR_EL1			sys_reg(3, 0, 5, 4, 3)
208 #define SYS_ERXMISC0_EL1		sys_reg(3, 0, 5, 5, 0)
209 #define SYS_ERXMISC1_EL1		sys_reg(3, 0, 5, 5, 1)
210 #define SYS_TFSR_EL1			sys_reg(3, 0, 5, 6, 0)
211 #define SYS_TFSRE0_EL1			sys_reg(3, 0, 5, 6, 1)
212 
213 #define SYS_PAR_EL1			sys_reg(3, 0, 7, 4, 0)
214 
215 #define SYS_PAR_EL1_F			BIT(0)
216 #define SYS_PAR_EL1_FST			GENMASK(6, 1)
217 
218 /*** Statistical Profiling Extension ***/
219 #define PMSEVFR_EL1_RES0_IMP	\
220 	(GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\
221 	 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
222 #define PMSEVFR_EL1_RES0_V1P1	\
223 	(PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11)))
224 #define PMSEVFR_EL1_RES0_V1P2	\
225 	(PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6))
226 
227 /* Buffer error reporting */
228 #define PMBSR_EL1_FAULT_FSC_SHIFT	PMBSR_EL1_MSS_SHIFT
229 #define PMBSR_EL1_FAULT_FSC_MASK	PMBSR_EL1_MSS_MASK
230 
231 #define PMBSR_EL1_BUF_BSC_SHIFT		PMBSR_EL1_MSS_SHIFT
232 #define PMBSR_EL1_BUF_BSC_MASK		PMBSR_EL1_MSS_MASK
233 
234 #define PMBSR_EL1_BUF_BSC_FULL		0x1UL
235 
236 /*** End of Statistical Profiling Extension ***/
237 
238 /*
239  * TRBE Registers
240  */
241 #define SYS_TRBLIMITR_EL1		sys_reg(3, 0, 9, 11, 0)
242 #define SYS_TRBPTR_EL1			sys_reg(3, 0, 9, 11, 1)
243 #define SYS_TRBBASER_EL1		sys_reg(3, 0, 9, 11, 2)
244 #define SYS_TRBSR_EL1			sys_reg(3, 0, 9, 11, 3)
245 #define SYS_TRBMAR_EL1			sys_reg(3, 0, 9, 11, 4)
246 #define SYS_TRBTRG_EL1			sys_reg(3, 0, 9, 11, 6)
247 #define SYS_TRBIDR_EL1			sys_reg(3, 0, 9, 11, 7)
248 
249 #define TRBLIMITR_LIMIT_MASK		GENMASK_ULL(51, 0)
250 #define TRBLIMITR_LIMIT_SHIFT		12
251 #define TRBLIMITR_NVM			BIT(5)
252 #define TRBLIMITR_TRIG_MODE_MASK	GENMASK(1, 0)
253 #define TRBLIMITR_TRIG_MODE_SHIFT	3
254 #define TRBLIMITR_FILL_MODE_MASK	GENMASK(1, 0)
255 #define TRBLIMITR_FILL_MODE_SHIFT	1
256 #define TRBLIMITR_ENABLE		BIT(0)
257 #define TRBPTR_PTR_MASK			GENMASK_ULL(63, 0)
258 #define TRBPTR_PTR_SHIFT		0
259 #define TRBBASER_BASE_MASK		GENMASK_ULL(51, 0)
260 #define TRBBASER_BASE_SHIFT		12
261 #define TRBSR_EC_MASK			GENMASK(5, 0)
262 #define TRBSR_EC_SHIFT			26
263 #define TRBSR_IRQ			BIT(22)
264 #define TRBSR_TRG			BIT(21)
265 #define TRBSR_WRAP			BIT(20)
266 #define TRBSR_ABORT			BIT(18)
267 #define TRBSR_STOP			BIT(17)
268 #define TRBSR_MSS_MASK			GENMASK(15, 0)
269 #define TRBSR_MSS_SHIFT			0
270 #define TRBSR_BSC_MASK			GENMASK(5, 0)
271 #define TRBSR_BSC_SHIFT			0
272 #define TRBSR_FSC_MASK			GENMASK(5, 0)
273 #define TRBSR_FSC_SHIFT			0
274 #define TRBMAR_SHARE_MASK		GENMASK(1, 0)
275 #define TRBMAR_SHARE_SHIFT		8
276 #define TRBMAR_OUTER_MASK		GENMASK(3, 0)
277 #define TRBMAR_OUTER_SHIFT		4
278 #define TRBMAR_INNER_MASK		GENMASK(3, 0)
279 #define TRBMAR_INNER_SHIFT		0
280 #define TRBTRG_TRG_MASK			GENMASK(31, 0)
281 #define TRBTRG_TRG_SHIFT		0
282 #define TRBIDR_FLAG			BIT(5)
283 #define TRBIDR_PROG			BIT(4)
284 #define TRBIDR_ALIGN_MASK		GENMASK(3, 0)
285 #define TRBIDR_ALIGN_SHIFT		0
286 
287 #define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)
288 #define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)
289 
290 #define SYS_PMMIR_EL1			sys_reg(3, 0, 9, 14, 6)
291 
292 #define SYS_MAIR_EL1			sys_reg(3, 0, 10, 2, 0)
293 #define SYS_AMAIR_EL1			sys_reg(3, 0, 10, 3, 0)
294 
295 #define SYS_VBAR_EL1			sys_reg(3, 0, 12, 0, 0)
296 #define SYS_DISR_EL1			sys_reg(3, 0, 12, 1, 1)
297 
298 #define SYS_ICC_IAR0_EL1		sys_reg(3, 0, 12, 8, 0)
299 #define SYS_ICC_EOIR0_EL1		sys_reg(3, 0, 12, 8, 1)
300 #define SYS_ICC_HPPIR0_EL1		sys_reg(3, 0, 12, 8, 2)
301 #define SYS_ICC_BPR0_EL1		sys_reg(3, 0, 12, 8, 3)
302 #define SYS_ICC_AP0Rn_EL1(n)		sys_reg(3, 0, 12, 8, 4 | n)
303 #define SYS_ICC_AP0R0_EL1		SYS_ICC_AP0Rn_EL1(0)
304 #define SYS_ICC_AP0R1_EL1		SYS_ICC_AP0Rn_EL1(1)
305 #define SYS_ICC_AP0R2_EL1		SYS_ICC_AP0Rn_EL1(2)
306 #define SYS_ICC_AP0R3_EL1		SYS_ICC_AP0Rn_EL1(3)
307 #define SYS_ICC_AP1Rn_EL1(n)		sys_reg(3, 0, 12, 9, n)
308 #define SYS_ICC_AP1R0_EL1		SYS_ICC_AP1Rn_EL1(0)
309 #define SYS_ICC_AP1R1_EL1		SYS_ICC_AP1Rn_EL1(1)
310 #define SYS_ICC_AP1R2_EL1		SYS_ICC_AP1Rn_EL1(2)
311 #define SYS_ICC_AP1R3_EL1		SYS_ICC_AP1Rn_EL1(3)
312 #define SYS_ICC_DIR_EL1			sys_reg(3, 0, 12, 11, 1)
313 #define SYS_ICC_RPR_EL1			sys_reg(3, 0, 12, 11, 3)
314 #define SYS_ICC_SGI1R_EL1		sys_reg(3, 0, 12, 11, 5)
315 #define SYS_ICC_ASGI1R_EL1		sys_reg(3, 0, 12, 11, 6)
316 #define SYS_ICC_SGI0R_EL1		sys_reg(3, 0, 12, 11, 7)
317 #define SYS_ICC_IAR1_EL1		sys_reg(3, 0, 12, 12, 0)
318 #define SYS_ICC_EOIR1_EL1		sys_reg(3, 0, 12, 12, 1)
319 #define SYS_ICC_HPPIR1_EL1		sys_reg(3, 0, 12, 12, 2)
320 #define SYS_ICC_BPR1_EL1		sys_reg(3, 0, 12, 12, 3)
321 #define SYS_ICC_CTLR_EL1		sys_reg(3, 0, 12, 12, 4)
322 #define SYS_ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)
323 #define SYS_ICC_IGRPEN0_EL1		sys_reg(3, 0, 12, 12, 6)
324 #define SYS_ICC_IGRPEN1_EL1		sys_reg(3, 0, 12, 12, 7)
325 
326 #define SYS_CNTKCTL_EL1			sys_reg(3, 0, 14, 1, 0)
327 
328 #define SYS_AIDR_EL1			sys_reg(3, 1, 0, 0, 7)
329 
330 #define SYS_RNDR_EL0			sys_reg(3, 3, 2, 4, 0)
331 #define SYS_RNDRRS_EL0			sys_reg(3, 3, 2, 4, 1)
332 
333 #define SYS_PMCR_EL0			sys_reg(3, 3, 9, 12, 0)
334 #define SYS_PMCNTENSET_EL0		sys_reg(3, 3, 9, 12, 1)
335 #define SYS_PMCNTENCLR_EL0		sys_reg(3, 3, 9, 12, 2)
336 #define SYS_PMOVSCLR_EL0		sys_reg(3, 3, 9, 12, 3)
337 #define SYS_PMSWINC_EL0			sys_reg(3, 3, 9, 12, 4)
338 #define SYS_PMSELR_EL0			sys_reg(3, 3, 9, 12, 5)
339 #define SYS_PMCEID0_EL0			sys_reg(3, 3, 9, 12, 6)
340 #define SYS_PMCEID1_EL0			sys_reg(3, 3, 9, 12, 7)
341 #define SYS_PMCCNTR_EL0			sys_reg(3, 3, 9, 13, 0)
342 #define SYS_PMXEVTYPER_EL0		sys_reg(3, 3, 9, 13, 1)
343 #define SYS_PMXEVCNTR_EL0		sys_reg(3, 3, 9, 13, 2)
344 #define SYS_PMUSERENR_EL0		sys_reg(3, 3, 9, 14, 0)
345 #define SYS_PMOVSSET_EL0		sys_reg(3, 3, 9, 14, 3)
346 
347 #define SYS_TPIDR_EL0			sys_reg(3, 3, 13, 0, 2)
348 #define SYS_TPIDRRO_EL0			sys_reg(3, 3, 13, 0, 3)
349 #define SYS_TPIDR2_EL0			sys_reg(3, 3, 13, 0, 5)
350 
351 #define SYS_SCXTNUM_EL0			sys_reg(3, 3, 13, 0, 7)
352 
353 /* Definitions for system register interface to AMU for ARMv8.4 onwards */
354 #define SYS_AM_EL0(crm, op2)		sys_reg(3, 3, 13, (crm), (op2))
355 #define SYS_AMCR_EL0			SYS_AM_EL0(2, 0)
356 #define SYS_AMCFGR_EL0			SYS_AM_EL0(2, 1)
357 #define SYS_AMCGCR_EL0			SYS_AM_EL0(2, 2)
358 #define SYS_AMUSERENR_EL0		SYS_AM_EL0(2, 3)
359 #define SYS_AMCNTENCLR0_EL0		SYS_AM_EL0(2, 4)
360 #define SYS_AMCNTENSET0_EL0		SYS_AM_EL0(2, 5)
361 #define SYS_AMCNTENCLR1_EL0		SYS_AM_EL0(3, 0)
362 #define SYS_AMCNTENSET1_EL0		SYS_AM_EL0(3, 1)
363 
364 /*
365  * Group 0 of activity monitors (architected):
366  *                op0  op1  CRn   CRm       op2
367  * Counter:       11   011  1101  010:n<3>  n<2:0>
368  * Type:          11   011  1101  011:n<3>  n<2:0>
369  * n: 0-15
370  *
371  * Group 1 of activity monitors (auxiliary):
372  *                op0  op1  CRn   CRm       op2
373  * Counter:       11   011  1101  110:n<3>  n<2:0>
374  * Type:          11   011  1101  111:n<3>  n<2:0>
375  * n: 0-15
376  */
377 
378 #define SYS_AMEVCNTR0_EL0(n)		SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
379 #define SYS_AMEVTYPER0_EL0(n)		SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
380 #define SYS_AMEVCNTR1_EL0(n)		SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
381 #define SYS_AMEVTYPER1_EL0(n)		SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
382 
383 /* AMU v1: Fixed (architecturally defined) activity monitors */
384 #define SYS_AMEVCNTR0_CORE_EL0		SYS_AMEVCNTR0_EL0(0)
385 #define SYS_AMEVCNTR0_CONST_EL0		SYS_AMEVCNTR0_EL0(1)
386 #define SYS_AMEVCNTR0_INST_RET_EL0	SYS_AMEVCNTR0_EL0(2)
387 #define SYS_AMEVCNTR0_MEM_STALL		SYS_AMEVCNTR0_EL0(3)
388 
389 #define SYS_CNTFRQ_EL0			sys_reg(3, 3, 14, 0, 0)
390 
391 #define SYS_CNTPCTSS_EL0		sys_reg(3, 3, 14, 0, 5)
392 #define SYS_CNTVCTSS_EL0		sys_reg(3, 3, 14, 0, 6)
393 
394 #define SYS_CNTP_TVAL_EL0		sys_reg(3, 3, 14, 2, 0)
395 #define SYS_CNTP_CTL_EL0		sys_reg(3, 3, 14, 2, 1)
396 #define SYS_CNTP_CVAL_EL0		sys_reg(3, 3, 14, 2, 2)
397 
398 #define SYS_CNTV_CTL_EL0		sys_reg(3, 3, 14, 3, 1)
399 #define SYS_CNTV_CVAL_EL0		sys_reg(3, 3, 14, 3, 2)
400 
401 #define SYS_AARCH32_CNTP_TVAL		sys_reg(0, 0, 14, 2, 0)
402 #define SYS_AARCH32_CNTP_CTL		sys_reg(0, 0, 14, 2, 1)
403 #define SYS_AARCH32_CNTP_CVAL		sys_reg(0, 2, 0, 14, 0)
404 
405 #define __PMEV_op2(n)			((n) & 0x7)
406 #define __CNTR_CRm(n)			(0x8 | (((n) >> 3) & 0x3))
407 #define SYS_PMEVCNTRn_EL0(n)		sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
408 #define __TYPER_CRm(n)			(0xc | (((n) >> 3) & 0x3))
409 #define SYS_PMEVTYPERn_EL0(n)		sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
410 
411 #define SYS_PMCCFILTR_EL0		sys_reg(3, 3, 14, 15, 7)
412 
413 #define SYS_VPIDR_EL2			sys_reg(3, 4, 0, 0, 0)
414 #define SYS_VMPIDR_EL2			sys_reg(3, 4, 0, 0, 5)
415 
416 #define SYS_SCTLR_EL2			sys_reg(3, 4, 1, 0, 0)
417 #define SYS_ACTLR_EL2			sys_reg(3, 4, 1, 0, 1)
418 #define SYS_HCR_EL2			sys_reg(3, 4, 1, 1, 0)
419 #define SYS_MDCR_EL2			sys_reg(3, 4, 1, 1, 1)
420 #define SYS_CPTR_EL2			sys_reg(3, 4, 1, 1, 2)
421 #define SYS_HSTR_EL2			sys_reg(3, 4, 1, 1, 3)
422 #define SYS_HFGRTR_EL2			sys_reg(3, 4, 1, 1, 4)
423 #define SYS_HFGWTR_EL2			sys_reg(3, 4, 1, 1, 5)
424 #define SYS_HFGITR_EL2			sys_reg(3, 4, 1, 1, 6)
425 #define SYS_HACR_EL2			sys_reg(3, 4, 1, 1, 7)
426 
427 #define SYS_TTBR0_EL2			sys_reg(3, 4, 2, 0, 0)
428 #define SYS_TTBR1_EL2			sys_reg(3, 4, 2, 0, 1)
429 #define SYS_TCR_EL2			sys_reg(3, 4, 2, 0, 2)
430 #define SYS_VTTBR_EL2			sys_reg(3, 4, 2, 1, 0)
431 #define SYS_VTCR_EL2			sys_reg(3, 4, 2, 1, 2)
432 
433 #define SYS_TRFCR_EL2			sys_reg(3, 4, 1, 2, 1)
434 #define SYS_HDFGRTR_EL2			sys_reg(3, 4, 3, 1, 4)
435 #define SYS_HDFGWTR_EL2			sys_reg(3, 4, 3, 1, 5)
436 #define SYS_HAFGRTR_EL2			sys_reg(3, 4, 3, 1, 6)
437 #define SYS_SPSR_EL2			sys_reg(3, 4, 4, 0, 0)
438 #define SYS_ELR_EL2			sys_reg(3, 4, 4, 0, 1)
439 #define SYS_SP_EL1			sys_reg(3, 4, 4, 1, 0)
440 #define SYS_IFSR32_EL2			sys_reg(3, 4, 5, 0, 1)
441 #define SYS_AFSR0_EL2			sys_reg(3, 4, 5, 1, 0)
442 #define SYS_AFSR1_EL2			sys_reg(3, 4, 5, 1, 1)
443 #define SYS_ESR_EL2			sys_reg(3, 4, 5, 2, 0)
444 #define SYS_VSESR_EL2			sys_reg(3, 4, 5, 2, 3)
445 #define SYS_FPEXC32_EL2			sys_reg(3, 4, 5, 3, 0)
446 #define SYS_TFSR_EL2			sys_reg(3, 4, 5, 6, 0)
447 
448 #define SYS_FAR_EL2			sys_reg(3, 4, 6, 0, 0)
449 #define SYS_HPFAR_EL2			sys_reg(3, 4, 6, 0, 4)
450 
451 #define SYS_MAIR_EL2			sys_reg(3, 4, 10, 2, 0)
452 #define SYS_AMAIR_EL2			sys_reg(3, 4, 10, 3, 0)
453 
454 #define SYS_VBAR_EL2			sys_reg(3, 4, 12, 0, 0)
455 #define SYS_RVBAR_EL2			sys_reg(3, 4, 12, 0, 1)
456 #define SYS_RMR_EL2			sys_reg(3, 4, 12, 0, 2)
457 #define SYS_VDISR_EL2			sys_reg(3, 4, 12, 1, 1)
458 #define __SYS__AP0Rx_EL2(x)		sys_reg(3, 4, 12, 8, x)
459 #define SYS_ICH_AP0R0_EL2		__SYS__AP0Rx_EL2(0)
460 #define SYS_ICH_AP0R1_EL2		__SYS__AP0Rx_EL2(1)
461 #define SYS_ICH_AP0R2_EL2		__SYS__AP0Rx_EL2(2)
462 #define SYS_ICH_AP0R3_EL2		__SYS__AP0Rx_EL2(3)
463 
464 #define __SYS__AP1Rx_EL2(x)		sys_reg(3, 4, 12, 9, x)
465 #define SYS_ICH_AP1R0_EL2		__SYS__AP1Rx_EL2(0)
466 #define SYS_ICH_AP1R1_EL2		__SYS__AP1Rx_EL2(1)
467 #define SYS_ICH_AP1R2_EL2		__SYS__AP1Rx_EL2(2)
468 #define SYS_ICH_AP1R3_EL2		__SYS__AP1Rx_EL2(3)
469 
470 #define SYS_ICH_VSEIR_EL2		sys_reg(3, 4, 12, 9, 4)
471 #define SYS_ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)
472 #define SYS_ICH_HCR_EL2			sys_reg(3, 4, 12, 11, 0)
473 #define SYS_ICH_VTR_EL2			sys_reg(3, 4, 12, 11, 1)
474 #define SYS_ICH_MISR_EL2		sys_reg(3, 4, 12, 11, 2)
475 #define SYS_ICH_EISR_EL2		sys_reg(3, 4, 12, 11, 3)
476 #define SYS_ICH_ELRSR_EL2		sys_reg(3, 4, 12, 11, 5)
477 #define SYS_ICH_VMCR_EL2		sys_reg(3, 4, 12, 11, 7)
478 
479 #define __SYS__LR0_EL2(x)		sys_reg(3, 4, 12, 12, x)
480 #define SYS_ICH_LR0_EL2			__SYS__LR0_EL2(0)
481 #define SYS_ICH_LR1_EL2			__SYS__LR0_EL2(1)
482 #define SYS_ICH_LR2_EL2			__SYS__LR0_EL2(2)
483 #define SYS_ICH_LR3_EL2			__SYS__LR0_EL2(3)
484 #define SYS_ICH_LR4_EL2			__SYS__LR0_EL2(4)
485 #define SYS_ICH_LR5_EL2			__SYS__LR0_EL2(5)
486 #define SYS_ICH_LR6_EL2			__SYS__LR0_EL2(6)
487 #define SYS_ICH_LR7_EL2			__SYS__LR0_EL2(7)
488 
489 #define __SYS__LR8_EL2(x)		sys_reg(3, 4, 12, 13, x)
490 #define SYS_ICH_LR8_EL2			__SYS__LR8_EL2(0)
491 #define SYS_ICH_LR9_EL2			__SYS__LR8_EL2(1)
492 #define SYS_ICH_LR10_EL2		__SYS__LR8_EL2(2)
493 #define SYS_ICH_LR11_EL2		__SYS__LR8_EL2(3)
494 #define SYS_ICH_LR12_EL2		__SYS__LR8_EL2(4)
495 #define SYS_ICH_LR13_EL2		__SYS__LR8_EL2(5)
496 #define SYS_ICH_LR14_EL2		__SYS__LR8_EL2(6)
497 #define SYS_ICH_LR15_EL2		__SYS__LR8_EL2(7)
498 
499 #define SYS_CONTEXTIDR_EL2		sys_reg(3, 4, 13, 0, 1)
500 #define SYS_TPIDR_EL2			sys_reg(3, 4, 13, 0, 2)
501 
502 #define SYS_CNTVOFF_EL2			sys_reg(3, 4, 14, 0, 3)
503 #define SYS_CNTHCTL_EL2			sys_reg(3, 4, 14, 1, 0)
504 
505 /* VHE encodings for architectural EL0/1 system registers */
506 #define SYS_SCTLR_EL12			sys_reg(3, 5, 1, 0, 0)
507 #define SYS_TTBR0_EL12			sys_reg(3, 5, 2, 0, 0)
508 #define SYS_TTBR1_EL12			sys_reg(3, 5, 2, 0, 1)
509 #define SYS_TCR_EL12			sys_reg(3, 5, 2, 0, 2)
510 #define SYS_SPSR_EL12			sys_reg(3, 5, 4, 0, 0)
511 #define SYS_ELR_EL12			sys_reg(3, 5, 4, 0, 1)
512 #define SYS_AFSR0_EL12			sys_reg(3, 5, 5, 1, 0)
513 #define SYS_AFSR1_EL12			sys_reg(3, 5, 5, 1, 1)
514 #define SYS_ESR_EL12			sys_reg(3, 5, 5, 2, 0)
515 #define SYS_TFSR_EL12			sys_reg(3, 5, 5, 6, 0)
516 #define SYS_MAIR_EL12			sys_reg(3, 5, 10, 2, 0)
517 #define SYS_AMAIR_EL12			sys_reg(3, 5, 10, 3, 0)
518 #define SYS_VBAR_EL12			sys_reg(3, 5, 12, 0, 0)
519 #define SYS_CNTKCTL_EL12		sys_reg(3, 5, 14, 1, 0)
520 #define SYS_CNTP_TVAL_EL02		sys_reg(3, 5, 14, 2, 0)
521 #define SYS_CNTP_CTL_EL02		sys_reg(3, 5, 14, 2, 1)
522 #define SYS_CNTP_CVAL_EL02		sys_reg(3, 5, 14, 2, 2)
523 #define SYS_CNTV_TVAL_EL02		sys_reg(3, 5, 14, 3, 0)
524 #define SYS_CNTV_CTL_EL02		sys_reg(3, 5, 14, 3, 1)
525 #define SYS_CNTV_CVAL_EL02		sys_reg(3, 5, 14, 3, 2)
526 
527 #define SYS_SP_EL2			sys_reg(3, 6,  4, 1, 0)
528 
529 /* Common SCTLR_ELx flags. */
530 #define SCTLR_ELx_ENTP2	(BIT(60))
531 #define SCTLR_ELx_DSSBS	(BIT(44))
532 #define SCTLR_ELx_ATA	(BIT(43))
533 
534 #define SCTLR_ELx_EE_SHIFT	25
535 #define SCTLR_ELx_ENIA_SHIFT	31
536 
537 #define SCTLR_ELx_ITFSB	 (BIT(37))
538 #define SCTLR_ELx_ENIA	 (BIT(SCTLR_ELx_ENIA_SHIFT))
539 #define SCTLR_ELx_ENIB	 (BIT(30))
540 #define SCTLR_ELx_LSMAOE (BIT(29))
541 #define SCTLR_ELx_nTLSMD (BIT(28))
542 #define SCTLR_ELx_ENDA	 (BIT(27))
543 #define SCTLR_ELx_EE     (BIT(SCTLR_ELx_EE_SHIFT))
544 #define SCTLR_ELx_EIS	 (BIT(22))
545 #define SCTLR_ELx_IESB	 (BIT(21))
546 #define SCTLR_ELx_TSCXT	 (BIT(20))
547 #define SCTLR_ELx_WXN	 (BIT(19))
548 #define SCTLR_ELx_ENDB	 (BIT(13))
549 #define SCTLR_ELx_I	 (BIT(12))
550 #define SCTLR_ELx_EOS	 (BIT(11))
551 #define SCTLR_ELx_SA	 (BIT(3))
552 #define SCTLR_ELx_C	 (BIT(2))
553 #define SCTLR_ELx_A	 (BIT(1))
554 #define SCTLR_ELx_M	 (BIT(0))
555 
556 /* SCTLR_EL2 specific flags. */
557 #define SCTLR_EL2_RES1	((BIT(4))  | (BIT(5))  | (BIT(11)) | (BIT(16)) | \
558 			 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
559 			 (BIT(29)))
560 
561 #ifdef CONFIG_CPU_BIG_ENDIAN
562 #define ENDIAN_SET_EL2		SCTLR_ELx_EE
563 #else
564 #define ENDIAN_SET_EL2		0
565 #endif
566 
567 #define INIT_SCTLR_EL2_MMU_ON						\
568 	(SCTLR_ELx_M  | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I |	\
569 	 SCTLR_ELx_IESB | SCTLR_ELx_WXN | ENDIAN_SET_EL2 |		\
570 	 SCTLR_ELx_ITFSB | SCTLR_EL2_RES1)
571 
572 #define INIT_SCTLR_EL2_MMU_OFF \
573 	(SCTLR_EL2_RES1 | ENDIAN_SET_EL2)
574 
575 /* SCTLR_EL1 specific flags. */
576 #ifdef CONFIG_CPU_BIG_ENDIAN
577 #define ENDIAN_SET_EL1		(SCTLR_EL1_E0E | SCTLR_ELx_EE)
578 #else
579 #define ENDIAN_SET_EL1		0
580 #endif
581 
582 #define INIT_SCTLR_EL1_MMU_OFF \
583 	(ENDIAN_SET_EL1 | SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | \
584 	 SCTLR_EL1_EIS  | SCTLR_EL1_TSCXT  | SCTLR_EL1_EOS)
585 
586 #define INIT_SCTLR_EL1_MMU_ON \
587 	(SCTLR_ELx_M      | SCTLR_ELx_C      | SCTLR_ELx_SA    | \
588 	 SCTLR_EL1_SA0    | SCTLR_EL1_SED    | SCTLR_ELx_I     | \
589 	 SCTLR_EL1_DZE    | SCTLR_EL1_UCT    | SCTLR_EL1_nTWE  | \
590 	 SCTLR_ELx_IESB   | SCTLR_EL1_SPAN   | SCTLR_ELx_ITFSB | \
591 	 ENDIAN_SET_EL1   | SCTLR_EL1_UCI    | SCTLR_EL1_EPAN  | \
592 	 SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS   | \
593 	 SCTLR_EL1_TSCXT  | SCTLR_EL1_EOS)
594 
595 /* MAIR_ELx memory attributes (used by Linux) */
596 #define MAIR_ATTR_DEVICE_nGnRnE		UL(0x00)
597 #define MAIR_ATTR_DEVICE_nGnRE		UL(0x04)
598 #define MAIR_ATTR_NORMAL_NC		UL(0x44)
599 #define MAIR_ATTR_NORMAL_TAGGED		UL(0xf0)
600 #define MAIR_ATTR_NORMAL		UL(0xff)
601 #define MAIR_ATTR_MASK			UL(0xff)
602 
603 /* Position the attr at the correct index */
604 #define MAIR_ATTRIDX(attr, idx)		((attr) << ((idx) * 8))
605 
606 /* id_aa64pfr0 */
607 #define ID_AA64PFR0_EL1_ELx_64BIT_ONLY		0x1
608 #define ID_AA64PFR0_EL1_ELx_32BIT_64BIT		0x2
609 
610 /* id_aa64mmfr0 */
611 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN	0x0
612 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX	0x7
613 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN	0x0
614 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX	0x7
615 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN	0x1
616 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX	0xf
617 
618 #define ARM64_MIN_PARANGE_BITS		32
619 
620 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT	0x0
621 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE		0x1
622 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN		0x2
623 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX		0x7
624 
625 #ifdef CONFIG_ARM64_PA_BITS_52
626 #define ID_AA64MMFR0_EL1_PARANGE_MAX	ID_AA64MMFR0_EL1_PARANGE_52
627 #else
628 #define ID_AA64MMFR0_EL1_PARANGE_MAX	ID_AA64MMFR0_EL1_PARANGE_48
629 #endif
630 
631 #if defined(CONFIG_ARM64_4K_PAGES)
632 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN4_SHIFT
633 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
634 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX
635 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT
636 #elif defined(CONFIG_ARM64_16K_PAGES)
637 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN16_SHIFT
638 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN
639 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX
640 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT
641 #elif defined(CONFIG_ARM64_64K_PAGES)
642 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN64_SHIFT
643 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN
644 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX	ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX
645 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT
646 #endif
647 
648 #define CPACR_EL1_FPEN_EL1EN	(BIT(20)) /* enable EL1 access */
649 #define CPACR_EL1_FPEN_EL0EN	(BIT(21)) /* enable EL0 access, if EL1EN set */
650 
651 #define CPACR_EL1_SMEN_EL1EN	(BIT(24)) /* enable EL1 access */
652 #define CPACR_EL1_SMEN_EL0EN	(BIT(25)) /* enable EL0 access, if EL1EN set */
653 
654 #define CPACR_EL1_ZEN_EL1EN	(BIT(16)) /* enable EL1 access */
655 #define CPACR_EL1_ZEN_EL0EN	(BIT(17)) /* enable EL0 access, if EL1EN set */
656 
657 /* GCR_EL1 Definitions */
658 #define SYS_GCR_EL1_RRND	(BIT(16))
659 #define SYS_GCR_EL1_EXCL_MASK	0xffffUL
660 
661 #ifdef CONFIG_KASAN_HW_TAGS
662 /*
663  * KASAN always uses a whole byte for its tags. With CONFIG_KASAN_HW_TAGS it
664  * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
665  */
666 #define __MTE_TAG_MIN		(KASAN_TAG_MIN & 0xf)
667 #define __MTE_TAG_MAX		(KASAN_TAG_MAX & 0xf)
668 #define __MTE_TAG_INCL		GENMASK(__MTE_TAG_MAX, __MTE_TAG_MIN)
669 #define KERNEL_GCR_EL1_EXCL	(SYS_GCR_EL1_EXCL_MASK & ~__MTE_TAG_INCL)
670 #else
671 #define KERNEL_GCR_EL1_EXCL	SYS_GCR_EL1_EXCL_MASK
672 #endif
673 
674 #define KERNEL_GCR_EL1		(SYS_GCR_EL1_RRND | KERNEL_GCR_EL1_EXCL)
675 
676 /* RGSR_EL1 Definitions */
677 #define SYS_RGSR_EL1_TAG_MASK	0xfUL
678 #define SYS_RGSR_EL1_SEED_SHIFT	8
679 #define SYS_RGSR_EL1_SEED_MASK	0xffffUL
680 
681 /* TFSR{,E0}_EL1 bit definitions */
682 #define SYS_TFSR_EL1_TF0_SHIFT	0
683 #define SYS_TFSR_EL1_TF1_SHIFT	1
684 #define SYS_TFSR_EL1_TF0	(UL(1) << SYS_TFSR_EL1_TF0_SHIFT)
685 #define SYS_TFSR_EL1_TF1	(UL(1) << SYS_TFSR_EL1_TF1_SHIFT)
686 
687 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
688 #define SYS_MPIDR_SAFE_VAL	(BIT(31))
689 
690 #define TRFCR_ELx_TS_SHIFT		5
691 #define TRFCR_ELx_TS_MASK		((0x3UL) << TRFCR_ELx_TS_SHIFT)
692 #define TRFCR_ELx_TS_VIRTUAL		((0x1UL) << TRFCR_ELx_TS_SHIFT)
693 #define TRFCR_ELx_TS_GUEST_PHYSICAL	((0x2UL) << TRFCR_ELx_TS_SHIFT)
694 #define TRFCR_ELx_TS_PHYSICAL		((0x3UL) << TRFCR_ELx_TS_SHIFT)
695 #define TRFCR_EL2_CX			BIT(3)
696 #define TRFCR_ELx_ExTRE			BIT(1)
697 #define TRFCR_ELx_E0TRE			BIT(0)
698 
699 /* GIC Hypervisor interface registers */
700 /* ICH_MISR_EL2 bit definitions */
701 #define ICH_MISR_EOI		(1 << 0)
702 #define ICH_MISR_U		(1 << 1)
703 
704 /* ICH_LR*_EL2 bit definitions */
705 #define ICH_LR_VIRTUAL_ID_MASK	((1ULL << 32) - 1)
706 
707 #define ICH_LR_EOI		(1ULL << 41)
708 #define ICH_LR_GROUP		(1ULL << 60)
709 #define ICH_LR_HW		(1ULL << 61)
710 #define ICH_LR_STATE		(3ULL << 62)
711 #define ICH_LR_PENDING_BIT	(1ULL << 62)
712 #define ICH_LR_ACTIVE_BIT	(1ULL << 63)
713 #define ICH_LR_PHYS_ID_SHIFT	32
714 #define ICH_LR_PHYS_ID_MASK	(0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
715 #define ICH_LR_PRIORITY_SHIFT	48
716 #define ICH_LR_PRIORITY_MASK	(0xffULL << ICH_LR_PRIORITY_SHIFT)
717 
718 /* ICH_HCR_EL2 bit definitions */
719 #define ICH_HCR_EN		(1 << 0)
720 #define ICH_HCR_UIE		(1 << 1)
721 #define ICH_HCR_NPIE		(1 << 3)
722 #define ICH_HCR_TC		(1 << 10)
723 #define ICH_HCR_TALL0		(1 << 11)
724 #define ICH_HCR_TALL1		(1 << 12)
725 #define ICH_HCR_TDIR		(1 << 14)
726 #define ICH_HCR_EOIcount_SHIFT	27
727 #define ICH_HCR_EOIcount_MASK	(0x1f << ICH_HCR_EOIcount_SHIFT)
728 
729 /* ICH_VMCR_EL2 bit definitions */
730 #define ICH_VMCR_ACK_CTL_SHIFT	2
731 #define ICH_VMCR_ACK_CTL_MASK	(1 << ICH_VMCR_ACK_CTL_SHIFT)
732 #define ICH_VMCR_FIQ_EN_SHIFT	3
733 #define ICH_VMCR_FIQ_EN_MASK	(1 << ICH_VMCR_FIQ_EN_SHIFT)
734 #define ICH_VMCR_CBPR_SHIFT	4
735 #define ICH_VMCR_CBPR_MASK	(1 << ICH_VMCR_CBPR_SHIFT)
736 #define ICH_VMCR_EOIM_SHIFT	9
737 #define ICH_VMCR_EOIM_MASK	(1 << ICH_VMCR_EOIM_SHIFT)
738 #define ICH_VMCR_BPR1_SHIFT	18
739 #define ICH_VMCR_BPR1_MASK	(7 << ICH_VMCR_BPR1_SHIFT)
740 #define ICH_VMCR_BPR0_SHIFT	21
741 #define ICH_VMCR_BPR0_MASK	(7 << ICH_VMCR_BPR0_SHIFT)
742 #define ICH_VMCR_PMR_SHIFT	24
743 #define ICH_VMCR_PMR_MASK	(0xffUL << ICH_VMCR_PMR_SHIFT)
744 #define ICH_VMCR_ENG0_SHIFT	0
745 #define ICH_VMCR_ENG0_MASK	(1 << ICH_VMCR_ENG0_SHIFT)
746 #define ICH_VMCR_ENG1_SHIFT	1
747 #define ICH_VMCR_ENG1_MASK	(1 << ICH_VMCR_ENG1_SHIFT)
748 
749 /* ICH_VTR_EL2 bit definitions */
750 #define ICH_VTR_PRI_BITS_SHIFT	29
751 #define ICH_VTR_PRI_BITS_MASK	(7 << ICH_VTR_PRI_BITS_SHIFT)
752 #define ICH_VTR_ID_BITS_SHIFT	23
753 #define ICH_VTR_ID_BITS_MASK	(7 << ICH_VTR_ID_BITS_SHIFT)
754 #define ICH_VTR_SEIS_SHIFT	22
755 #define ICH_VTR_SEIS_MASK	(1 << ICH_VTR_SEIS_SHIFT)
756 #define ICH_VTR_A3V_SHIFT	21
757 #define ICH_VTR_A3V_MASK	(1 << ICH_VTR_A3V_SHIFT)
758 #define ICH_VTR_TDS_SHIFT	19
759 #define ICH_VTR_TDS_MASK	(1 << ICH_VTR_TDS_SHIFT)
760 
761 /* HFG[WR]TR_EL2 bit definitions */
762 #define HFGxTR_EL2_nTPIDR2_EL0_SHIFT	55
763 #define HFGxTR_EL2_nTPIDR2_EL0_MASK	BIT_MASK(HFGxTR_EL2_nTPIDR2_EL0_SHIFT)
764 #define HFGxTR_EL2_nSMPRI_EL1_SHIFT	54
765 #define HFGxTR_EL2_nSMPRI_EL1_MASK	BIT_MASK(HFGxTR_EL2_nSMPRI_EL1_SHIFT)
766 
767 #define ARM64_FEATURE_FIELD_BITS	4
768 
769 /* Defined for compatibility only, do not add new users. */
770 #define ARM64_FEATURE_MASK(x)	(x##_MASK)
771 
772 #ifdef __ASSEMBLY__
773 
774 	.macro	mrs_s, rt, sreg
775 	 __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt))
776 	.endm
777 
778 	.macro	msr_s, sreg, rt
779 	__emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt))
780 	.endm
781 
782 #else
783 
784 #include <linux/bitfield.h>
785 #include <linux/build_bug.h>
786 #include <linux/types.h>
787 #include <asm/alternative.h>
788 
789 #define DEFINE_MRS_S						\
790 	__DEFINE_ASM_GPR_NUMS					\
791 "	.macro	mrs_s, rt, sreg\n"				\
792 	__emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt))	\
793 "	.endm\n"
794 
795 #define DEFINE_MSR_S						\
796 	__DEFINE_ASM_GPR_NUMS					\
797 "	.macro	msr_s, sreg, rt\n"				\
798 	__emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt))	\
799 "	.endm\n"
800 
801 #define UNDEFINE_MRS_S						\
802 "	.purgem	mrs_s\n"
803 
804 #define UNDEFINE_MSR_S						\
805 "	.purgem	msr_s\n"
806 
807 #define __mrs_s(v, r)						\
808 	DEFINE_MRS_S						\
809 "	mrs_s " v ", " __stringify(r) "\n"			\
810 	UNDEFINE_MRS_S
811 
812 #define __msr_s(r, v)						\
813 	DEFINE_MSR_S						\
814 "	msr_s " __stringify(r) ", " v "\n"			\
815 	UNDEFINE_MSR_S
816 
817 /*
818  * Unlike read_cpuid, calls to read_sysreg are never expected to be
819  * optimized away or replaced with synthetic values.
820  */
821 #define read_sysreg(r) ({					\
822 	u64 __val;						\
823 	asm volatile("mrs %0, " __stringify(r) : "=r" (__val));	\
824 	__val;							\
825 })
826 
827 /*
828  * The "Z" constraint normally means a zero immediate, but when combined with
829  * the "%x0" template means XZR.
830  */
831 #define write_sysreg(v, r) do {					\
832 	u64 __val = (u64)(v);					\
833 	asm volatile("msr " __stringify(r) ", %x0"		\
834 		     : : "rZ" (__val));				\
835 } while (0)
836 
837 /*
838  * For registers without architectural names, or simply unsupported by
839  * GAS.
840  */
841 #define read_sysreg_s(r) ({						\
842 	u64 __val;							\
843 	asm volatile(__mrs_s("%0", r) : "=r" (__val));			\
844 	__val;								\
845 })
846 
847 #define write_sysreg_s(v, r) do {					\
848 	u64 __val = (u64)(v);						\
849 	asm volatile(__msr_s(r, "%x0") : : "rZ" (__val));		\
850 } while (0)
851 
852 /*
853  * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the
854  * set mask are set. Other bits are left as-is.
855  */
856 #define sysreg_clear_set(sysreg, clear, set) do {			\
857 	u64 __scs_val = read_sysreg(sysreg);				\
858 	u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set);		\
859 	if (__scs_new != __scs_val)					\
860 		write_sysreg(__scs_new, sysreg);			\
861 } while (0)
862 
863 #define sysreg_clear_set_s(sysreg, clear, set) do {			\
864 	u64 __scs_val = read_sysreg_s(sysreg);				\
865 	u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set);		\
866 	if (__scs_new != __scs_val)					\
867 		write_sysreg_s(__scs_new, sysreg);			\
868 } while (0)
869 
870 #define read_sysreg_par() ({						\
871 	u64 par;							\
872 	asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));	\
873 	par = read_sysreg(par_el1);					\
874 	asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));	\
875 	par;								\
876 })
877 
878 #define SYS_FIELD_GET(reg, field, val)		\
879 		 FIELD_GET(reg##_##field##_MASK, val)
880 
881 #define SYS_FIELD_PREP(reg, field, val)		\
882 		 FIELD_PREP(reg##_##field##_MASK, val)
883 
884 #define SYS_FIELD_PREP_ENUM(reg, field, val)		\
885 		 FIELD_PREP(reg##_##field##_MASK, reg##_##field##_##val)
886 
887 #endif
888 
889 #endif	/* __ASM_SYSREG_H */
890