1 /*
2 * Copyright © 2006-2019 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #ifndef _INTEL_DISPLAY_H_
26 #define _INTEL_DISPLAY_H_
27
28 #include <drm/drm_util.h>
29
30 #include "i915_reg_defs.h"
31 #include "intel_display_limits.h"
32
33 enum drm_scaling_filter;
34 struct dpll;
35 struct drm_connector;
36 struct drm_device;
37 struct drm_display_mode;
38 struct drm_encoder;
39 struct drm_file;
40 struct drm_format_info;
41 struct drm_framebuffer;
42 struct drm_i915_gem_object;
43 struct drm_i915_private;
44 struct drm_mode_fb_cmd2;
45 struct drm_modeset_acquire_ctx;
46 struct drm_plane;
47 struct drm_plane_state;
48 struct i915_address_space;
49 struct i915_gtt_view;
50 struct intel_atomic_state;
51 struct intel_crtc;
52 struct intel_crtc_state;
53 struct intel_digital_port;
54 struct intel_dp;
55 struct intel_encoder;
56 struct intel_initial_plane_config;
57 struct intel_link_m_n;
58 struct intel_load_detect_pipe;
59 struct intel_plane;
60 struct intel_plane_state;
61 struct intel_power_domain_mask;
62 struct intel_remapped_info;
63 struct intel_rotation_info;
64 struct pci_dev;
65
66
67 #define pipe_name(p) ((p) + 'A')
68
transcoder_name(enum transcoder transcoder)69 static inline const char *transcoder_name(enum transcoder transcoder)
70 {
71 switch (transcoder) {
72 case TRANSCODER_A:
73 return "A";
74 case TRANSCODER_B:
75 return "B";
76 case TRANSCODER_C:
77 return "C";
78 case TRANSCODER_D:
79 return "D";
80 case TRANSCODER_EDP:
81 return "EDP";
82 case TRANSCODER_DSI_A:
83 return "DSI A";
84 case TRANSCODER_DSI_C:
85 return "DSI C";
86 default:
87 return "<invalid>";
88 }
89 }
90
transcoder_is_dsi(enum transcoder transcoder)91 static inline bool transcoder_is_dsi(enum transcoder transcoder)
92 {
93 return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
94 }
95
96 /*
97 * Global legacy plane identifier. Valid only for primary/sprite
98 * planes on pre-g4x, and only for primary planes on g4x-bdw.
99 */
100 enum i9xx_plane_id {
101 PLANE_A,
102 PLANE_B,
103 PLANE_C,
104 };
105
106 #define plane_name(p) ((p) + 'A')
107 #define sprite_name(p, s) ((p) * RUNTIME_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
108
109 #define for_each_plane_id_on_crtc(__crtc, __p) \
110 for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
111 for_each_if((__crtc)->plane_ids_mask & BIT(__p))
112
113 #define for_each_dbuf_slice(__dev_priv, __slice) \
114 for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
115 for_each_if(INTEL_INFO(__dev_priv)->display.dbuf.slice_mask & BIT(__slice))
116
117 #define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
118 for_each_dbuf_slice((__dev_priv), (__slice)) \
119 for_each_if((__mask) & BIT(__slice))
120
121 #define port_name(p) ((p) + 'A')
122
123 /*
124 * Ports identifier referenced from other drivers.
125 * Expected to remain stable over time
126 */
port_identifier(enum port port)127 static inline const char *port_identifier(enum port port)
128 {
129 switch (port) {
130 case PORT_A:
131 return "Port A";
132 case PORT_B:
133 return "Port B";
134 case PORT_C:
135 return "Port C";
136 case PORT_D:
137 return "Port D";
138 case PORT_E:
139 return "Port E";
140 case PORT_F:
141 return "Port F";
142 case PORT_G:
143 return "Port G";
144 case PORT_H:
145 return "Port H";
146 case PORT_I:
147 return "Port I";
148 default:
149 return "<invalid>";
150 }
151 }
152
153 enum tc_port {
154 TC_PORT_NONE = -1,
155
156 TC_PORT_1 = 0,
157 TC_PORT_2,
158 TC_PORT_3,
159 TC_PORT_4,
160 TC_PORT_5,
161 TC_PORT_6,
162
163 I915_MAX_TC_PORTS
164 };
165
166 enum tc_port_mode {
167 TC_PORT_DISCONNECTED,
168 TC_PORT_TBT_ALT,
169 TC_PORT_DP_ALT,
170 TC_PORT_LEGACY,
171 };
172
173 enum aux_ch {
174 AUX_CH_A,
175 AUX_CH_B,
176 AUX_CH_C,
177 AUX_CH_D,
178 AUX_CH_E, /* ICL+ */
179 AUX_CH_F,
180 AUX_CH_G,
181 AUX_CH_H,
182 AUX_CH_I,
183
184 /* tgl+ */
185 AUX_CH_USBC1 = AUX_CH_D,
186 AUX_CH_USBC2,
187 AUX_CH_USBC3,
188 AUX_CH_USBC4,
189 AUX_CH_USBC5,
190 AUX_CH_USBC6,
191
192 /* XE_LPD repositions D/E offsets and bitfields */
193 AUX_CH_D_XELPD = AUX_CH_USBC5,
194 AUX_CH_E_XELPD,
195 };
196
197 #define aux_ch_name(a) ((a) + 'A')
198
199 enum phy {
200 PHY_NONE = -1,
201
202 PHY_A = 0,
203 PHY_B,
204 PHY_C,
205 PHY_D,
206 PHY_E,
207 PHY_F,
208 PHY_G,
209 PHY_H,
210 PHY_I,
211
212 I915_MAX_PHYS
213 };
214
215 #define phy_name(a) ((a) + 'A')
216
217 enum phy_fia {
218 FIA1,
219 FIA2,
220 FIA3,
221 };
222
223 #define for_each_hpd_pin(__pin) \
224 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
225
226 #define for_each_pipe(__dev_priv, __p) \
227 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
228 for_each_if(RUNTIME_INFO(__dev_priv)->pipe_mask & BIT(__p))
229
230 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
231 for_each_pipe(__dev_priv, __p) \
232 for_each_if((__mask) & BIT(__p))
233
234 #define for_each_cpu_transcoder(__dev_priv, __t) \
235 for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++) \
236 for_each_if (RUNTIME_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
237
238 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
239 for_each_cpu_transcoder(__dev_priv, __t) \
240 for_each_if ((__mask) & BIT(__t))
241
242 #define for_each_sprite(__dev_priv, __p, __s) \
243 for ((__s) = 0; \
244 (__s) < RUNTIME_INFO(__dev_priv)->num_sprites[(__p)]; \
245 (__s)++)
246
247 #define for_each_port(__port) \
248 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
249
250 #define for_each_port_masked(__port, __ports_mask) \
251 for_each_port(__port) \
252 for_each_if((__ports_mask) & BIT(__port))
253
254 #define for_each_phy_masked(__phy, __phys_mask) \
255 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
256 for_each_if((__phys_mask) & BIT(__phy))
257
258 #define for_each_crtc(dev, crtc) \
259 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
260
261 #define for_each_intel_plane(dev, intel_plane) \
262 list_for_each_entry(intel_plane, \
263 &(dev)->mode_config.plane_list, \
264 base.head)
265
266 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
267 list_for_each_entry(intel_plane, \
268 &(dev)->mode_config.plane_list, \
269 base.head) \
270 for_each_if((plane_mask) & \
271 drm_plane_mask(&intel_plane->base))
272
273 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
274 list_for_each_entry(intel_plane, \
275 &(dev)->mode_config.plane_list, \
276 base.head) \
277 for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
278
279 #define for_each_intel_crtc(dev, intel_crtc) \
280 list_for_each_entry(intel_crtc, \
281 &(dev)->mode_config.crtc_list, \
282 base.head)
283
284 #define for_each_intel_crtc_in_pipe_mask(dev, intel_crtc, pipe_mask) \
285 list_for_each_entry(intel_crtc, \
286 &(dev)->mode_config.crtc_list, \
287 base.head) \
288 for_each_if((pipe_mask) & BIT(intel_crtc->pipe))
289
290 #define for_each_intel_encoder(dev, intel_encoder) \
291 list_for_each_entry(intel_encoder, \
292 &(dev)->mode_config.encoder_list, \
293 base.head)
294
295 #define for_each_intel_encoder_mask(dev, intel_encoder, encoder_mask) \
296 list_for_each_entry(intel_encoder, \
297 &(dev)->mode_config.encoder_list, \
298 base.head) \
299 for_each_if((encoder_mask) & \
300 drm_encoder_mask(&intel_encoder->base))
301
302 #define for_each_intel_encoder_mask_with_psr(dev, intel_encoder, encoder_mask) \
303 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
304 for_each_if(((encoder_mask) & drm_encoder_mask(&(intel_encoder)->base)) && \
305 intel_encoder_can_psr(intel_encoder))
306
307 #define for_each_intel_dp(dev, intel_encoder) \
308 for_each_intel_encoder(dev, intel_encoder) \
309 for_each_if(intel_encoder_is_dp(intel_encoder))
310
311 #define for_each_intel_encoder_with_psr(dev, intel_encoder) \
312 for_each_intel_encoder((dev), (intel_encoder)) \
313 for_each_if(intel_encoder_can_psr(intel_encoder))
314
315 #define for_each_intel_connector_iter(intel_connector, iter) \
316 while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
317
318 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
319 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
320 for_each_if((intel_encoder)->base.crtc == (__crtc))
321
322 #define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \
323 for ((__i) = 0; \
324 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
325 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
326 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), 1); \
327 (__i)++) \
328 for_each_if(plane)
329
330 #define for_each_old_intel_crtc_in_state(__state, crtc, old_crtc_state, __i) \
331 for ((__i) = 0; \
332 (__i) < (__state)->base.dev->mode_config.num_crtc && \
333 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
334 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), 1); \
335 (__i)++) \
336 for_each_if(crtc)
337
338 #define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
339 for ((__i) = 0; \
340 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
341 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
342 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
343 (__i)++) \
344 for_each_if(plane)
345
346 #define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
347 for ((__i) = 0; \
348 (__i) < (__state)->base.dev->mode_config.num_crtc && \
349 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
350 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
351 (__i)++) \
352 for_each_if(crtc)
353
354 #define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
355 for ((__i) = 0; \
356 (__i) < (__state)->base.dev->mode_config.num_total_plane && \
357 ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
358 (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
359 (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
360 (__i)++) \
361 for_each_if(plane)
362
363 #define for_each_oldnew_intel_crtc_in_state(__state, crtc, old_crtc_state, new_crtc_state, __i) \
364 for ((__i) = 0; \
365 (__i) < (__state)->base.dev->mode_config.num_crtc && \
366 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
367 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
368 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
369 (__i)++) \
370 for_each_if(crtc)
371
372 #define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
373 for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
374 (__i) >= 0 && \
375 ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
376 (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
377 (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
378 (__i)--) \
379 for_each_if(crtc)
380
381 #define intel_atomic_crtc_state_for_each_plane_state( \
382 plane, plane_state, \
383 crtc_state) \
384 for_each_intel_plane_mask(((crtc_state)->uapi.state->dev), (plane), \
385 ((crtc_state)->uapi.plane_mask)) \
386 for_each_if ((plane_state = \
387 to_intel_plane_state(__drm_atomic_get_current_plane_state((crtc_state)->uapi.state, &plane->base))))
388
389 #define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
390 for ((__i) = 0; \
391 (__i) < (__state)->base.num_connector; \
392 (__i)++) \
393 for_each_if ((__state)->base.connectors[__i].ptr && \
394 ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
395 (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
396
397 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
398 struct intel_crtc *crtc);
399 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
400 u8 active_pipes);
401 void intel_link_compute_m_n(u16 bpp, int nlanes,
402 int pixel_clock, int link_clock,
403 struct intel_link_m_n *m_n,
404 bool fec_enable);
405 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
406 u32 pixel_format, u64 modifier);
407 enum drm_mode_status
408 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
409 const struct drm_display_mode *mode,
410 bool bigjoiner);
411 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
412 bool is_trans_port_sync_mode(const struct intel_crtc_state *state);
413 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state);
414 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state);
415 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state);
416 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state);
417 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
418 bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
419 const struct intel_crtc_state *pipe_config,
420 bool fastset);
421 void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state);
422
423 void intel_plane_destroy(struct drm_plane *plane);
424 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
425 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
426 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
427 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state);
428 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
429 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
430 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
431 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
432 const char *name, u32 reg, int ref_freq);
433 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
434 const char *name, u32 reg);
435 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
436 unsigned int intel_fb_xy_to_linear(int x, int y,
437 const struct intel_plane_state *state,
438 int plane);
439 void intel_add_fb_offsets(int *x, int *y,
440 const struct intel_plane_state *state, int plane);
441 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
442 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
443 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
444 int intel_display_suspend(struct drm_device *dev);
445 void intel_encoder_destroy(struct drm_encoder *encoder);
446 struct drm_display_mode *
447 intel_encoder_current_mode(struct intel_encoder *encoder);
448 void intel_encoder_get_config(struct intel_encoder *encoder,
449 struct intel_crtc_state *crtc_state);
450 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
451 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
452 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy);
453 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
454 enum port port);
455 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
456 struct drm_file *file_priv);
457
458 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
459 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
460 struct intel_digital_port *dig_port,
461 unsigned int expected_mask);
462 int intel_get_load_detect_pipe(struct drm_connector *connector,
463 struct intel_load_detect_pipe *old,
464 struct drm_modeset_acquire_ctx *ctx);
465 void intel_release_load_detect_pipe(struct drm_connector *connector,
466 struct intel_load_detect_pipe *old,
467 struct drm_modeset_acquire_ctx *ctx);
468 struct drm_framebuffer *
469 intel_framebuffer_create(struct drm_i915_gem_object *obj,
470 struct drm_mode_fb_cmd2 *mode_cmd);
471
472 bool intel_fuzzy_clock_check(int clock1, int clock2);
473
474 void intel_display_prepare_reset(struct drm_i915_private *dev_priv);
475 void intel_display_finish_reset(struct drm_i915_private *dev_priv);
476 void intel_zero_m_n(struct intel_link_m_n *m_n);
477 void intel_set_m_n(struct drm_i915_private *i915,
478 const struct intel_link_m_n *m_n,
479 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
480 i915_reg_t link_m_reg, i915_reg_t link_n_reg);
481 void intel_get_m_n(struct drm_i915_private *i915,
482 struct intel_link_m_n *m_n,
483 i915_reg_t data_m_reg, i915_reg_t data_n_reg,
484 i915_reg_t link_m_reg, i915_reg_t link_n_reg);
485 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
486 enum transcoder transcoder);
487 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
488 enum transcoder cpu_transcoder,
489 const struct intel_link_m_n *m_n);
490 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
491 enum transcoder cpu_transcoder,
492 const struct intel_link_m_n *m_n);
493 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
494 enum transcoder cpu_transcoder,
495 struct intel_link_m_n *m_n);
496 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
497 enum transcoder cpu_transcoder,
498 struct intel_link_m_n *m_n);
499 void i9xx_crtc_clock_get(struct intel_crtc *crtc,
500 struct intel_crtc_state *pipe_config);
501 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
502 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config);
503 enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);
504 enum intel_display_power_domain
505 intel_aux_power_domain(struct intel_digital_port *dig_port);
506 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
507 struct intel_crtc_state *crtc_state);
508 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
509
510 int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
511 unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state);
512
513 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state);
514
515 struct intel_encoder *
516 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
517 const struct intel_crtc_state *crtc_state);
518 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
519 struct intel_plane *plane);
520 void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
521 struct intel_plane_state *plane_state,
522 bool visible);
523 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state);
524
525 void intel_display_driver_register(struct drm_i915_private *i915);
526 void intel_display_driver_unregister(struct drm_i915_private *i915);
527
528 void intel_update_watermarks(struct drm_i915_private *i915);
529
530 /* modesetting */
531 bool intel_modeset_probe_defer(struct pci_dev *pdev);
532 void intel_modeset_init_hw(struct drm_i915_private *i915);
533 int intel_modeset_init_noirq(struct drm_i915_private *i915);
534 int intel_modeset_init_nogem(struct drm_i915_private *i915);
535 int intel_modeset_init(struct drm_i915_private *i915);
536 void intel_modeset_driver_remove(struct drm_i915_private *i915);
537 void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915);
538 void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915);
539 void intel_display_resume(struct drm_device *dev);
540 int intel_modeset_all_pipes(struct intel_atomic_state *state,
541 const char *reason);
542 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
543 struct intel_power_domain_mask *old_domains);
544 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
545 struct intel_power_domain_mask *domains);
546
547 /* modesetting asserts */
548 void assert_transcoder(struct drm_i915_private *dev_priv,
549 enum transcoder cpu_transcoder, bool state);
550 #define assert_transcoder_enabled(d, t) assert_transcoder(d, t, true)
551 #define assert_transcoder_disabled(d, t) assert_transcoder(d, t, false)
552
553 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
554 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
555 * which may not necessarily be a user visible problem. This will either
556 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
557 * enable distros and users to tailor their preferred amount of i915 abrt
558 * spam.
559 */
560 #define I915_STATE_WARN(condition, format...) ({ \
561 int __ret_warn_on = !!(condition); \
562 if (unlikely(__ret_warn_on)) \
563 if (!WARN(i915_modparams.verbose_state_checks, format)) \
564 DRM_ERROR(format); \
565 unlikely(__ret_warn_on); \
566 })
567
568 #define I915_STATE_WARN_ON(x) \
569 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
570
571 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915);
572
573 #endif
574