1 /** 2 ****************************************************************************** 3 * @file rtl8721d_tim.h 4 * @author 5 * @version V1.0.0 6 * @date 2016-05-17 7 * @brief This file contains all the functions prototypes for the Timer firmware 8 * library. 9 ****************************************************************************** 10 * @attention 11 * 12 * This module is a confidential and proprietary property of RealTek and 13 * possession or use of this module requires written permission of RealTek. 14 * 15 * Copyright(c) 2015, Realtek Semiconductor Corporation. All rights reserved. 16 ****************************************************************************** 17 */ 18 19 #ifndef _RTL8721D_TIMER_H_ 20 #define _RTL8721D_TIMER_H_ 21 22 /** @addtogroup AmebaD_Periph_Driver 23 * @{ 24 */ 25 26 /** @defgroup Timer 27 * @brief Timer driver modules 28 * @{ 29 */ 30 31 /** @addtogroup Timer 32 * @verbatim 33 ***************************************************************************************** 34 * Introduction 35 ***************************************************************************************** 36 * TIM0/TIM1/TIM2/TIM3: used as generic timers for time-base generation 37 * - Base Address: TIMM00/TIMM01/TIMM02/TIMM03/TIM0/TIM1/TIM2/TIM3 38 * - Clock Source: 32kHz 39 * - Resolution: 32bit 40 * - Count Mode: Upcounting 41 * - Interrupt Generation 42 * - Support Upcounting mode 43 * TIM4: 44 * - Base Address: TIMM04/TIM4 45 * - Channels: 1 46 * - Clock Source: XTAL, normally is 40MHz 47 * - Resolution: 16bit 48 * - Prescaler: 8bit 49 * - Count Mode: Upcounting 50 * - Input Pin: 1 input capture 51 * - Interrupt Generation 52 * - Support Upcounting mode/Statistic Pulse Width mode/Statistic Pulse Number mode 53 * TIM5: 54 * - Base Address: TIMM05/TIM5 55 * - Channels: 6(KM0)/18(KM4) 56 * - Clock Source: XTAL, normally is 40MHz 57 * - Resolution: 16bit 58 * - Prescaler: 8bit 59 * - Count Mode: Upcounting 60 * - Interrup Generation 61 * - Input Pin: 1 input capture 62 * - Ouput Pin: 6(KM0)/18(KM4) PWM out 63 * - Support Upcounting mode/Input capture mode/PWM mode/One Pulse mode 64 * 65 ***************************************************************************************** 66 * Sys Timer 67 ***************************************************************************************** 68 * - TIMM00 is used as systimer, so TIMM00 can not be used for other purpose 69 * 70 ***************************************************************************************** 71 * Upcounting mode 72 ***************************************************************************************** 73 * TIMM00~5/TIM0~5 support 74 * The counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), 75 * then restarts from 0 and generates a counter overflow interrupt. 76 * 77 ***************************************************************************************** 78 * Statistic Pulse Width mode 79 ***************************************************************************************** 80 * Only TIMM04/TIM4 support 81 * TIMM04/TIM4 can statistic the width of active level of TRGI. When the TRGI is transferred from 82 * inactive level to active level, the counter is enabled automatically and counter starts 83 * from 0. When the TRGI is transferred from active level to inactive level , the counter 84 * is disabled automatically, the current counter value will be copied to CCR0 field of 85 * TIMx_CCR0, the CCxIF will be set and an interrupt can be sent if they are enabled. 86 * 87 ***************************************************************************************** 88 * Statistic Pulse Number mode 89 ***************************************************************************************** 90 * Only TIMM04/TIM4 support 91 * TIM4 can statistic the number of active edge of TRGI in the given period. When the 92 * counter overflow, the number will be copied to CCR0 field of TIMx_CCR0, the CCxIF will 93 * be set and an interrupt can be sent if they are enabled 94 * 95 ***************************************************************************************** 96 * Input capture mode 97 ***************************************************************************************** 98 * Only TIMM05/TIM5 supports 99 * In input capture mode, the CCRx field of TIMx_CCRx are used to latch the value of the 100 * counter after a transition detected by the TRGI signal. When a capture occurs, the 101 * corresponding CCXIF flag (TIMx_SR register) is set and an interrupt can be sent if they are enabled. 102 * 103 ***************************************************************************************** 104 * PWM mode 105 ***************************************************************************************** 106 * Only TIMM05/TIM5 supports 107 * Pulse Width Modulation mode allows you to generate a signal with a frequency determined 108 * by the value of the TIMx_ARR register and a duty cycle determined by the value of the 109 * CCRx field of TIMx_CCRx register. 110 * Period = (ARR + 1)*Tcnt, Duty cycle = CCRx*Tcnt/Period, where Tcnt = Txtal *(PSC+1). 111 * 112 ***************************************************************************************** 113 * One Pulse mode 114 ***************************************************************************************** 115 * Only TIM5 supports 116 * This mode allows the counter to be started in response to a stimulus and to generate 117 * a pulse with a programmable length after a programmable delay. Starting the counter can 118 * be controlled through the active edge of TRGI. Generating the waveform can be done in PWM 119 * mode. You select One-pulse mode by setting the OPM bit in the TIMx_CR register. This makes 120 * the counter stop automatically at the next update event. 121 * 122 * NOTICE: you shoud pull up/down the pwm pin (PAD_PullCtrl) when you use one pulse mode based on polarity 123 * 124 ***************************************************************************************** 125 * How to use Base Timer 126 ***************************************************************************************** 127 * To use the Timer in Timing(Time base) mode, the following steps are mandatory: 128 * 129 * 1. Enable TIM clock : 130 * RCC_PeriphClockCmd(APBPeriph_GTIMER, APBPeriph_GTIMER_CLOCK, ENABLE) 131 * 132 * 2. Fill the TIM_InitStruct with default parameters using: 133 * RTIM_TimeBaseStructInit(&TIM_InitStruct) 134 * or setting the desired parameters manually. 135 * 136 * 3. Configure the Time Base unit with the corresponding configurations, register TimerIRQHandler 137 * and enable the NVIC if you need to generate the update interrupt. 138 * RTIM_TimeBaseInit(TIMx, &TIM_InitStruct, IrqNum, UserCB, UserCBData) 139 * 140 * 4. Enable the corresponding interrupt using : 141 * RTIM_INTConfig(TIMx, TIM_IT_Update, ENABLE) 142 * 143 * 5. Enable the TIM counter. 144 * RTIM_Cmd(TIMx, ENABLE) 145 * 146 * Note1: All other functions can be used separately to modify, if needed, 147 * a specific feature of the Timer. 148 * 149 ***************************************************************************************** 150 * How to use Timer in Capture Compare Mode 151 ***************************************************************************************** 152 * To use the Timer in CC mode, the following steps are mandatory: 153 * 154 * 1. Enable TIM clock : 155 * RCC_PeriphClockCmd(APBPeriph_GTIMER, APBPeriph_GTIMER_CLOCK, ENABLE) 156 * 157 * 2. Configure the TIM pinmux: 158 * Pinmux_Config(PinName, PinFunc) 159 * 160 * 3. Configure the Time base unit as described in the first part of this driver if needed, 161 * else the Timer will run with the default configuration: 162 * - Autoreload value = 0xFFFF 163 * - Prescaler value = 0x0000 164 * 165 * 4. Fill the TIM_CCInitStruct with the desired parameters including: 166 * - The TIM Output Compare mode: TIM_CCMode 167 * - TIM Output Compare Pulse value: TIM_OCMPulse 168 * - TIM Output Compare Polarity : TIM_CCPolarity 169 * - TIM Output Compare value update protection: TIM_OCProtection 170 * 171 * 5. Configure the desired channel with the corresponding configuration 172 * RTIM_CCxInit(TIMx, &TIM_CCInitStruct, TIM_Channel) 173 * 174 * 6. Enable corresponding TIM channel. 175 * RTIM_CCxCmd(TIMx, TIM_Channel, TIM_CCx_Enable) 176 * 177 * 7. Enable the TIM counter. 178 * RTIM_Cmd(TIMx, ENABLE) 179 * 180 * Note1: All other functions can be used separately to modify, if needed, 181 * a specific feature of the Timer. 182 * 183 * Note2: In case of PWM mode, the TIMx peripheral Preload register on CCRx(TIM_OCProtection) 184 * should be enabled. 185 * 186 * Note3: If the corresponding interrupt is needed, the user should: 187 * 1. Enable the NVIC to use the TIM interrupts. 188 * 2. Enable the corresponding interrupt using the function 189 * RTIM_ITConfig(TIMx, TIM_IT_CCx, ENABLE) 190 * 191 * @endverbatim 192 */ 193 194 /* Exported types ------------------------------------------------------------*/ 195 196 /** @defgroup TIM_Exported_Types TIM Exported Types 197 * @{ 198 */ 199 200 /** 201 * @brief TIM Basic Init structure definition 202 */ 203 typedef struct { 204 u32 TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 205 This parameter can be a number between 0x00 and 0xFF, basic timer dont care */ 206 u32 TIM_Period; /*!< Specifies the period value to be loaded into the active 207 Auto-Reload Register at the next update event. 208 This parameter is 16bits for TIM4-5, and 32bits for TIM0-TIM3 209 you can get it from SourceClock & TIM_Prescaler */ 210 u32 TIM_UpdateEvent; /*!< Specifies whether or not to enable update event(UEV). 211 This parameter can be ENABLE or DISABLE. ENABLE means UEV Enable, DISABLE means UEV Disable*/ 212 u32 TIM_UpdateSource; /*!< Specifies the update request source. This parameter can be 213 TIM_UpdateSource_Overflow or TIM_UpdateSource_Global. 214 TIM_UpdateSource_Overflow means counter overflow generates an update event(UEV). 215 TIM_UpdateSource_Global means both counter overflow and setting the UG bit can generate UEV.*/ 216 u32 TIM_ARRProtection; /*!< DISABLE or ENABLE, when ENABLE: period will update when cnt = 0(counter overflow, an UEV happens), 217 or period will update immediatly */ 218 219 u8 TIM_Idx; /*!< 0~5 */ 220 } RTIM_TimeBaseInitTypeDef; 221 222 /** 223 * @brief TIM Output Compare Init structure definition 224 */ 225 typedef struct 226 { 227 u32 TIM_CCMode; /*!< Specifies the TIM5 mode. This parameter can be a value of TIM_CCMode_PWM or TIM_CCMode_Inputcapture */ 228 u32 TIM_CCPolarity; /*!< Specifies the polarity. This parameter can be TIM_CCPolarity_High/TIM_CCPolarity_Low. 229 If CCx channel is configured as output: 230 TIM_CCPolarity_High means OCx active high. 231 TIM_CCPolarity_Low means OCx active low. 232 If CCx channel is configured as input: 233 TIM_CCPolarity_High means positive edge of TRGI is active for capture. 234 TIM_CCPolarity_Low means negative edge of TRGI is active for capture. */ 235 236 u32 TIM_OCProtection; /*!< Output Compare value update protection. TIM_OCPreload_Enable/TIM_OCPreload_Disable. 237 TIM_OCPreload_Enable means duty cycle will update when UEV happens if write to CCRx field in TIMx_CCRX. 238 TIM_OCPreload_Disable means duty cycle will update immediately if write to CCRx field in TIMx_CCRX.*/ 239 240 u32 TIM_OCPulse; /*!< Specifies the output pulse value to be loaded into the CCRx Register, which decides the duty cycle. 241 This parameter can be a number between 0x0000 and 0xFFFF */ 242 243 u32 TIM_ICPulseMode; /*!< Specifies the TIM4 mode, TIM_CCMode_PulseWidth or TIM_CCMode_PulseNumber */ 244 } TIM_CCInitTypeDef; 245 246 /** 247 * @} 248 */ 249 250 /* Exported constants --------------------------------------------------------*/ 251 /** @defgroup TIM_Exported_constants TIM Exported constants 252 * @{ 253 */ 254 255 /** @defgroup TIM_Type_definitions 256 * @{ 257 */ 258 #define IS_TIM_ALL_TIM(PERIPH) (((PERIPH) == TIM0) || \ 259 ((PERIPH) == TIM1) || \ 260 ((PERIPH) == TIM2) || \ 261 ((PERIPH) == TIM3) || \ 262 ((PERIPH) == TIM4) || \ 263 ((PERIPH) == TIM5) || \ 264 ((PERIPH) == TIMM00) || \ 265 ((PERIPH) == TIMM01) || \ 266 ((PERIPH) == TIMM02) || \ 267 ((PERIPH) == TIMM03) || \ 268 ((PERIPH) == TIMM04) || \ 269 ((PERIPH) == TIMM05)) 270 271 #define IS_TIM_ONE_PULSE_TIM(PERIPH) ((PERIPH) == TIM5 || (PERIPH) == TIMM05) 272 273 #define IS_TIM_CCM_TIM(PERIPH) (((PERIPH) == TIM4) || \ 274 ((PERIPH) == TIM5) || \ 275 ((PERIPH) == TIMM04) || \ 276 ((PERIPH) == TIMM05)) 277 278 #define IS_TIM_PWM_TIM(PERIPH) ((PERIPH) == TIM5 || (PERIPH) == TIMM05) 279 280 #define IS_TIM_INPULSE_TIM(PERIPH) ((PERIPH) == TIM4 || (PERIPH) == TIMM04) 281 282 #define IS_TIM_40M_TIM(PERIPH) (((PERIPH) == TIM4) || \ 283 ((PERIPH) == TIM5) || \ 284 ((PERIPH) == TIMM04) || \ 285 ((PERIPH) == TIMM05)) 286 /** 287 * @} 288 */ 289 290 /** @defgroup TIM_Channel_definitions 291 * @note TIMM0x: 0~5, TIMx: 0~17 292 * @{ 293 */ 294 #define TIM_Channel_0 ((u16)0x0000) 295 #define TIM_Channel_1 ((u16)0x0001) 296 #define TIM_Channel_2 ((u16)0x0002) 297 #define TIM_Channel_3 ((u16)0x0003) 298 #define TIM_Channel_4 ((u16)0x0004) 299 #define TIM_Channel_5 ((u16)0x0005) 300 #define TIM_Channel_6 ((u16)0x0006) 301 #define TIM_Channel_7 ((u16)0x0007) 302 #define TIM_Channel_8 ((u16)0x0008) 303 #define TIM_Channel_9 ((u16)0x0009) 304 #define TIM_Channel_10 ((u16)0x000a) 305 #define TIM_Channel_11 ((u16)0x000b) 306 #define TIM_Channel_12 ((u16)0x000c) 307 #define TIM_Channel_13 ((u16)0x000d) 308 #define TIM_Channel_14 ((u16)0x000e) 309 #define TIM_Channel_15 ((u16)0x000f) 310 #define TIM_Channel_16 ((u16)0x0010) 311 #define TIM_Channel_17 ((u16)0x0011) 312 313 #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_0) || \ 314 ((CHANNEL) == TIM_Channel_1) || \ 315 ((CHANNEL) == TIM_Channel_2) || \ 316 ((CHANNEL) == TIM_Channel_3) || \ 317 ((CHANNEL) == TIM_Channel_4) || \ 318 ((CHANNEL) == TIM_Channel_5) || \ 319 ((CHANNEL) == TIM_Channel_6) || \ 320 ((CHANNEL) == TIM_Channel_7) || \ 321 ((CHANNEL) == TIM_Channel_8) || \ 322 ((CHANNEL) == TIM_Channel_9) || \ 323 ((CHANNEL) == TIM_Channel_10) || \ 324 ((CHANNEL) == TIM_Channel_11) || \ 325 ((CHANNEL) == TIM_Channel_12) || \ 326 ((CHANNEL) == TIM_Channel_13) || \ 327 ((CHANNEL) == TIM_Channel_14) || \ 328 ((CHANNEL) == TIM_Channel_15) || \ 329 ((CHANNEL) == TIM_Channel_16) || \ 330 ((CHANNEL) == TIM_Channel_17)) 331 332 /** 333 * @} 334 */ 335 336 /** @defgroup TIMx_Prescaler_definitons 337 * @{ 338 */ 339 #define IS_TIM_PSC(VAL) (VAL <= 0xFF) 340 /** 341 * @} 342 */ 343 344 /** @defgroup TIMx_Control_Bit_definitions 345 * @{ 346 */ 347 #define TIM_OPMode_ETP_positive ((u32)0x00000000) 348 #define TIM_OPMode_ETP_negative ((u32)0x00000100) 349 #define IS_TIM_OPM_ETP_MODE(MODE) (((MODE) == TIM_OPMode_ETP_positive) || \ 350 ((MODE) == TIM_OPMode_ETP_negative)) 351 352 #define TIM_OPMode_Single ((u32)0x00000008) 353 #define TIM_OPMode_Repetitive ((u32)0x00000000) /* repeative is PWM mode */ 354 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ 355 ((MODE) == TIM_OPMode_Repetitive)) 356 357 #define TIM_UpdateSource_Global ((u32)0x00000000) /*!< Source of update is the counter overflow or the setting of UG bit. */ 358 #define TIM_UpdateSource_Overflow ((u32)0x00000004) /*!< Source of update is counter overflow. */ 359 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ 360 ((SOURCE) == TIM_UpdateSource_Overflow)) 361 /** 362 * @} 363 */ 364 365 /** @defgroup TIMx_Interrupt_Enable_definitions 366 * @{ 367 */ 368 369 #define TIM_IT_Update ((u32)0x00000001) 370 #define TIM_IT_CC0 ((u32)0x00000002) 371 #define TIM_IT_CC1 ((u32)0x00000004) 372 #define TIM_IT_CC2 ((u32)0x00000008) 373 #define TIM_IT_CC3 ((u32)0x00000010) 374 #define TIM_IT_CC4 ((u32)0x00000020) 375 #define TIM_IT_CC5 ((u32)0x00000040) 376 #define TIM_IT_CC6 ((u32)0x00000080) 377 #define TIM_IT_CC7 ((u32)0x00000100) 378 #define TIM_IT_CC8 ((u32)0x00000200) 379 #define TIM_IT_CC9 ((u32)0x00000400) 380 #define TIM_IT_CC10 ((u32)0x00000800) 381 #define TIM_IT_CC11 ((u32)0x00001000) 382 #define TIM_IT_CC12 ((u32)0x00002000) 383 #define TIM_IT_CC13 ((u32)0x00004000) 384 #define TIM_IT_CC14 ((u32)0x00008000) 385 #define TIM_IT_CC15 ((u32)0x00010000) 386 #define TIM_IT_CC16 ((u32)0x00020000) 387 #define TIM_IT_CC17 ((u32)0x00040000) 388 #define IS_TIM_IT(IT) ((((IT) & (u32)0xFFF80000) == 0x0000) && (((IT) & (u32)0x7FFFF) != 0x0000)) 389 390 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ 391 ((IT) == TIM_IT_CC0) || \ 392 ((IT) == TIM_IT_CC1) || \ 393 ((IT) == TIM_IT_CC2) || \ 394 ((IT) == TIM_IT_CC3) || \ 395 ((IT) == TIM_IT_CC4) || \ 396 ((IT) == TIM_IT_CC5) || \ 397 ((IT) == TIM_IT_CC6) || \ 398 ((IT) == TIM_IT_CC7) || \ 399 ((IT) == TIM_IT_CC8) || \ 400 ((IT) == TIM_IT_CC9) || \ 401 ((IT) == TIM_IT_CC10) || \ 402 ((IT) == TIM_IT_CC11) || \ 403 ((IT) == TIM_IT_CC12) || \ 404 ((IT) == TIM_IT_CC13) || \ 405 ((IT) == TIM_IT_CC14) || \ 406 ((IT) == TIM_IT_CC15) || \ 407 ((IT) == TIM_IT_CC16) || \ 408 ((IT) == TIM_IT_CC17)) 409 410 /** 411 * @} 412 */ 413 414 415 /** @defgroup TIMx_PSC_Reload_Mode_definitons 416 * @{ 417 */ 418 #define TIM_PSCReloadMode_Update ((u32)0x00000000) 419 #define TIM_PSCReloadMode_Immediate ((u32)0x00000001) 420 #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ 421 ((RELOAD) == TIM_PSCReloadMode_Immediate)) 422 /** 423 * @} 424 */ 425 426 427 /** @defgroup TIMx_Event_Generation_definitons 428 * @{ 429 */ 430 #define TIM_EventSource_Update ((u32)0x00000001) 431 #define TIM_EventSource_CC0 ((u32)0x00000002) 432 #define TIM_EventSource_CC1 ((u32)0x00000004) 433 #define TIM_EventSource_CC2 ((u32)0x00000008) 434 #define TIM_EventSource_CC3 ((u32)0x00000010) 435 #define TIM_EventSource_CC4 ((u32)0x00000020) 436 #define TIM_EventSource_CC5 ((u32)0x00000040) 437 #define TIM_EventSource_CC6 ((u32)0x00000080) 438 #define TIM_EventSource_CC7 ((u32)0x00000100) 439 #define TIM_EventSource_CC8 ((u32)0x00000200) 440 #define TIM_EventSource_CC9 ((u32)0x00000400) 441 #define TIM_EventSource_CC10 ((u32)0x00000800) 442 #define TIM_EventSource_CC11 ((u32)0x00001000) 443 #define TIM_EventSource_CC12 ((u32)0x00002000) 444 #define TIM_EventSource_CC13 ((u32)0x00004000) 445 #define TIM_EventSource_CC14 ((u32)0x00008000) 446 #define TIM_EventSource_CC15 ((u32)0x00010000) 447 #define TIM_EventSource_CC16 ((u32)0x00020000) 448 #define TIM_EventSource_CC17 ((u32)0x00040000) 449 #define IS_LP_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF80) == 0x0000) && \ 450 (((SOURCE) & 0x7F) != 0x0000)) 451 #define IS_HP_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFF80000) == 0x0000) && \ 452 (((SOURCE) & 0x7FFFF) != 0x0000)) 453 454 /** 455 * @} 456 */ 457 458 459 /** @defgroup TIMx_Capture_Compare_definitions 460 * @{ 461 */ 462 463 #define TIM_CCx_Enable ((u32)0x01000000) 464 #define TIM_CCx_Disable ((u32)0x00000000) 465 #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || ((CCX) == TIM_CCx_Disable)) 466 467 #define TIM_OCPreload_Enable ((u32)0x02000000) 468 #define TIM_OCPreload_Disable ((u32)0x00000000) 469 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ 470 ((STATE) == TIM_OCPreload_Disable)) 471 472 #define TIM_CCPolarity_High ((u32)0x00000000) /*!< if input is set : Positive edge of TRGI is active for capture */ 473 #define TIM_CCPolarity_Low ((u32)0x04000000) /*!< if input is set : negative edge of TRGI is active for capture */ 474 #define IS_TIM_CC_POLARITY(POLARITY) (((POLARITY) == TIM_CCPolarity_High) || \ 475 ((POLARITY) == TIM_CCPolarity_Low)) 476 477 /* TIM5 PWM or Inputcapture mode */ 478 #define TIM_CCMode_PWM ((u32)0x00000000) 479 #define TIM_CCMode_Inputcapture ((u32)0x08000000) 480 #define IS_TIM_CC_MODE(MODE) (((MODE) == TIM_CCMode_PWM) || \ 481 ((MODE) == TIM_CCMode_Inputcapture)) 482 483 /* TIM4 pulse mode */ 484 #define TIM_CCMode_PulseWidth ((u32)0x00000000) 485 #define TIM_CCMode_PulseNumber ((u32)0x10000000) 486 #define IS_TIM_CC_PULSEMODE(MODE) (((MODE) == TIM_CCMode_PulseWidth) || \ 487 ((MODE) == TIM_CCMode_PulseNumber)) 488 489 #define TIM_CCMode_CCR ((u32)0x0000FFFF) 490 #define IS_TIM_CC_PULSEWIDTH(Compare) ((Compare) <= TIM_CCMode_CCR) 491 /** 492 * @} 493 */ 494 495 /** 496 * @} 497 */ 498 499 /** @defgroup TIM_Exported_Functions TIM Exported Functions 500 * @{ 501 */ 502 503 /** @defgroup TimeBase_Management_Functions TimeBase Management Functions 504 * @{ 505 */ 506 _LONG_CALL_ void RTIM_TimeBaseStructInit(RTIM_TimeBaseInitTypeDef* TIM_InitStruct); 507 _LONG_CALL_ void RTIM_TimeBaseInit(RTIM_TypeDef* TIMx, RTIM_TimeBaseInitTypeDef* TIM_InitStruct, IRQn_Type IrqNum, IRQ_FUN UserCB, u32 UserCBData); 508 _LONG_CALL_ void RTIM_Cmd(RTIM_TypeDef* TIMx, u32 NewState); 509 _LONG_CALL_ void RTIM_DeInit(RTIM_TypeDef* TIMx); 510 _LONG_CALL_ u32 RTIM_GetCount(RTIM_TypeDef* TIMx); 511 _LONG_CALL_ void RTIM_UpdateDisableConfig(RTIM_TypeDef* TIMx, u32 NewState); 512 _LONG_CALL_ void RTIM_ARRPreloadConfig(RTIM_TypeDef* TIMx, u32 NewState); 513 _LONG_CALL_ void RTIM_UpdateRequestConfig(RTIM_TypeDef* TIMx, u32 TIM_UpdateSource); 514 _LONG_CALL_ void RTIM_PrescalerConfig(RTIM_TypeDef* TIMx, u32 Prescaler, u32 TIM_PSCReloadMode); 515 _LONG_CALL_ void RTIM_GenerateEvent(RTIM_TypeDef* TIMx, u32 TIM_EventSource); 516 _LONG_CALL_ void RTIM_ChangePeriod(RTIM_TypeDef* TIMx, u32 Autoreload); 517 _LONG_CALL_ void RTIM_ChangePeriodImmediate(RTIM_TypeDef* TIMx, u32 Autoreload); 518 _LONG_CALL_ void RTIM_Reset(RTIM_TypeDef* TIMx); 519 /** 520 * @} 521 */ 522 523 /** @defgroup Capture_Compare_Management_Functions Capture Compare Management Functions 524 * @{ 525 */ 526 _LONG_CALL_ void RTIM_CCStructInit(TIM_CCInitTypeDef* TIM_CCInitStruct); 527 _LONG_CALL_ void RTIM_CCxInit(RTIM_TypeDef* TIMx, TIM_CCInitTypeDef* TIM_CCInitStruct, u16 TIM_Channel); 528 _LONG_CALL_ void RTIM_CCRxMode(RTIM_TypeDef* TIMx, u16 TIM_Channel, u32 TIM_CCMode); 529 _LONG_CALL_ void RTIM_CCRxSet(RTIM_TypeDef* TIMx, u32 Compare, u16 TIM_Channel); 530 _LONG_CALL_ u32 RTIM_CCRxGet(RTIM_TypeDef* TIMx, u16 TIM_Channel); 531 _LONG_CALL_ void RTIM_OCxPreloadConfig(RTIM_TypeDef* TIMx, u32 TIM_OCProtection, u16 TIM_Channel); 532 _LONG_CALL_ void RTIM_CCxPolarityConfig(RTIM_TypeDef* TIMx, u32 TIM_OCPolarity, u16 TIM_Channel); 533 _LONG_CALL_ void RTIM_CCxCmd(RTIM_TypeDef* TIMx, u16 TIM_Channel, u32 TIM_CCx); 534 _LONG_CALL_ void RTIM_SetOnePulseOutputMode(RTIM_TypeDef* TIMx, u32 TIM_OPMode, u32 TrigerPolarity); 535 /** 536 * @} 537 */ 538 539 /** @defgroup Interrupt_Management_Functions Interrupt Management Functions 540 * @{ 541 */ 542 _LONG_CALL_ void RTIM_INTConfig(RTIM_TypeDef* TIMx, u32 TIM_IT, u32 NewState); 543 _LONG_CALL_ void RTIM_INTClear(RTIM_TypeDef* TIMx); 544 _LONG_CALL_ void RTIM_INTClearPendingBit(RTIM_TypeDef* TIMx, u16 TIM_IT); 545 _LONG_CALL_ u32 RTIM_GetFlagStatus(RTIM_TypeDef* TIMx, u32 TIM_FLAG); 546 _LONG_CALL_ u32 RTIM_GetINTStatus(RTIM_TypeDef* TIMx, u32 TIM_IT); 547 /** 548 * @} 549 */ 550 551 /** 552 * @} 553 */ 554 555 556 /* Registers Definitions --------------------------------------------------------*/ 557 /**************************************************************************//** 558 * @defgroup TIM_Register_Definitions TIM Register Definitions 559 * @{ 560 *****************************************************************************/ 561 562 /**************************************************************************//** 563 * @defgroup TIM_EN 564 * @{ 565 *****************************************************************************/ 566 #define TIM_CR_CNT_START ((u32)0x00000001) /*!<Counter start */ 567 #define TIM_CR_CNT_STOP ((u32)0x00000002) /*!<Counter stop */ 568 #define TIM_CR_CNT_RUN ((u32)0x00000100) /*!<Counter run status. polling bit */ 569 #define TIM_CR_CNT_STS ((u32)0x00010000) /*!<Counter working status, polling bit */ 570 /** @} */ 571 572 /**************************************************************************//** 573 * @defgroup TIM_CR 574 * @{ 575 *****************************************************************************/ 576 #define TIM_CR_UDIS ((u32)0x00000002) /*!<Update disable */ 577 #define TIM_CR_URS ((u32)0x00000004) /*!<Update request source */ 578 #define TIM_CR_OPM ((u32)0x00000008) /*!<One pulse mode */ 579 #define TIM_CR_ARPE ((u32)0x00000010) /*!<Auto-reload preload enable */ 580 #define TIM_CR_ETP ((u32)0x00000100) /*!<External trigger polarity for one pulse mode (TRGI). */ 581 /** @} */ 582 583 /**************************************************************************//** 584 * @defgroup TIM_DIER 585 * @{ 586 *****************************************************************************/ 587 /* Interrupt EN */ 588 #define TIM_DIER_UIE ((u32)0x00000001) /*!<Update interrupt enable */ 589 #define TIM_DIER_CC0IE ((u32)0x00000002) /*!<Capture/Compare 0 interrupt enable */ 590 #define TIM_DIER_CC1IE ((u32)0x00000004) /*!<Capture/Compare 1 interrupt enable */ 591 #define TIM_DIER_CC2IE ((u32)0x00000008) /*!<Capture/Compare 2 interrupt enable */ 592 #define TIM_DIER_CC3IE ((u32)0x00000010) /*!<Capture/Compare 3 interrupt enable */ 593 #define TIM_DIER_CC4IE ((u32)0x00000020) /*!<Capture/Compare 4 interrupt enable */ 594 #define TIM_DIER_CC5IE ((u32)0x00000040) /*!<Capture/Compare 5 interrupt enable */ 595 #define TIM_DIER_CC6IE ((u32)0x00000080) /*!<Capture/Compare 6 interrupt enable */ 596 #define TIM_DIER_CC7IE ((u32)0x00000100) /*!<Capture/Compare 7 interrupt enable */ 597 #define TIM_DIER_CC8IE ((u32)0x00000200) /*!<Capture/Compare 8 interrupt enable */ 598 #define TIM_DIER_CC9IE ((u32)0x00000400) /*!<Capture/Compare 9 interrupt enable */ 599 #define TIM_DIER_CC10IE ((u32)0x00000800) /*!<Capture/Compare 10 interrupt enable */ 600 #define TIM_DIER_CC11IE ((u32)0x00001000) /*!<Capture/Compare 11 interrupt enable */ 601 #define TIM_DIER_CC12IE ((u32)0x00002000) /*!<Capture/Compare 12 interrupt enable */ 602 #define TIM_DIER_CC13IE ((u32)0x00004000) /*!<Capture/Compare 13 interrupt enable */ 603 #define TIM_DIER_CC14IE ((u32)0x00008000) /*!<Capture/Compare 14 interrupt enable */ 604 #define TIM_DIER_CC15IE ((u32)0x00010000) /*!<Capture/Compare 15 interrupt enable */ 605 #define TIM_DIER_CC16IE ((u32)0x00020000) /*!<Capture/Compare 16 interrupt enable */ 606 #define TIM_DIER_CC17IE ((u32)0x00040000) /*!<Capture/Compare 17 interrupt enable */ 607 /** @} */ 608 609 /**************************************************************************//** 610 * @defgroup TIM_SR 611 * @{ 612 *****************************************************************************/ 613 #define TIM_SR_UIF ((u32)0x00000001) /*!<Update interrupt Flag */ 614 #define TIM_SR_CC0IF ((u32)0x00000002) /*!<Capture/Compare 0 interrupt Flag */ 615 #define TIM_SR_CC1IF ((u32)0x00000004) /*!<Capture/Compare 1 interrupt Flag */ 616 #define TIM_SR_CC2IF ((u32)0x00000008) /*!<Capture/Compare 2 interrupt Flag */ 617 #define TIM_SR_CC3IF ((u32)0x00000010) /*!<Capture/Compare 3 interrupt Flag */ 618 #define TIM_SR_CC4IF ((u32)0x00000020) /*!<Capture/Compare 4 interrupt Flag */ 619 #define TIM_SR_CC5IF ((u32)0x00000040) /*!<Capture/Compare 5 interrupt Flag */ 620 #define TIM_SR_CC6IF ((u32)0x00000080) /*!<Capture/Compare 6 interrupt Flag */ 621 #define TIM_SR_CC7IF ((u32)0x00000100) /*!<Capture/Compare 7 interrupt Flag */ 622 #define TIM_SR_CC8IF ((u32)0x00000200) /*!<Capture/Compare 8 interrupt Flag */ 623 #define TIM_SR_CC9IF ((u32)0x00000400) /*!<Capture/Compare 9 interrupt Flag */ 624 #define TIM_SR_CC10IF ((u32)0x00000800) /*!<Capture/Compare 10 interrupt Flag */ 625 #define TIM_SR_CC11IF ((u32)0x00001000) /*!<Capture/Compare 11 interrupt Flag */ 626 #define TIM_SR_CC12IF ((u32)0x00002000) /*!<Capture/Compare 12 interrupt Flag */ 627 #define TIM_SR_CC13IF ((u32)0x00004000) /*!<Capture/Compare 13 interrupt Flag */ 628 #define TIM_SR_CC14IF ((u32)0x00008000) /*!<Capture/Compare 14 interrupt Flag */ 629 #define TIM_SR_CC15IF ((u32)0x00010000) /*!<Capture/Compare 15 interrupt Flag */ 630 #define TIM_SR_CC16IF ((u32)0x00020000) /*!<Capture/Compare 16 interrupt Flag */ 631 #define TIM_SR_CC17IF ((u32)0x00040000) /*!<Capture/Compare 17 interrupt Flag */ 632 #define TIM_SR_UG_DONE ((u32)0x80000000) /*!<UG operation status for TIMx_EGR UG bit, polling bit */ 633 /** @} */ 634 635 /**************************************************************************//** 636 * @defgroup TIM_EGR 637 * @{ 638 *****************************************************************************/ 639 #define TIM_EGR_UG ((u32)0x00000001) /*!<Update Generation */ 640 #define TIM_EGR_CC0G ((u32)0x00000002) /*!<Capture/Compare 0 Generation */ 641 #define TIM_EGR_CC1G ((u32)0x00000004) /*!<Capture/Compare 1 Generation */ 642 #define TIM_EGR_CC2G ((u32)0x00000008) /*!<Capture/Compare 2 Generation */ 643 #define TIM_EGR_CC3G ((u32)0x00000010) /*!<Capture/Compare 3 Generation */ 644 #define TIM_EGR_CC4G ((u32)0x00000020) /*!<Capture/Compare 4 Generation */ 645 #define TIM_EGR_CC5G ((u32)0x00000040) /*!<Capture/Compare 5 Generation */ 646 #define TIM_EGR_CC6G ((u32)0x00000080) /*!<Capture/Compare 6 Generation */ 647 #define TIM_EGR_CC7G ((u32)0x00000100) /*!<Capture/Compare 7 Generation */ 648 #define TIM_EGR_CC8G ((u32)0x00000200) /*!<Capture/Compare 8 Generation */ 649 #define TIM_EGR_CC9G ((u32)0x00000400) /*!<Capture/Compare 9 Generation */ 650 #define TIM_EGR_CC10G ((u32)0x00000800) /*!<Capture/Compare 10 Generation */ 651 #define TIM_EGR_CC11G ((u32)0x00001000) /*!<Capture/Compare 11 Generation */ 652 #define TIM_EGR_CC12G ((u32)0x00002000) /*!<Capture/Compare 12 Generation */ 653 #define TIM_EGR_CC13G ((u32)0x00004000) /*!<Capture/Compare 13 Generation */ 654 #define TIM_EGR_CC14G ((u32)0x00008000) /*!<Capture/Compare 14 Generation */ 655 #define TIM_EGR_CC15G ((u32)0x00010000) /*!<Capture/Compare 15 Generation */ 656 #define TIM_EGR_CC16G ((u32)0x00020000) /*!<Capture/Compare 16 Generation */ 657 #define TIM_EGR_CC17G ((u32)0x00040000) /*!<Capture/Compare 17 Generation */ 658 /** @} */ 659 660 /**************************************************************************//** 661 * @defgroup TIM_CCMR 662 * @{ 663 *****************************************************************************/ 664 #define TIM_CCER_CCxE ((u32)0x01 << 24) /*!<Capture/Compare x input/output enable */ 665 #define TIM_OCER_CCxPE ((u32)0x02 << 24) /*!<Output Compare x Preload enable */ 666 #define TIM_CCER_CCxP ((u32)0x04 << 24) /*!<Capture/Compare x input/output Polarity */ 667 #define TIM_CCER_CCxM ((u32)0x08 << 24) /*!<CCx working mode input or output mode */ 668 #define TIM_ICER_CCxPULSE_MODE ((u32)0x10 << 24) /*!<CCx input pulse mode: width or num, just CC1 valid */ 669 /** @} */ 670 /** @} */ 671 672 /** 673 * @} 674 */ 675 676 /** 677 * @} 678 */ 679 680 typedef struct 681 { 682 u32 PWM_CHANNEL; 683 u32 KM0_CHAN_STATUS; 684 u32 KM4_CHAN_STATUS; 685 } PWMCHANCFG_TypeDef; 686 687 extern PWMCHANCFG_TypeDef pwmchannel_config[]; 688 extern int TIMx_irq[6]; 689 extern int TIMx_irq_LP[6]; 690 extern RTIM_TypeDef* TIMx[6]; 691 extern RTIM_TypeDef* TIMx_LP[6]; 692 extern u32 TIM_IT_CCx_LP[6]; 693 extern u32 TIM_IT_CCx[18]; 694 695 #define TIMER_TICK_US 31 696 #define TIMER_TICK_US_X4 (4*1000000/32000) //32k clock, 31.25us every timer_tick 697 #endif //_RTL8721D_TIMER_H_ 698 699 /******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/ 700