1 //***************************************************************************** 2 // 3 // hw_udma.h - Macros for use in accessing the UDMA registers. 4 // 5 // Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 9453 of the Stellaris Firmware Development Package. 37 // 38 //***************************************************************************** 39 40 #ifndef __HW_UDMA_H__ 41 #define __HW_UDMA_H__ 42 43 //***************************************************************************** 44 // 45 // The following are defines for the Micro Direct Memory Access register 46 // addresses. 47 // 48 //***************************************************************************** 49 #define UDMA_STAT 0x400FF000 // DMA Status 50 #define UDMA_CFG 0x400FF004 // DMA Configuration 51 #define UDMA_CTLBASE 0x400FF008 // DMA Channel Control Base Pointer 52 #define UDMA_ALTBASE 0x400FF00C // DMA Alternate Channel Control 53 // Base Pointer 54 #define UDMA_WAITSTAT 0x400FF010 // DMA Channel Wait-on-Request 55 // Status 56 #define UDMA_SWREQ 0x400FF014 // DMA Channel Software Request 57 #define UDMA_USEBURSTSET 0x400FF018 // DMA Channel Useburst Set 58 #define UDMA_USEBURSTCLR 0x400FF01C // DMA Channel Useburst Clear 59 #define UDMA_REQMASKSET 0x400FF020 // DMA Channel Request Mask Set 60 #define UDMA_REQMASKCLR 0x400FF024 // DMA Channel Request Mask Clear 61 #define UDMA_ENASET 0x400FF028 // DMA Channel Enable Set 62 #define UDMA_ENACLR 0x400FF02C // DMA Channel Enable Clear 63 #define UDMA_ALTSET 0x400FF030 // DMA Channel Primary Alternate 64 // Set 65 #define UDMA_ALTCLR 0x400FF034 // DMA Channel Primary Alternate 66 // Clear 67 #define UDMA_PRIOSET 0x400FF038 // DMA Channel Priority Set 68 #define UDMA_PRIOCLR 0x400FF03C // DMA Channel Priority Clear 69 #define UDMA_ERRCLR 0x400FF04C // DMA Bus Error Clear 70 #define UDMA_CHASGN 0x400FF500 // DMA Channel Assignment 71 #define UDMA_CHIS 0x400FF504 // DMA Channel Interrupt Status 72 #define UDMA_CHMAP0 0x400FF510 // DMA Channel Map Select 0 73 #define UDMA_CHMAP1 0x400FF514 // DMA Channel Map Select 1 74 #define UDMA_CHMAP2 0x400FF518 // DMA Channel Map Select 2 75 #define UDMA_CHMAP3 0x400FF51C // DMA Channel Map Select 3 76 77 //***************************************************************************** 78 // 79 // The following are defines for the bit fields in the UDMA_STAT register. 80 // 81 //***************************************************************************** 82 #define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1 83 #define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status 84 #define UDMA_STAT_STATE_IDLE 0x00000000 // Idle 85 #define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data 86 #define UDMA_STAT_STATE_RD_SRCENDP \ 87 0x00000020 // Reading source end pointer 88 #define UDMA_STAT_STATE_RD_DSTENDP \ 89 0x00000030 // Reading destination end pointer 90 #define UDMA_STAT_STATE_RD_SRCDAT \ 91 0x00000040 // Reading source data 92 #define UDMA_STAT_STATE_WR_DSTDAT \ 93 0x00000050 // Writing destination data 94 #define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for uDMA request to 95 // clear 96 #define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data 97 #define UDMA_STAT_STATE_STALL 0x00000080 // Stalled 98 #define UDMA_STAT_STATE_DONE 0x00000090 // Done 99 #define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined 100 #define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status 101 #define UDMA_STAT_DMACHANS_S 16 102 103 //***************************************************************************** 104 // 105 // The following are defines for the bit fields in the UDMA_CFG register. 106 // 107 //***************************************************************************** 108 #define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable 109 110 //***************************************************************************** 111 // 112 // The following are defines for the bit fields in the UDMA_CTLBASE register. 113 // 114 //***************************************************************************** 115 #define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address 116 #define UDMA_CTLBASE_ADDR_S 10 117 118 //***************************************************************************** 119 // 120 // The following are defines for the bit fields in the UDMA_ALTBASE register. 121 // 122 //***************************************************************************** 123 #define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address 124 // Pointer 125 #define UDMA_ALTBASE_ADDR_S 0 126 127 //***************************************************************************** 128 // 129 // The following are defines for the bit fields in the UDMA_WAITSTAT register. 130 // 131 //***************************************************************************** 132 #define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status 133 134 //***************************************************************************** 135 // 136 // The following are defines for the bit fields in the UDMA_SWREQ register. 137 // 138 //***************************************************************************** 139 #define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request 140 141 //***************************************************************************** 142 // 143 // The following are defines for the bit fields in the UDMA_USEBURSTSET 144 // register. 145 // 146 //***************************************************************************** 147 #define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set 148 149 //***************************************************************************** 150 // 151 // The following are defines for the bit fields in the UDMA_USEBURSTCLR 152 // register. 153 // 154 //***************************************************************************** 155 #define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear 156 157 //***************************************************************************** 158 // 159 // The following are defines for the bit fields in the UDMA_REQMASKSET 160 // register. 161 // 162 //***************************************************************************** 163 #define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set 164 165 //***************************************************************************** 166 // 167 // The following are defines for the bit fields in the UDMA_REQMASKCLR 168 // register. 169 // 170 //***************************************************************************** 171 #define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear 172 173 //***************************************************************************** 174 // 175 // The following are defines for the bit fields in the UDMA_ENASET register. 176 // 177 //***************************************************************************** 178 #define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set 179 180 //***************************************************************************** 181 // 182 // The following are defines for the bit fields in the UDMA_ENACLR register. 183 // 184 //***************************************************************************** 185 #define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear 186 187 //***************************************************************************** 188 // 189 // The following are defines for the bit fields in the UDMA_ALTSET register. 190 // 191 //***************************************************************************** 192 #define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set 193 194 //***************************************************************************** 195 // 196 // The following are defines for the bit fields in the UDMA_ALTCLR register. 197 // 198 //***************************************************************************** 199 #define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear 200 201 //***************************************************************************** 202 // 203 // The following are defines for the bit fields in the UDMA_PRIOSET register. 204 // 205 //***************************************************************************** 206 #define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set 207 208 //***************************************************************************** 209 // 210 // The following are defines for the bit fields in the UDMA_PRIOCLR register. 211 // 212 //***************************************************************************** 213 #define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear 214 215 //***************************************************************************** 216 // 217 // The following are defines for the bit fields in the UDMA_ERRCLR register. 218 // 219 //***************************************************************************** 220 #define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status 221 222 //***************************************************************************** 223 // 224 // The following are defines for the bit fields in the UDMA_CHASGN register. 225 // 226 //***************************************************************************** 227 #define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select 228 #define UDMA_CHASGN_PRIMARY 0x00000000 // Use the primary channel 229 // assignment 230 #define UDMA_CHASGN_SECONDARY 0x00000001 // Use the secondary channel 231 // assignment 232 233 //***************************************************************************** 234 // 235 // The following are defines for the bit fields in the UDMA_CHIS register. 236 // 237 //***************************************************************************** 238 #define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status 239 240 //***************************************************************************** 241 // 242 // The following are defines for the bit fields in the UDMA_CHMAP0 register. 243 // 244 //***************************************************************************** 245 #define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select 246 #define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select 247 #define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select 248 #define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select 249 #define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select 250 #define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select 251 #define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select 252 #define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select 253 #define UDMA_CHMAP0_CH7SEL_S 28 254 #define UDMA_CHMAP0_CH6SEL_S 24 255 #define UDMA_CHMAP0_CH5SEL_S 20 256 #define UDMA_CHMAP0_CH4SEL_S 16 257 #define UDMA_CHMAP0_CH3SEL_S 12 258 #define UDMA_CHMAP0_CH2SEL_S 8 259 #define UDMA_CHMAP0_CH1SEL_S 4 260 #define UDMA_CHMAP0_CH0SEL_S 0 261 262 //***************************************************************************** 263 // 264 // The following are defines for the bit fields in the UDMA_CHMAP1 register. 265 // 266 //***************************************************************************** 267 #define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select 268 #define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select 269 #define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select 270 #define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select 271 #define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select 272 #define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select 273 #define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select 274 #define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select 275 #define UDMA_CHMAP1_CH15SEL_S 28 276 #define UDMA_CHMAP1_CH14SEL_S 24 277 #define UDMA_CHMAP1_CH13SEL_S 20 278 #define UDMA_CHMAP1_CH12SEL_S 16 279 #define UDMA_CHMAP1_CH11SEL_S 12 280 #define UDMA_CHMAP1_CH10SEL_S 8 281 #define UDMA_CHMAP1_CH9SEL_S 4 282 #define UDMA_CHMAP1_CH8SEL_S 0 283 284 //***************************************************************************** 285 // 286 // The following are defines for the bit fields in the UDMA_CHMAP2 register. 287 // 288 //***************************************************************************** 289 #define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select 290 #define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select 291 #define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select 292 #define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select 293 #define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select 294 #define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select 295 #define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select 296 #define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select 297 #define UDMA_CHMAP2_CH23SEL_S 28 298 #define UDMA_CHMAP2_CH22SEL_S 24 299 #define UDMA_CHMAP2_CH21SEL_S 20 300 #define UDMA_CHMAP2_CH20SEL_S 16 301 #define UDMA_CHMAP2_CH19SEL_S 12 302 #define UDMA_CHMAP2_CH18SEL_S 8 303 #define UDMA_CHMAP2_CH17SEL_S 4 304 #define UDMA_CHMAP2_CH16SEL_S 0 305 306 //***************************************************************************** 307 // 308 // The following are defines for the bit fields in the UDMA_CHMAP3 register. 309 // 310 //***************************************************************************** 311 #define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select 312 #define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select 313 #define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select 314 #define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select 315 #define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select 316 #define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select 317 #define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select 318 #define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select 319 #define UDMA_CHMAP3_CH31SEL_S 28 320 #define UDMA_CHMAP3_CH30SEL_S 24 321 #define UDMA_CHMAP3_CH29SEL_S 20 322 #define UDMA_CHMAP3_CH28SEL_S 16 323 #define UDMA_CHMAP3_CH27SEL_S 12 324 #define UDMA_CHMAP3_CH26SEL_S 8 325 #define UDMA_CHMAP3_CH25SEL_S 4 326 #define UDMA_CHMAP3_CH24SEL_S 0 327 328 //***************************************************************************** 329 // 330 // The following are defines for the Micro Direct Memory Access (uDMA) offsets. 331 // 332 //***************************************************************************** 333 #define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End 334 // Pointer 335 #define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address 336 // End Pointer 337 #define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word 338 339 //***************************************************************************** 340 // 341 // The following are defines for the bit fields in the UDMA_O_SRCENDP register. 342 // 343 //***************************************************************************** 344 #define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer 345 #define UDMA_SRCENDP_ADDR_S 0 346 347 //***************************************************************************** 348 // 349 // The following are defines for the bit fields in the UDMA_O_DSTENDP register. 350 // 351 //***************************************************************************** 352 #define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer 353 #define UDMA_DSTENDP_ADDR_S 0 354 355 //***************************************************************************** 356 // 357 // The following are defines for the bit fields in the UDMA_O_CHCTL register. 358 // 359 //***************************************************************************** 360 #define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment 361 #define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte 362 #define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word 363 #define UDMA_CHCTL_DSTINC_32 0x80000000 // Word 364 #define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment 365 #define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size 366 #define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte 367 #define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word 368 #define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word 369 #define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment 370 #define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte 371 #define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word 372 #define UDMA_CHCTL_SRCINC_32 0x08000000 // Word 373 #define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment 374 #define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size 375 #define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte 376 #define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word 377 #define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word 378 #define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size 379 #define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer 380 #define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers 381 #define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers 382 #define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers 383 #define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers 384 #define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers 385 #define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers 386 #define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers 387 #define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers 388 #define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers 389 #define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers 390 #define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1) 391 #define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst 392 #define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode 393 #define UDMA_CHCTL_XFERMODE_STOP \ 394 0x00000000 // Stop 395 #define UDMA_CHCTL_XFERMODE_BASIC \ 396 0x00000001 // Basic 397 #define UDMA_CHCTL_XFERMODE_AUTO \ 398 0x00000002 // Auto-Request 399 #define UDMA_CHCTL_XFERMODE_PINGPONG \ 400 0x00000003 // Ping-Pong 401 #define UDMA_CHCTL_XFERMODE_MEM_SG \ 402 0x00000004 // Memory Scatter-Gather 403 #define UDMA_CHCTL_XFERMODE_MEM_SGA \ 404 0x00000005 // Alternate Memory Scatter-Gather 405 #define UDMA_CHCTL_XFERMODE_PER_SG \ 406 0x00000006 // Peripheral Scatter-Gather 407 #define UDMA_CHCTL_XFERMODE_PER_SGA \ 408 0x00000007 // Alternate Peripheral 409 // Scatter-Gather 410 #define UDMA_CHCTL_XFERSIZE_S 4 411 412 //***************************************************************************** 413 // 414 // The following definitions are deprecated. 415 // 416 //***************************************************************************** 417 #ifndef DEPRECATED 418 419 //***************************************************************************** 420 // 421 // The following are deprecated defines for the Micro Direct Memory Access 422 // register addresses. 423 // 424 //***************************************************************************** 425 #define UDMA_CHALT 0x400FF500 // DMA Channel Alternate Select 426 427 //***************************************************************************** 428 // 429 // The following are deprecated defines for the bit fields in the UDMA_ENASET 430 // register. 431 // 432 //***************************************************************************** 433 #define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set 434 435 //***************************************************************************** 436 // 437 // The following are deprecated defines for the bit fields in the UDMA_CHALT 438 // register. 439 // 440 //***************************************************************************** 441 #define UDMA_CHALT_M 0xFFFFFFFF // Channel [n] Alternate Assignment 442 // Select 443 444 #endif 445 446 #endif // __HW_UDMA_H__ 447