1 //***************************************************************************** 2 // 3 // udma.h - Prototypes and macros for the uDMA controller. 4 // 5 // Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Redistribution and use in source and binary forms, with or without 9 // modification, are permitted provided that the following conditions 10 // are met: 11 // 12 // Redistributions of source code must retain the above copyright 13 // notice, this list of conditions and the following disclaimer. 14 // 15 // Redistributions in binary form must reproduce the above copyright 16 // notice, this list of conditions and the following disclaimer in the 17 // documentation and/or other materials provided with the 18 // distribution. 19 // 20 // Neither the name of Texas Instruments Incorporated nor the names of 21 // its contributors may be used to endorse or promote products derived 22 // from this software without specific prior written permission. 23 // 24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 // 36 // This is part of revision 9453 of the Stellaris Peripheral Driver Library. 37 // 38 //***************************************************************************** 39 40 #ifndef __UDMA_H__ 41 #define __UDMA_H__ 42 43 //***************************************************************************** 44 // 45 // If building with a C++ compiler, make all of the definitions in this header 46 // have a C binding. 47 // 48 //***************************************************************************** 49 #ifdef __cplusplus 50 extern "C" 51 { 52 #endif 53 54 //***************************************************************************** 55 // 56 //! \addtogroup udma_api 57 //! @{ 58 // 59 //***************************************************************************** 60 61 //***************************************************************************** 62 // 63 // A structure that defines an entry in the channel control table. These 64 // fields are used by the uDMA controller and normally it is not necessary for 65 // software to directly read or write fields in the table. 66 // 67 //***************************************************************************** 68 typedef struct 69 { 70 // 71 // The ending source address of the data transfer. 72 // 73 volatile void *pvSrcEndAddr; 74 75 // 76 // The ending destination address of the data transfer. 77 // 78 volatile void *pvDstEndAddr; 79 80 // 81 // The channel control mode. 82 // 83 volatile unsigned long ulControl; 84 85 // 86 // An unused location. 87 // 88 volatile unsigned long ulSpare; 89 } 90 tDMAControlTable; 91 92 //***************************************************************************** 93 // 94 //! A helper macro for building scatter-gather task table entries. 95 //! 96 //! \param ulTransferCount is the count of items to transfer for this task. 97 //! \param ulItemSize is the bit size of the items to transfer for this task. 98 //! \param ulSrcIncrement is the bit size increment for source data. 99 //! \param pvSrcAddr is the starting address of the data to transfer. 100 //! \param ulDstIncrement is the bit size increment for destination data. 101 //! \param pvDstAddr is the starting address of the destination data. 102 //! \param ulArbSize is the arbitration size to use for the transfer task. 103 //! \param ulMode is the transfer mode for this task. 104 //! 105 //! This macro is intended to be used to help populate a table of uDMA tasks 106 //! for a scatter-gather transfer. This macro will calculate the values for 107 //! the fields of a task structure entry based on the input parameters. 108 //! 109 //! There are specific requirements for the values of each parameter. No 110 //! checking is done so it is up to the caller to ensure that correct values 111 //! are used for the parameters. 112 //! 113 //! The \e ulTransferCount parameter is the number of items that will be 114 //! transferred by this task. It must be in the range 1-1024. 115 //! 116 //! The \e ulItemSize parameter is the bit size of the transfer data. It must 117 //! be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32. 118 //! 119 //! The \e ulSrcIncrement parameter is the increment size for the source data. 120 //! It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16, 121 //! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE. 122 //! 123 //! The \e pvSrcAddr parameter is a void pointer to the beginning of the source 124 //! data. 125 //! 126 //! The \e ulDstIncrement parameter is the increment size for the destination 127 //! data. It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16, 128 //! \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE. 129 //! 130 //! The \e pvDstAddr parameter is a void pointer to the beginning of the 131 //! location where the data will be transferred. 132 //! 133 //! The \e ulArbSize parameter is the arbitration size for the transfer, and 134 //! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on 135 //! up to \b UDMA_ARB_1024. This is used to select the arbitration size in 136 //! powers of 2, from 1 to 1024. 137 //! 138 //! The \e ulMode parameter is the mode to use for this transfer task. It 139 //! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, 140 //! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. Note 141 //! that normally all tasks will be one of the scatter-gather modes while the 142 //! last task is a task list will be AUTO or BASIC. 143 //! 144 //! This macro is intended to be used to initialize individual entries of 145 //! a structure of tDMAControlTable type, like this: 146 //! 147 //! \verbatim 148 //! tDMAControlTable MyTaskList[] = 149 //! { 150 //! uDMATaskStructEntry(Task1Count, UDMA_SIZE_8, 151 //! UDMA_SRC_INC_8, MySourceBuf, 152 //! UDMA_DST_INC_8, MyDestBuf, 153 //! UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER), 154 //! uDMATaskStructEntry(Task2Count, ... ), 155 //! } 156 //! \endverbatim 157 //! 158 //! \return Nothing; this is not a function. 159 // 160 //***************************************************************************** 161 #define uDMATaskStructEntry(ulTransferCount, \ 162 ulItemSize, \ 163 ulSrcIncrement, \ 164 pvSrcAddr, \ 165 ulDstIncrement, \ 166 pvDstAddr, \ 167 ulArbSize, \ 168 ulMode) \ 169 { \ 170 (((ulSrcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(pvSrcAddr) : \ 171 ((void *)(&((unsigned char *)(pvSrcAddr))[((ulTransferCount) << \ 172 ((ulSrcIncrement) >> 26)) - 1]))), \ 173 (((ulDstIncrement) == UDMA_DST_INC_NONE) ? (void *)(pvDstAddr) : \ 174 ((void *)(&((unsigned char *)(pvDstAddr))[((ulTransferCount) << \ 175 ((ulDstIncrement) >> 30)) - 1]))), \ 176 (ulSrcIncrement) | (ulDstIncrement) | (ulItemSize) | (ulArbSize) | \ 177 (((ulTransferCount) - 1) << 4) | \ 178 ((((ulMode) == UDMA_MODE_MEM_SCATTER_GATHER) || \ 179 ((ulMode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \ 180 (ulMode) | UDMA_MODE_ALT_SELECT : (ulMode)), 0 \ 181 } 182 183 //***************************************************************************** 184 // 185 // Close the Doxygen group. 186 //! @} 187 // 188 //***************************************************************************** 189 190 //***************************************************************************** 191 // 192 // Flags that can be passed to uDMAChannelAttributeEnable(), 193 // uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet(). 194 // 195 //***************************************************************************** 196 #define UDMA_ATTR_USEBURST 0x00000001 197 #define UDMA_ATTR_ALTSELECT 0x00000002 198 #define UDMA_ATTR_HIGH_PRIORITY 0x00000004 199 #define UDMA_ATTR_REQMASK 0x00000008 200 #define UDMA_ATTR_ALL 0x0000000F 201 202 //***************************************************************************** 203 // 204 // DMA control modes that can be passed to uDMAModeSet() and returned 205 // uDMAModeGet(). 206 // 207 //***************************************************************************** 208 #define UDMA_MODE_STOP 0x00000000 209 #define UDMA_MODE_BASIC 0x00000001 210 #define UDMA_MODE_AUTO 0x00000002 211 #define UDMA_MODE_PINGPONG 0x00000003 212 #define UDMA_MODE_MEM_SCATTER_GATHER \ 213 0x00000004 214 #define UDMA_MODE_PER_SCATTER_GATHER \ 215 0x00000006 216 #define UDMA_MODE_ALT_SELECT 0x00000001 217 218 //***************************************************************************** 219 // 220 // Channel configuration values that can be passed to uDMAControlSet(). 221 // 222 //***************************************************************************** 223 #define UDMA_DST_INC_8 0x00000000 224 #define UDMA_DST_INC_16 0x40000000 225 #define UDMA_DST_INC_32 0x80000000 226 #define UDMA_DST_INC_NONE 0xc0000000 227 #define UDMA_SRC_INC_8 0x00000000 228 #define UDMA_SRC_INC_16 0x04000000 229 #define UDMA_SRC_INC_32 0x08000000 230 #define UDMA_SRC_INC_NONE 0x0c000000 231 #define UDMA_SIZE_8 0x00000000 232 #define UDMA_SIZE_16 0x11000000 233 #define UDMA_SIZE_32 0x22000000 234 #define UDMA_ARB_1 0x00000000 235 #define UDMA_ARB_2 0x00004000 236 #define UDMA_ARB_4 0x00008000 237 #define UDMA_ARB_8 0x0000c000 238 #define UDMA_ARB_16 0x00010000 239 #define UDMA_ARB_32 0x00014000 240 #define UDMA_ARB_64 0x00018000 241 #define UDMA_ARB_128 0x0001c000 242 #define UDMA_ARB_256 0x00020000 243 #define UDMA_ARB_512 0x00024000 244 #define UDMA_ARB_1024 0x00028000 245 #define UDMA_NEXT_USEBURST 0x00000008 246 247 //***************************************************************************** 248 // 249 // Channel numbers to be passed to API functions that require a channel number 250 // ID. 251 // 252 //***************************************************************************** 253 #define UDMA_CHANNEL_USBEP1RX 0 254 #define UDMA_CHANNEL_USBEP1TX 1 255 #define UDMA_CHANNEL_USBEP2RX 2 256 #define UDMA_CHANNEL_USBEP2TX 3 257 #define UDMA_CHANNEL_USBEP3RX 4 258 #define UDMA_CHANNEL_USBEP3TX 5 259 #define UDMA_CHANNEL_ETH0RX 6 260 #define UDMA_CHANNEL_ETH0TX 7 261 #define UDMA_CHANNEL_UART0RX 8 262 #define UDMA_CHANNEL_UART0TX 9 263 #define UDMA_CHANNEL_SSI0RX 10 264 #define UDMA_CHANNEL_SSI0TX 11 265 #define UDMA_CHANNEL_ADC0 14 266 #define UDMA_CHANNEL_ADC1 15 267 #define UDMA_CHANNEL_ADC2 16 268 #define UDMA_CHANNEL_ADC3 17 269 #define UDMA_CHANNEL_TMR0A 18 270 #define UDMA_CHANNEL_TMR0B 19 271 #define UDMA_CHANNEL_TMR1A 20 272 #define UDMA_CHANNEL_TMR1B 21 273 #define UDMA_CHANNEL_UART1RX 22 274 #define UDMA_CHANNEL_UART1TX 23 275 #define UDMA_CHANNEL_SSI1RX 24 276 #define UDMA_CHANNEL_SSI1TX 25 277 #define UDMA_CHANNEL_I2S0RX 28 278 #define UDMA_CHANNEL_I2S0TX 29 279 #define UDMA_CHANNEL_SW 30 280 281 //***************************************************************************** 282 // 283 // Flags to be OR'd with the channel ID to indicate if the primary or alternate 284 // control structure should be used. 285 // 286 //***************************************************************************** 287 #define UDMA_PRI_SELECT 0x00000000 288 #define UDMA_ALT_SELECT 0x00000020 289 290 //***************************************************************************** 291 // 292 // uDMA interrupt sources, to be passed to uDMAIntRegister() and 293 // uDMAIntUnregister(). 294 // 295 //***************************************************************************** 296 #define UDMA_INT_SW 62 297 #define UDMA_INT_ERR 63 298 299 //***************************************************************************** 300 // 301 // Channel numbers to be passed to API functions that require a channel number 302 // ID. These are for secondary peripheral assignments. 303 // 304 //***************************************************************************** 305 #define UDMA_SEC_CHANNEL_UART2RX_0 \ 306 0 307 #define UDMA_SEC_CHANNEL_UART2TX_1 \ 308 1 309 #define UDMA_SEC_CHANNEL_TMR3A 2 310 #define UDMA_SEC_CHANNEL_TMR3B 3 311 #define UDMA_SEC_CHANNEL_TMR2A_4 \ 312 4 313 #define UDMA_SEC_CHANNEL_TMR2B_5 \ 314 5 315 #define UDMA_SEC_CHANNEL_TMR2A_6 \ 316 6 317 #define UDMA_SEC_CHANNEL_TMR2B_7 \ 318 7 319 #define UDMA_SEC_CHANNEL_UART1RX \ 320 8 321 #define UDMA_SEC_CHANNEL_UART1TX \ 322 9 323 #define UDMA_SEC_CHANNEL_SSI1RX 10 324 #define UDMA_SEC_CHANNEL_SSI1TX 11 325 #define UDMA_SEC_CHANNEL_UART2RX_12 \ 326 12 327 #define UDMA_SEC_CHANNEL_UART2TX_13 \ 328 13 329 #define UDMA_SEC_CHANNEL_TMR2A_14 \ 330 14 331 #define UDMA_SEC_CHANNEL_TMR2B_15 \ 332 15 333 #define UDMA_SEC_CHANNEL_TMR1A 18 334 #define UDMA_SEC_CHANNEL_TMR1B 19 335 #define UDMA_SEC_CHANNEL_EPI0RX 20 336 #define UDMA_SEC_CHANNEL_EPI0TX 21 337 #define UDMA_SEC_CHANNEL_ADC10 24 338 #define UDMA_SEC_CHANNEL_ADC11 25 339 #define UDMA_SEC_CHANNEL_ADC12 26 340 #define UDMA_SEC_CHANNEL_ADC13 27 341 #define UDMA_SEC_CHANNEL_SW 30 342 343 //***************************************************************************** 344 // 345 // uDMA default/secondary peripheral selections, to be passed to 346 // uDMAChannelSelectSecondary() and uDMAChannelSelectDefault(). 347 // 348 //***************************************************************************** 349 #define UDMA_DEF_USBEP1RX_SEC_UART2RX \ 350 0x00000001 351 #define UDMA_DEF_USBEP1TX_SEC_UART2TX \ 352 0x00000002 353 #define UDMA_DEF_USBEP2RX_SEC_TMR3A \ 354 0x00000004 355 #define UDMA_DEF_USBEP2TX_SEC_TMR3B \ 356 0x00000008 357 #define UDMA_DEF_USBEP3RX_SEC_TMR2A \ 358 0x00000010 359 #define UDMA_DEF_USBEP3TX_SEC_TMR2B \ 360 0x00000020 361 #define UDMA_DEF_ETH0RX_SEC_TMR2A \ 362 0x00000040 363 #define UDMA_DEF_ETH0TX_SEC_TMR2B \ 364 0x00000080 365 #define UDMA_DEF_UART0RX_SEC_UART1RX \ 366 0x00000100 367 #define UDMA_DEF_UART0TX_SEC_UART1TX \ 368 0x00000200 369 #define UDMA_DEF_SSI0RX_SEC_SSI1RX \ 370 0x00000400 371 #define UDMA_DEF_SSI0TX_SEC_SSI1TX \ 372 0x00000800 373 #define UDMA_DEF_RESERVED_SEC_UART2RX \ 374 0x00001000 375 #define UDMA_DEF_RESERVED_SEC_UART2TX \ 376 0x00002000 377 #define UDMA_DEF_ADC00_SEC_TMR2A \ 378 0x00004000 379 #define UDMA_DEF_ADC01_SEC_TMR2B \ 380 0x00008000 381 #define UDMA_DEF_ADC02_SEC_RESERVED \ 382 0x00010000 383 #define UDMA_DEF_ADC03_SEC_RESERVED \ 384 0x00020000 385 #define UDMA_DEF_TMR0A_SEC_TMR1A \ 386 0x00040000 387 #define UDMA_DEF_TMR0B_SEC_TMR1B \ 388 0x00080000 389 #define UDMA_DEF_TMR1A_SEC_EPI0RX \ 390 0x00100000 391 #define UDMA_DEF_TMR1B_SEC_EPI0TX \ 392 0x00200000 393 #define UDMA_DEF_UART1RX_SEC_RESERVED \ 394 0x00400000 395 #define UDMA_DEF_UART1TX_SEC_RESERVED \ 396 0x00800000 397 #define UDMA_DEF_SSI1RX_SEC_ADC10 \ 398 0x01000000 399 #define UDMA_DEF_SSI1TX_SEC_ADC11 \ 400 0x02000000 401 #define UDMA_DEF_RESERVED_SEC_ADC12 \ 402 0x04000000 403 #define UDMA_DEF_RESERVED_SEC_ADC13 \ 404 0x08000000 405 #define UDMA_DEF_I2S0RX_SEC_RESERVED \ 406 0x10000000 407 #define UDMA_DEF_I2S0TX_SEC_RESERVED \ 408 0x20000000 409 410 //***************************************************************************** 411 // 412 // Values that can be passed to uDMAChannelAssign() to select peripheral 413 // mapping for each channel. The channels named RESERVED may be assigned 414 // to a peripheral in future parts. 415 // 416 //***************************************************************************** 417 // 418 // Channel 0 419 // 420 #define UDMA_CH0_USB0EP1RX 0x00000000 421 #define UDMA_CH0_UART2RX 0x00010000 422 #define UDMA_CH0_RESERVED2 0x00020000 423 #define UDMA_CH0_TIMER4A 0x00030000 424 #define UDMA_CH0_RESERVED4 0x00040000 425 426 // 427 // Channel 1 428 // 429 #define UDMA_CH1_USB0EP1TX 0x00000001 430 #define UDMA_CH1_UART2TX 0x00010001 431 #define UDMA_CH1_RESERVED2 0x00020001 432 #define UDMA_CH1_TIMER4B 0x00030001 433 #define UDMA_CH1_RESERVED4 0x00040001 434 435 // 436 // Channel 2 437 // 438 #define UDMA_CH2_USB0EP2RX 0x00000002 439 #define UDMA_CH2_TIMER3A 0x00010002 440 #define UDMA_CH2_RESERVED2 0x00020002 441 #define UDMA_CH2_RESERVED3 0x00030002 442 #define UDMA_CH2_RESERVED4 0x00040002 443 444 // 445 // Channel 3 446 // 447 #define UDMA_CH3_USB0EP2TX 0x00000003 448 #define UDMA_CH3_TIMER3B 0x00010003 449 #define UDMA_CH3_RESERVED2 0x00020003 450 #define UDMA_CH3_LPC0_3 0x00030003 451 #define UDMA_CH3_RESERVED4 0x00040003 452 453 // 454 // Channel 4 455 // 456 #define UDMA_CH4_USB0EP3RX 0x00000004 457 #define UDMA_CH4_TIMER2A 0x00010004 458 #define UDMA_CH4_RESERVED2 0x00020004 459 #define UDMA_CH4_GPIOA 0x00030004 460 #define UDMA_CH4_RESERVED4 0x00040004 461 462 // 463 // Channel 5 464 // 465 #define UDMA_CH5_USB0EP3TX 0x00000005 466 #define UDMA_CH5_TIMER2B 0x00010005 467 #define UDMA_CH5_RESERVED2 0x00020005 468 #define UDMA_CH5_GPIOB 0x00030005 469 #define UDMA_CH5_RESERVED4 0x00040005 470 471 // 472 // Channel 6 473 // 474 #define UDMA_CH6_RESERVED0 0x00000006 475 #define UDMA_CH6_TIMER2A 0x00010006 476 #define UDMA_CH6_UART5RX 0x00020006 477 #define UDMA_CH6_GPIOC 0x00030006 478 #define UDMA_CH6_I2C0RX 0x00040006 479 480 // 481 // Channel 7 482 // 483 #define UDMA_CH7_RESERVED0 0x00000007 484 #define UDMA_CH7_TIMER2B 0x00010007 485 #define UDMA_CH7_UART5TX 0x00020007 486 #define UDMA_CH7_GPIOD 0x00030007 487 #define UDMA_CH7_I2C0TX 0x00040007 488 489 // 490 // Channel 8 491 // 492 #define UDMA_CH8_UART0RX 0x00000008 493 #define UDMA_CH8_UART1RX 0x00010008 494 #define UDMA_CH8_RESERVED2 0x00020008 495 #define UDMA_CH8_TIMER5A 0x00030008 496 #define UDMA_CH8_I2C1RX 0x00040008 497 498 // 499 // Channel 9 500 // 501 #define UDMA_CH9_UART0TX 0x00000009 502 #define UDMA_CH9_UART1TX 0x00010009 503 #define UDMA_CH9_RESERVED2 0x00020009 504 #define UDMA_CH9_TIMER5B 0x00030009 505 #define UDMA_CH9_I2C1TX 0x00040009 506 507 // 508 // Channel 10 509 // 510 #define UDMA_CH10_SSI0RX 0x0000000A 511 #define UDMA_CH10_SSI1RX 0x0001000A 512 #define UDMA_CH10_UART6RX 0x0002000A 513 #define UDMA_CH10_WTIMER0A 0x0003000A 514 #define UDMA_CH10_I2C2RX 0x0004000A 515 516 // 517 // Channel 11 518 // 519 #define UDMA_CH11_SSI0TX 0x0000000B 520 #define UDMA_CH11_SSI1TX 0x0001000B 521 #define UDMA_CH11_UART6TX 0x0002000B 522 #define UDMA_CH11_WTIMER0B 0x0003000B 523 #define UDMA_CH11_I2C2TX 0x0004000B 524 525 // 526 // Channel 12 527 // 528 #define UDMA_CH12_RESERVED0 0x0000000C 529 #define UDMA_CH12_UART2RX 0x0001000C 530 #define UDMA_CH12_SSI2RX 0x0002000C 531 #define UDMA_CH12_WTIMER1A 0x0003000C 532 #define UDMA_CH12_GPIOK 0x0004000C 533 534 // 535 // Channel 13 536 // 537 #define UDMA_CH13_RESERVED0 0x0000000D 538 #define UDMA_CH13_UART2TX 0x0001000D 539 #define UDMA_CH13_SSI2TX 0x0002000D 540 #define UDMA_CH13_WTIMER1B 0x0003000D 541 #define UDMA_CH13_GPIOL 0x0004000D 542 543 // 544 // Channel 14 545 // 546 #define UDMA_CH14_ADC0_0 0x0000000E 547 #define UDMA_CH14_TIMER2A 0x0001000E 548 #define UDMA_CH14_SSI3RX 0x0002000E 549 #define UDMA_CH14_GPIOE 0x0003000E 550 #define UDMA_CH14_GPIOM 0x0004000E 551 552 // 553 // Channel 15 554 // 555 #define UDMA_CH15_ADC0_1 0x0000000F 556 #define UDMA_CH15_TIMER2B 0x0001000F 557 #define UDMA_CH15_SSI3TX 0x0002000F 558 #define UDMA_CH15_GPIOF 0x0003000F 559 #define UDMA_CH15_GPION 0x0004000F 560 561 // 562 // Channel 16 563 // 564 #define UDMA_CH16_ADC0_2 0x00000010 565 #define UDMA_CH16_RESERVED1 0x00010010 566 #define UDMA_CH16_UART3RX 0x00020010 567 #define UDMA_CH16_WTIMER2A 0x00030010 568 #define UDMA_CH16_GPIOP 0x00040010 569 570 // 571 // Channel 17 572 // 573 #define UDMA_CH17_ADC0_3 0x00000011 574 #define UDMA_CH17_RESERVED1 0x00010011 575 #define UDMA_CH17_UART3TX 0x00020011 576 #define UDMA_CH17_WTIMER2B 0x00030011 577 #define UDMA_CH17_RESERVED4 0x00040011 578 579 // 580 // Channel 18 581 // 582 #define UDMA_CH18_TIMER0A 0x00000012 583 #define UDMA_CH18_TIMER1A 0x00010012 584 #define UDMA_CH18_UART4RX 0x00020012 585 #define UDMA_CH18_GPIOB 0x00030012 586 #define UDMA_CH18_I2C3RX 0x00040012 587 588 // 589 // Channel 19 590 // 591 #define UDMA_CH19_TIMER0B 0x00000013 592 #define UDMA_CH19_TIMER1B 0x00010013 593 #define UDMA_CH19_UART4TX 0x00020013 594 #define UDMA_CH19_GPIOG 0x00030013 595 #define UDMA_CH19_I2C3TX 0x00040013 596 597 // 598 // Channel 20 599 // 600 #define UDMA_CH20_TIMER1A 0x00000014 601 #define UDMA_CH20_RESERVED1 0x00010014 602 #define UDMA_CH20_UART7RX 0x00020014 603 #define UDMA_CH20_GPIOH 0x00030014 604 #define UDMA_CH20_I2C4RX 0x00040014 605 606 // 607 // Channel 21 608 // 609 #define UDMA_CH21_TIMER1B 0x00000015 610 #define UDMA_CH21_RESERVED1 0x00010015 611 #define UDMA_CH21_UART7TX 0x00020015 612 #define UDMA_CH21_GPIOJ 0x00030015 613 #define UDMA_CH21_I2C4TX 0x00040015 614 615 // 616 // Channel 22 617 // 618 #define UDMA_CH22_UART1RX 0x00000016 619 #define UDMA_CH22_RESERVED1 0x00010016 620 #define UDMA_CH22_RESERVED2 0x00020016 621 #define UDMA_CH22_LPC0_2 0x00030016 622 #define UDMA_CH22_I2C5RX 0x00040016 623 624 // 625 // Channel 23 626 // 627 #define UDMA_CH23_UART1TX 0x00000017 628 #define UDMA_CH23_RESERVED1 0x00010017 629 #define UDMA_CH23_RESERVED2 0x00020017 630 #define UDMA_CH23_LPC0_1 0x00030017 631 #define UDMA_CH23_I2C5TX 0x00040017 632 633 // 634 // Channel 24 635 // 636 #define UDMA_CH24_SSI1RX 0x00000018 637 #define UDMA_CH24_ADC1_0 0x00010018 638 #define UDMA_CH24_RESERVED2 0x00020018 639 #define UDMA_CH24_WTIMER3A 0x00030018 640 #define UDMA_CH24_GPIOQ 0x00040018 641 642 // 643 // Channel 25 644 // 645 #define UDMA_CH25_SSI1TX 0x00000019 646 #define UDMA_CH25_ADC1_1 0x00010019 647 #define UDMA_CH25_RESERVED2 0x00020019 648 #define UDMA_CH25_WTIMER3B 0x00030019 649 #define UDMA_CH25_RESERVED4 0x00040019 650 651 // 652 // Channel 26 653 // 654 #define UDMA_CH26_RESERVED0 0x0000001A 655 #define UDMA_CH26_ADC1_2 0x0001001A 656 #define UDMA_CH26_RESERVED2 0x0002001A 657 #define UDMA_CH26_WTIMER4A 0x0003001A 658 #define UDMA_CH26_RESERVED4 0x0004001A 659 660 // 661 // Channel 27 662 // 663 #define UDMA_CH27_RESERVED0 0x0000001B 664 #define UDMA_CH27_ADC1_3 0x0001001B 665 #define UDMA_CH27_RESERVED2 0x0002001B 666 #define UDMA_CH27_WTIMER4B 0x0003001B 667 #define UDMA_CH27_RESERVED4 0x0004001B 668 669 // 670 // Channel 28 671 // 672 #define UDMA_CH28_RESERVED0 0x0000001C 673 #define UDMA_CH28_RESERVED1 0x0001001C 674 #define UDMA_CH28_RESERVED2 0x0002001C 675 #define UDMA_CH28_WTIMER5A 0x0003001C 676 #define UDMA_CH28_RESERVED4 0x0004001C 677 678 // 679 // Channel 29 680 // 681 #define UDMA_CH29_RESERVED0 0x0000001D 682 #define UDMA_CH29_RESERVED1 0x0001001D 683 #define UDMA_CH29_RESERVED2 0x0002001D 684 #define UDMA_CH29_WTIMER5B 0x0003001D 685 #define UDMA_CH29_RESERVED4 0x0004001D 686 687 // 688 // Channel 30 689 // 690 #define UDMA_CH30_SW 0x0000001E 691 #define UDMA_CH30_RESERVED1 0x0001001E 692 #define UDMA_CH30_RESERVED2 0x0002001E 693 #define UDMA_CH30_RESERVED3 0x0003001E 694 #define UDMA_CH30_RESERVED4 0x0004001E 695 696 // 697 // Channel 31 698 // 699 #define UDMA_CH31_RESERVED0 0x0000001F 700 #define UDMA_CH31_RESERVED1 0x0001001F 701 #define UDMA_CH31_RESERVED2 0x0002001F 702 #define UDMA_CH31_LPC0_0 0x0003001F 703 #define UDMA_CH31_RESERVED4 0x0004001F 704 705 //***************************************************************************** 706 // 707 // API Function prototypes 708 // 709 //***************************************************************************** 710 extern void uDMAEnable(void); 711 extern void uDMADisable(void); 712 extern unsigned long uDMAErrorStatusGet(void); 713 extern void uDMAErrorStatusClear(void); 714 extern void uDMAChannelEnable(unsigned long ulChannelNum); 715 extern void uDMAChannelDisable(unsigned long ulChannelNum); 716 extern tBoolean uDMAChannelIsEnabled(unsigned long ulChannelNum); 717 extern void uDMAControlBaseSet(void *pControlTable); 718 extern void *uDMAControlBaseGet(void); 719 extern void *uDMAControlAlternateBaseGet(void); 720 extern void uDMAChannelRequest(unsigned long ulChannelNum); 721 extern void uDMAChannelAttributeEnable(unsigned long ulChannelNum, 722 unsigned long ulAttr); 723 extern void uDMAChannelAttributeDisable(unsigned long ulChannelNum, 724 unsigned long ulAttr); 725 extern unsigned long uDMAChannelAttributeGet(unsigned long ulChannelNum); 726 extern void uDMAChannelControlSet(unsigned long ulChannelStructIndex, 727 unsigned long ulControl); 728 extern void uDMAChannelTransferSet(unsigned long ulChannelStructIndex, 729 unsigned long ulMode, void *pvSrcAddr, 730 void *pvDstAddr, 731 unsigned long ulTransferSize); 732 extern void uDMAChannelScatterGatherSet(unsigned long ulChannelNum, 733 unsigned ulTaskCount, void *pvTaskList, 734 unsigned long ulIsPeriphSG); 735 extern unsigned long uDMAChannelSizeGet(unsigned long ulChannelStructIndex); 736 extern unsigned long uDMAChannelModeGet(unsigned long ulChannelStructIndex); 737 extern void uDMAIntRegister(unsigned long ulIntChannel, 738 void (*pfnHandler)(void)); 739 extern void uDMAIntUnregister(unsigned long ulIntChannel); 740 extern void uDMAChannelSelectDefault(unsigned long ulDefPeriphs); 741 extern void uDMAChannelSelectSecondary(unsigned long ulSecPeriphs); 742 extern unsigned long uDMAIntStatus(void); 743 extern void uDMAIntClear(unsigned long ulChanMask); 744 extern void uDMAChannelAssign(unsigned long ulMapping); 745 746 //***************************************************************************** 747 // 748 // Mark the end of the C bindings section for C++ compilers. 749 // 750 //***************************************************************************** 751 #ifdef __cplusplus 752 } 753 #endif 754 755 #endif // __UDMA_H__ 756