1 /** 2 ****************************************************************************** 3 * @file rtl8721dhp_usi_i2c.c 4 * @author 5 * @version V1.0.0 6 * @date 2017-12-18 7 * @brief This file contains all the functions prototypes for the I2C firmware 8 * library, including the following functionalities of theIntel-Integrated 9 * Circuit (I2C) peripheral: 10 * - Initialization 11 * - I2C Speed Setting 12 * - I2C Slave Address Updating 13 * - Receive/Send Data Interface 14 * - I2C Peripheral Control (disable/enable) 15 * - I2C SleepMode Control 16 * - Output pin Configuration 17 * - Interrupts and flags management 18 * 19 ****************************************************************************** 20 * @attention 21 * 22 * This module is a confidential and proprietary property of RealTek and 23 * possession or use of this module requires written permission of RealTek. 24 * 25 * Copyright(c) 2017, Realtek Semiconductor Corporation. All rights reserved. 26 ****************************************************************************** 27 */ 28 29 #include "ameba_soc.h" 30 #include "rtl8721d_usi_i2c.h" 31 32 u32 USI_I2C_SLAVEWRITE_PATCH; 33 u32 USI_IC_FS_SCL_HCNT_TRIM; 34 u32 USI_IC_FS_SCL_LCNT_TRIM; 35 36 /** 37 * @brief Fills each USI_I2C_StructInit member with its default value. 38 * @param USI_I2C_StructInit: pointer to an USI_I2C_InitTypeDef structure which will be initialized. 39 * @retval None 40 */ USI_I2C_StructInit(USI_I2C_InitTypeDef * USI_I2C_InitStruct)41 void USI_I2C_StructInit(USI_I2C_InitTypeDef* USI_I2C_InitStruct) 42 { 43 /* Load HAL initial data structure default value */ 44 USI_I2C_InitStruct->USI_I2CMaster = USI_I2C_MASTER_MODE; 45 USI_I2C_InitStruct->USI_I2CAddrMod = USI_I2C_ADDR_7BIT; 46 USI_I2C_InitStruct->USI_I2CSpdMod = USI_I2C_SS_MODE; 47 USI_I2C_InitStruct->USI_I2CClk = 100; 48 USI_I2C_InitStruct->USI_I2CIPClk = 50000000; 49 USI_I2C_InitStruct->USI_I2CAckAddr = 0x11; 50 USI_I2C_InitStruct->USI_I2CSdaHd = 1; 51 USI_I2C_InitStruct->USI_I2CSlvSetup = 0x3; 52 USI_I2C_InitStruct->USI_I2CRXTL = 0x01; 53 USI_I2C_InitStruct->USI_I2CTXTL = 0x10; 54 USI_I2C_InitStruct->USI_I2CMstReSTR = DISABLE; 55 USI_I2C_InitStruct->USI_I2CMstGC = DISABLE; 56 USI_I2C_InitStruct->USI_I2CMstStartB = DISABLE; 57 USI_I2C_InitStruct->USI_I2CSlvNoAck = DISABLE; 58 USI_I2C_InitStruct->USI_I2CFilter = 0x11; 59 USI_I2C_InitStruct->USI_I2CTxDMARqLv = 0x09; 60 USI_I2C_InitStruct->USI_I2CRxDMARqLv = 0x04; 61 } 62 63 /** 64 * @brief Initializes the USIx peripheral according to the specified 65 * parameters in the USI_I2C_InitStruct. 66 * @param USIx: where USIx can be USI0_DEV. 67 * @param USI_I2C_InitStruct: pointer to a USI_I2C_InitTypeDef structure that contains 68 * the configuration information for the specified I2C peripheral. 69 * @retval None 70 */ USI_I2C_Init(USI_TypeDef * USIx,USI_I2C_InitTypeDef * USI_I2C_InitStruct)71 void USI_I2C_Init(USI_TypeDef *USIx, USI_I2C_InitTypeDef* USI_I2C_InitStruct) 72 { 73 u8 Specical; 74 75 /* Check the parameters */ 76 assert_param(IS_USI_I2C_ALL_PERIPH(USIx)); 77 assert_param(IS_USI_I2C_ADDR_MODE(USI_I2C_InitStruct->USI_I2CAddrMod)); 78 assert_param(IS_USI_I2C_SPEED_MODE(USI_I2C_InitStruct->USI_I2CSpdMod)); 79 80 /* Disable the IC first */ 81 USIx->I2C_ENABLE &= ~USI_I2C_ENABLE; 82 83 /*reset USI all logic, this step will clear tx/rx fifo*/ 84 USIx->SW_RESET &=(~USI_SW_RESET_RSTB); 85 USIx->SW_RESET = 0x1f; 86 87 /*disable USI all mode, configure USI with I2C mode*/ 88 USIx->USI_MODE_CTRL &= (~USI_SERIAL_MODE); 89 USIx->USI_MODE_CTRL |= USI_SERIAL_I2C_MODE; 90 91 /* Master case*/ 92 if (USI_I2C_InitStruct->USI_I2CMaster) { 93 /*RESTART MUST be set in these condition in Master mode. 94 But it might be NOT compatible in old slaves.*/ 95 if ((USI_I2C_InitStruct->USI_I2CAddrMod == USI_I2C_ADDR_10BIT) || (USI_I2C_InitStruct->USI_I2CSpdMod == USI_I2C_HS_MODE) || (USI_I2C_InitStruct->USI_I2CMstStartB != 0)) 96 USI_I2C_InitStruct->USI_I2CMstReSTR = ENABLE; 97 98 USIx->I2C_CTRL = (USI_I2C_SLV_DISABLE | 99 (USI_I2C_InitStruct->USI_I2CSpdMod << 2) | 100 (USI_I2C_InitStruct->USI_I2CMstReSTR << 1) | 101 (USI_I2C_InitStruct->USI_I2CMaster)); 102 103 /* To set target addr.*/ 104 Specical = 0; 105 if ((USI_I2C_InitStruct->USI_I2CMstGC != 0) || (USI_I2C_InitStruct->USI_I2CMstStartB != 0)) 106 Specical = 1; 107 108 USIx->I2C_TAR = ((USI_I2C_InitStruct->USI_I2CAddrMod << 12) | 109 (Specical << 11) | 110 (USI_I2C_InitStruct->USI_I2CMstStartB << 10) | 111 (USI_I2C_InitStruct->USI_I2CAckAddr & USI_I2C_IC_TAR)); 112 113 /* To Set I2C clock*/ 114 USI_I2C_SetSpeed(USIx, USI_I2C_InitStruct->USI_I2CSpdMod, USI_I2C_InitStruct->USI_I2CClk, USI_I2C_InitStruct->USI_I2CIPClk); 115 } /*if (Master)*/ 116 else { 117 USIx->I2C_CTRL = (((USI_I2C_InitStruct->USI_I2CAckAddr <<12) & USI_I2C_SAR) | 118 (USI_I2C_InitStruct->USI_I2CAddrMod << 9) | 119 (USI_I2C_InitStruct->USI_I2CMaster << 8) | 120 (USI_I2C_InitStruct->USI_I2CSpdMod << 2) | 121 (USI_I2C_InitStruct->USI_I2CMaster)); 122 123 /* To set slave no ack and ack general call*/ 124 USIx->I2C_SLV_ACK_CTRL = USI_I2C_InitStruct->USI_I2CSlvNoAck |(USI_I2C_InitStruct->USI_I2CSlvAckGC << 1); 125 /* to set SDA setup time */ 126 USIx->I2C_SDA_TIMING = (USI_I2C_InitStruct->USI_I2CSlvSetup & USI_I2C_SDA_SETUP); 127 } 128 /* To set SDA hold time */ 129 USIx->I2C_SDA_TIMING = (((USI_I2C_InitStruct->USI_I2CSdaHd << 16) & USI_I2C_SDA_HOLD) | (USIx->I2C_SDA_TIMING & USI_I2C_SDA_SETUP)); 130 131 /* To set TX almost empty Level */ 132 USIx->TX_FIFO_CTRL= USI_I2C_InitStruct->USI_I2CTXTL; 133 134 /* To set RX almost full Level */ 135 USIx->RX_FIFO_CTRL = USI_I2C_InitStruct->USI_I2CRXTL; 136 137 /* To set IC_FILTER */ 138 USIx->I2C_DIG_FILTER= USI_I2C_InitStruct->USI_I2CFilter; 139 140 /* To set DMA TX/RX level */ 141 USIx->DMA_REQ_SIZE &= (~(USI_TX_DMA_BURST_SIZE | USI_RX_DMA_BURST_SIZE)); 142 USIx->DMA_REQ_SIZE |= (USI_I2C_InitStruct->USI_I2CTxDMARqLv | (USI_I2C_InitStruct->USI_I2CRxDMARqLv << 16)); 143 144 /*I2C Clear all interrupts first*/ 145 USI_I2C_ClearAllINT(USIx); 146 147 /*I2C Disable all interrupts first*/ 148 USI_I2C_INTConfig(USIx, 0xFFFFFFFF, DISABLE); 149 } 150 151 /** 152 * @brief Master sets I2C Speed Mode. 153 * @param USIx: where USIx can be USI0_DEV. 154 * @param SpdMd: I2C Speed Mode. 155 * This parameter can be one of the following values: 156 * @arg USI_I2C_SS_MODE: 157 * @arg USI_I2C_FS_MODE: 158 * @arg USI_I2C_HS_MODE: 159 * @param I2Clk: I2C Bus Clock, unit is KHz. 160 * This parameter can be one of the following values: 161 * @arg 50: 162 * @arg 100: 163 * @arg 400: 164 * @arg 1000: 165 * @arg 3000: 166 * @param IPClk: I2C IP Clock, unit is Hz. 167 * @retval None 168 */ USI_I2C_SetSpeed(USI_TypeDef * USIx,u32 SpdMd,u32 I2Clk,u32 I2CIPClk)169 void USI_I2C_SetSpeed(USI_TypeDef *USIx, u32 SpdMd, u32 I2Clk, u32 I2CIPClk) 170 { 171 u32 ICHLcnt; 172 u32 ICHtime; 173 u32 ICLtime; 174 u32 IPClkM = I2CIPClk /1000000; 175 176 /* Check the parameters */ 177 assert_param(IS_USI_I2C_ALL_PERIPH(USIx)); 178 179 switch (SpdMd) 180 { 181 case USI_I2C_SS_MODE: 182 { 183 ICHtime = ((1000000/I2Clk)*USI_I2C_SS_MIN_SCL_HTIME)/(USI_I2C_SS_MIN_SCL_HTIME+USI_I2C_SS_MIN_SCL_LTIME); 184 ICLtime = ((1000000/I2Clk)*USI_I2C_SS_MIN_SCL_LTIME)/(USI_I2C_SS_MIN_SCL_HTIME+USI_I2C_SS_MIN_SCL_LTIME); 185 186 ICHLcnt = (ICHtime * IPClkM)/1000; 187 USIx->I2C_SS_SCL_CNT = (ICHLcnt & USI_I2C_SS_SCL_HCNT) + 1; 188 ICHLcnt = (ICLtime * IPClkM)/1000; 189 USIx->I2C_SS_SCL_CNT |= (ICHLcnt << 16) & USI_I2C_SS_SCL_LCNT; 190 191 break; 192 } 193 194 case USI_I2C_FS_MODE: 195 { 196 ICHtime = ((1000000/I2Clk)*USI_I2C_FS_MIN_SCL_HTIME)/(USI_I2C_FS_MIN_SCL_HTIME+USI_I2C_FS_MIN_SCL_LTIME); 197 ICLtime = ((1000000/I2Clk)*USI_I2C_FS_MIN_SCL_LTIME)/(USI_I2C_FS_MIN_SCL_HTIME+USI_I2C_FS_MIN_SCL_LTIME); 198 199 ICHLcnt = (ICHtime * IPClkM)/1000; 200 if (ICHLcnt > IC_FS_SCL_HCNT_TRIM)/*this part is according to the fine-tune result*/ 201 ICHLcnt -= IC_FS_SCL_HCNT_TRIM; 202 USIx->I2C_FS_SCL_CNT = (ICHLcnt & USI_I2C_FS_SCL_HCNT) + 1; 203 204 ICHLcnt = (ICLtime * IPClkM)/1000; 205 if (ICHLcnt > IC_FS_SCL_LCNT_TRIM)/*this part is according to the fine-tune result*/ 206 ICHLcnt -= IC_FS_SCL_LCNT_TRIM; 207 USIx->I2C_FS_SCL_CNT |= (ICHLcnt << 16) & USI_I2C_FS_SCL_LCNT; 208 209 break; 210 } 211 212 case USI_I2C_HS_MODE: 213 { 214 /*set Fast mode count for Master code*/ 215 ICHtime = ((1000000/400)*USI_I2C_FS_MIN_SCL_HTIME)/(USI_I2C_FS_MIN_SCL_HTIME+USI_I2C_FS_MIN_SCL_LTIME); 216 ICLtime = ((1000000/400)*USI_I2C_FS_MIN_SCL_LTIME)/(USI_I2C_FS_MIN_SCL_HTIME+USI_I2C_FS_MIN_SCL_LTIME); 217 218 ICHLcnt = (ICHtime * IPClkM)/1000; 219 USIx->I2C_FS_SCL_CNT = ICHLcnt & USI_I2C_FS_SCL_HCNT; 220 221 ICHLcnt = (ICLtime * IPClkM)/1000; 222 USIx->I2C_FS_SCL_CNT |= (ICHLcnt << 16) & USI_I2C_FS_SCL_LCNT; 223 224 ICHtime = ((1000000/I2Clk)*USI_I2C_HS_MIN_SCL_HTIME_100)/(USI_I2C_HS_MIN_SCL_HTIME_100+USI_I2C_HS_MIN_SCL_LTIME_100); 225 ICLtime = ((1000000/I2Clk)*USI_I2C_HS_MIN_SCL_LTIME_100)/(USI_I2C_HS_MIN_SCL_HTIME_100+USI_I2C_HS_MIN_SCL_LTIME_100); 226 227 ICHLcnt = (ICHtime * IPClkM)/1000; 228 //if (ICHLcnt>8)/*this part is according to the fine-tune result*/ 229 // ICHLcnt -= 3; 230 USIx->I2C_HS_SCL_CNT = (ICHLcnt & USI_I2C_HS_SCL_HCNT)+1; 231 232 ICHLcnt = (ICLtime * IPClkM)/1000; 233 //if (ICHLcnt>6)/*this part is according to the fine-tune result*/ 234 // ICHLcnt -= 6; 235 USIx->I2C_HS_SCL_CNT |= (ICHLcnt << 16) & USI_I2C_HS_SCL_LCNT; 236 237 break; 238 } 239 240 default: 241 break; 242 } 243 } 244 245 /** 246 * @brief Master transmits the address byte to select the slave device. 247 * @param USIx: where USIx can be USI0_DEV. 248 * @param Address: specifies the slave address which will be transmitted 249 * @retval None. 250 */ USI_I2C_SetSlaveAddress(USI_TypeDef * USIx,u16 Address)251 void USI_I2C_SetSlaveAddress(USI_TypeDef *USIx, u16 Address) 252 { 253 u32 tar = USIx->I2C_TAR & ~(USI_I2C_IC_TAR); 254 255 /* Check the parameters */ 256 assert_param(IS_USI_I2C_ALL_PERIPH(USIx)); 257 258 /*set target address to generate start signal*/ 259 USIx->I2C_TAR = (Address & USI_I2C_IC_TAR) | tar; 260 } 261 262 /** 263 * @brief Checks whether the specified I2C flag is set or not. 264 * @param USIx: where USIx can be USI0_DEV. 265 * @param USI_I2C_FLAG: specifies the flag to check. 266 * This parameter can be one of the following values: 267 * @arg USI_I2C_BUS_ACTIVITY: BUS FSM Activity Status. 268 * @arg USI_I2C_SLV_ACTIVITY: Slave FSM Activity Status. 269 * @arg USI_I2C_MST_ACTIVITY: Master FSM Activity Status. 270 * @arg USI_I2C_ACTIVITY_COMB: I2C Activity Status, combine Master and Slave. 271 * @arg USI_I2C_ENABLE_COPY: i2c_enable copy to here 272 * @retval The new state of USI_I2C_FLAG: 273 * - 1: the specified I2C flag is set 274 * - 0: the specified I2C flag is not set 275 */ USI_I2C_CheckFlagState(USI_TypeDef * USIx,u32 USI_I2C_FLAG)276 u8 USI_I2C_CheckFlagState(USI_TypeDef *USIx, u32 USI_I2C_FLAG) 277 { 278 u8 bit_status = 0; 279 280 /* Check the parameters */ 281 assert_param(IS_USI_I2C_ALL_PERIPH(USIx)); 282 283 if((USIx->I2C_STATUS & USI_I2C_FLAG) != 0) 284 { 285 /* USI_I2C_FLAG is set */ 286 bit_status = 1; 287 } 288 289 /* Return the USI_I2C_FLAG status */ 290 return bit_status; 291 } 292 293 /** 294 * @brief Checks whether the specified I2C TXFIFO flag is set or not. 295 * @param USIx: where USIx can be USI0_DEV. 296 * @param USI_I2C_TXFIFO_FLAG: specifies the flag to check. 297 * This parameter can be one of the following values: 298 * @arg USI_TXFIFO_ALMOST_EMPTY_COPY: TX FIFO ALMOST EMPTY status 299 * @arg USI_TXFIFO_EMPTY: TX FIFO EMPTY status 300 * @arg USI_TXFIFO_FULL: TX FIFO FULL status 301 * @retval The new state of USI_I2C_TXFIFO_FLAG: 302 * - 1: the specified I2C flag is set 303 * - 0: the specified I2C flag is not set 304 */ USI_I2C_CheckTXFIFOState(USI_TypeDef * USIx,u32 USI_I2C_TXFIFO_FLAG)305 u8 USI_I2C_CheckTXFIFOState(USI_TypeDef *USIx, u32 USI_I2C_TXFIFO_FLAG) 306 { 307 u8 bit_status = 0; 308 309 /* Check the parameters */ 310 assert_param(IS_USI_I2C_ALL_PERIPH(USIx)); 311 312 if((USIx->TX_FIFO_STATUS & USI_I2C_TXFIFO_FLAG) != 0) 313 { 314 /* USI_I2C_TXFIFO_FLAG is set */ 315 bit_status = 1; 316 } 317 318 /* Return the USI_I2C_TXFIFO_FLAG status */ 319 return bit_status; 320 } 321 322 /** 323 * @brief Checks whether the specified I2C RXFIFO flag is set or not. 324 * @param USIx: where USIx can be USI0_DEV. 325 * @param USI_I2C_RXFIFO_FLAG: specifies the flag to check. 326 * This parameter can be one of the following values: 327 * @arg USI_RXFIFO_ALMOST_FULL_COPY: RX FIFO ALMOST EMPTY status 328 * @arg USI_RXFIFO_EMPTY: RX FIFO EMPTY status 329 * @arg USI_RXFIFO_FULL: RX FIFO FULL status 330 * @retval The new state of USI_I2C_RXFIFO_FLAG: 331 * - 1: the specified I2C flag is set 332 * - 0: the specified I2C flag is not set 333 */ USI_I2C_CheckRXFIFOState(USI_TypeDef * USIx,u32 USI_I2C_RXFIFO_FLAG)334 u8 USI_I2C_CheckRXFIFOState(USI_TypeDef *USIx, u32 USI_I2C_RXFIFO_FLAG) 335 { 336 u8 bit_status = 0; 337 338 /* Check the parameters */ 339 assert_param(IS_USI_I2C_ALL_PERIPH(USIx)); 340 341 if((USIx->RX_FIFO_STATUS & USI_I2C_RXFIFO_FLAG) != 0) 342 { 343 /* USI_I2C_RXFIFO_FLAG is set */ 344 bit_status = 1; 345 } 346 347 /* Return the USI_I2C_RXFIFO_FLAG status */ 348 return bit_status; 349 } 350 /** 351 * @brief ENABLE/DISABLE the I2C's interrupt bits.. 352 * @param USIx: where USIx can be USI0_DEV. 353 * @param USI_I2C_IT: specifies the USIx interrupt sources to be enabled or disabled. 354 * This parameter can be one or combinations of the following values: 355 * @arg USI_I2C_DMA_DONE_INTER_EN: I2C DMA Done Interrupt 356 * @arg USI_I2C_LP_WAKE_INTER_EN: I2C Low power wakeup Interrupt 357 * @arg USI_I2C_GEN_CALL_INTER_EN: General Call Interrupt 358 * @arg USI_I2C_START_DET_INTER_EN: Start or Restart Condition Interrupt 359 * @arg USI_I2C_STOP_DET_INTER_EN: Stop Condition Interrupt 360 * @arg USI_I2C_ACTIVITY_INTER_EN: I2C Activity Interrupt 361 * @arg USI_I2C_RX_DONE_INTER_EN: Slave Transmitter RX Done Interrupt 362 * @arg USI_I2C_TX_ABRT_INTER_EN: Transmit Abort Interrupt 363 * @arg USI_I2C_RD_REQ_INTER_EN: Read Request Interrupt 364 * @arg USI_RXFIFO_UNDERFLOW_INTR_EN: RX FIFO underflow Interrupt 365 * @arg USI_RXFIFO_OVERFLOW_INTR_EN: RX FIFO overflow Interrupt 366 * @arg USI_RXFIFO_ALMOST_FULL_INTR_EN: RX FIFO almost Full Interrupt 367 * @arg USI_TXFIFO_OVERFLOW_INTR_EN: TX FIFO overflow Interrupt 368 * @arg USI_TXFIFO_ALMOST_EMTY_INTR_EN: TX FIFO almost Empty Interrupt 369 * @param NewState: specifies the state of the interrupt. 370 * This parameter can be: ENABLE or DISABLE. 371 * @retval None 372 */ USI_I2C_INTConfig(USI_TypeDef * USIx,u32 USI_I2C_IT,u32 NewState)373 void USI_I2C_INTConfig(USI_TypeDef *USIx, u32 USI_I2C_IT, u32 NewState) 374 { 375 u32 TempVal = USIx->INTERRUPT_ENABLE; 376 377 /* Check the parameters */ 378 assert_param(IS_USI_I2C_ALL_PERIPH(USIx)); 379 380 if (NewState == ENABLE) { 381 TempVal |= USI_I2C_IT; 382 } else { 383 TempVal &= ~USI_I2C_IT; 384 } 385 386 USIx->INTERRUPT_ENABLE = TempVal; 387 } 388 389 /** 390 * @brief Clears the specified I2C interrupt pending bit. 391 * @param USIx: where USIx can be USI0_DEV. 392 * @param INTrBit: specifies the interrupt to be cleared. 393 * This parameter can be one of the following values: 394 * @arg USI_I2C_DMA_DONE_CLR: clear I2C DMA Done interrupt 395 * @arg USI_I2C_LP_WAKE_CLR: clear I2C Low Power wakeup Interrupt 396 * @arg USI_I2C_GEN_CALL_CLR: clear General Call Interrupt 397 * @arg USI_I2C_START_DET_CLR: clear Start or Restart Condition Interrupt 398 * @arg USI_I2C_STOP_DET_CLR: clear Stop Condition Interrupt 399 * @arg USI_I2C_ACTIVITY_CLR: clear I2C Activity Interrupt 400 * @arg USI_I2C_RX_DONE_CLR: clear Slave Transmitter RX Done Interrupt 401 * @arg USI_I2C_TX_ABRT_CLR: clear Transmit Abort Interrupt 402 * @arg USI_I2C_RD_REQ_CLR: clear Read Request Interrupt 403 * @arg USI_RXFIFO_UNDERFLOW_CLR: clear RX FIFO underflow Interrupt 404 * @arg USI_RXFIFO_OVERFLOW_CLR: clear RX FIFO overflow Interrupt 405 * @arg USI_TXFIFO_OVERFLOW_CLR: clear TX FIFO overflow Interrupt 406 * @note USI_TXFIFO_ALMOST_EMTY_INTS is automatically cleared by hardware when the buffer 407 * level goes above the TX_FIFO_CTRL threshold. 408 * USI_RXFIFO_ALMOST_FULL_INTS is automatically cleared by hardware when the buffer 409 * level goes below the RX_FIFO_CTRL threshold. 410 * @retval None 411 */ USI_I2C_ClearINT(USI_TypeDef * USIx,u32 INTrBit)412 void USI_I2C_ClearINT(USI_TypeDef *USIx, u32 INTrBit) 413 { 414 /* Check the parameters */ 415 assert_param(IS_USI_I2C_ALL_PERIPH(USIx)); 416 417 /*write 1 to clear all interrupts*/ 418 USIx->INTERRUPT_STATUS_CLR = INTrBit; 419 } 420 421 /** 422 * @brief Clears all of the I2C interrupt pending bit. 423 * @param USIx: where USIx can be USI0_DEV. 424 * @retval None 425 */ USI_I2C_ClearAllINT(USI_TypeDef * USIx)426 void USI_I2C_ClearAllINT(USI_TypeDef *USIx) 427 { 428 /* Check the parameters */ 429 assert_param(IS_USI_I2C_ALL_PERIPH(USIx)); 430 431 /*write 1 to clear all interrupts*/ 432 USIx->INTERRUPT_ALL_CLR = USI_INT_ALL_CLEAR; 433 } 434 435 /** 436 * @brief Get I2C Raw Interrupt Status. 437 * @param USIx: where USIx can be USI0_DEV. 438 * @retval raw interrupt status 439 */ USI_I2C_GetRawINT(USI_TypeDef * USIx)440 u32 USI_I2C_GetRawINT(USI_TypeDef *USIx) 441 { 442 /* Check the parameters */ 443 assert_param(IS_USI_I2C_ALL_PERIPH(USIx)); 444 445 return USIx->RAW_INTERRUPT_STATUS; 446 } 447 448 /** 449 * @brief Get I2C interrupt status. 450 * @param USIx: where USIx can be USI0_DEV. 451 * @retval interrupt status 452 */ USI_I2C_GetINT(USI_TypeDef * USIx)453 u32 USI_I2C_GetINT(USI_TypeDef *USIx) 454 { 455 /* Check the parameters */ 456 assert_param(IS_USI_I2C_ALL_PERIPH(USIx)); 457 458 return USIx->INTERRUPT_STATUS; 459 } 460 461 /** 462 * @brief Master sends single byte through the USIx peripheral according to the set of the upper layer. 463 * @param USIx: where USIx can be USI0_DEV. 464 * @param pBuf: point to the data that to be write. 465 * @param I2CCmd: specifies whether a read from FIFO or a write to FIFO is performed. 466 * @param I2CStop: specifies whether a STOP is issued after the byte is sent or received. 467 * @param I2CReSTR: specifies whether a RESTART is issued after the byte is sent or received. 468 * @retval None 469 */ USI_I2C_MasterSendNullData(USI_TypeDef * USIx,u8 * pBuf,u8 I2CCmd,u8 I2CStop,u8 I2CReSTR)470 void USI_I2C_MasterSendNullData(USI_TypeDef *USIx, u8* pBuf, u8 I2CCmd, u8 I2CStop, u8 I2CReSTR) 471 { 472 /* Check the parameters */ 473 assert_param(IS_USI_I2C_ALL_PERIPH(USIx)); 474 475 USIx->TX_FIFO_WRITE = *(pBuf) | 476 (1 << 11) | 477 (I2CReSTR << 10) | 478 (I2CCmd << 8) | 479 (I2CStop << 9); 480 } 481 482 /** 483 * @brief Master sends single byte through the USIx peripheral according to the set of the upper layer. 484 * @param USIx: where USIx can be USI0_DEV. 485 * @param pBuf: point to the data that to be write. 486 * @param I2CCmd: specifies whether a read from FIFO or a write to FIFO is performed. 487 * @param I2CStop: specifies whether a STOP is issued after the byte is sent or received. 488 * @param I2CReSTR: specifies whether a RESTART is issued after the byte is sent or received. 489 * @retval None 490 */ USI_I2C_MasterSend(USI_TypeDef * USIx,u8 * pBuf,u8 I2CCmd,u8 I2CStop,u8 I2CReSTR)491 void USI_I2C_MasterSend(USI_TypeDef *USIx, u8* pBuf, u8 I2CCmd, u8 I2CStop, u8 I2CReSTR) 492 { 493 /* Check the parameters */ 494 assert_param(IS_USI_I2C_ALL_PERIPH(USIx)); 495 496 USIx->TX_FIFO_WRITE = *(pBuf) | 497 (I2CReSTR << 10) | 498 (I2CCmd << 8) | 499 (I2CStop << 9); 500 } 501 502 /** 503 * @brief Slave sends single byte through the USIx peripheral after receiving read request of Master. 504 * @param USIx: where USIx can be USI0_DEV. 505 * @param Data: data to be transmitted. 506 * @param StopState: specifies whether a STOP is issued after the byte is sent. 507 * @retval None 508 */ USI_I2C_SlaveSend(USI_TypeDef * USIx,u8 Data)509 void USI_I2C_SlaveSend(USI_TypeDef *USIx, u8 Data) 510 { 511 /* Check the parameters */ 512 assert_param(IS_USI_I2C_ALL_PERIPH(USIx)); 513 514 USIx->TX_FIFO_WRITE = Data; 515 } 516 517 /** 518 * @brief Returns the most recent received data by the USIx peripheral. 519 * @param USIx: where USIx can be USI0_DEV. 520 * @retval The value of the received data. 521 */ USI_I2C_ReceiveData(USI_TypeDef * USIx)522 u8 USI_I2C_ReceiveData(USI_TypeDef *USIx) 523 { 524 /* Check the parameters */ 525 assert_param(IS_USI_I2C_ALL_PERIPH(USIx)); 526 527 /* Return the data in the DR register */ 528 return (u8)USIx->RX_FIFO_READ; 529 } 530 531 /** 532 * @brief Send data with special length in master mode through the USIx peripheral. 533 * @param USIx: where USIx can be USI0_DEV. 534 * @param pBuf: point to the data to be transmitted. 535 * @param len: the length of data that to be transmitted. 536 * @note deal with condition that master send address or data while slave no ack 537 * @retval The length of data that have been sent to tx fifo 538 */ USI_I2C_MasterWrite(USI_TypeDef * USIx,u8 * pBuf,u8 len)539 u8 USI_I2C_MasterWrite(USI_TypeDef *USIx, u8* pBuf, u8 len) 540 { 541 u8 cnt = 0; 542 543 /* Check the parameters */ 544 assert_param(IS_USI_I2C_ALL_PERIPH(USIx)); 545 546 /* Write in the DR register the data to be sent */ 547 for(cnt = 0; cnt < len; cnt++) 548 { 549 while((USI_I2C_CheckTXFIFOState(USIx, USI_TXFIFO_ALMOST_EMPTY_COPY)) == 0); 550 551 if(cnt >= len - 1) 552 { 553 /*generate stop signal*/ 554 USIx->TX_FIFO_WRITE = (*pBuf++) | (1 << 9); 555 } 556 else 557 { 558 USIx->TX_FIFO_WRITE = (*pBuf++); 559 } 560 561 while((USI_I2C_CheckTXFIFOState(USIx, USI_TXFIFO_EMPTY)) == 0) { 562 if(USI_I2C_GetRawINT(USIx) & USI_I2C_TX_ABRT_RSTS) { 563 USI_I2C_ClearAllINT(USIx); 564 return cnt; 565 } 566 } 567 } 568 569 return cnt; 570 } 571 572 /** 573 * @brief Read data with special length in master mode through the USIx peripheral under in-house IP. 574 * @param USIx: where USIx can be USI0_DEV. 575 * @param pBuf: point to the buffer to hold the received data. 576 * @param len: the length of data that to be received. 577 * @retval The length of data that have received from rx fifo 578 */ USI_I2C_MasterRead(USI_TypeDef * USIx,u8 * pBuf,u8 len)579 u8 USI_I2C_MasterRead(USI_TypeDef *USIx, u8* pBuf, u8 len) 580 { 581 u8 cnt = 0; 582 583 /* Check the parameters */ 584 assert_param(IS_USI_I2C_ALL_PERIPH(USIx)); 585 586 /* read in the DR register the data to be received */ 587 for(cnt = 0; cnt < len; cnt++) 588 { 589 if(cnt >= len - 1) 590 { 591 /* generate stop singal */ 592 USIx->TX_FIFO_WRITE = 0x0003 << 8; 593 } 594 else 595 { 596 USIx->TX_FIFO_WRITE = 0x0001 << 8; 597 } 598 599 /* wait for USI_I2C_FLAG_RFNE flag */ 600 while((USI_I2C_CheckRXFIFOState(USIx, USI_RXFIFO_EMPTY)) == 1) { 601 if(USI_I2C_GetRawINT(USIx) & USI_I2C_TX_ABRT_RSTS) { 602 USI_I2C_ClearAllINT(USIx); 603 return cnt; 604 } 605 } 606 *pBuf++ = (u8)USIx->RX_FIFO_READ; 607 } 608 609 return cnt; 610 } 611 612 /** 613 * @brief Send data with special length in slave mode through the USIx peripheral. 614 * @param USIx: where USIx can be USI0_DEV. 615 * @param pBuf: point to the data to be transmitted. 616 * @param len: the length of data that to be transmitted. 617 * @retval None 618 */ USI_I2C_SlaveWrite(USI_TypeDef * USIx,u8 * pBuf,u8 len)619 void USI_I2C_SlaveWrite(USI_TypeDef *USIx, u8* pBuf, u8 len) 620 { 621 u8 cnt = 0; 622 623 /* Check the parameters */ 624 assert_param(IS_USI_I2C_ALL_PERIPH(USIx)); 625 626 for(cnt = 0; cnt < len; cnt++) { 627 /* Check I2C RD Request flag */ 628 while((USI_I2C_GetRawINT(USIx) & USI_I2C_RD_REQ_RSTS) == 0); 629 630 if (USI_I2C_SLAVEWRITE_PATCH) { 631 USIx->INTERRUPT_STATUS_CLR = USI_I2C_RD_REQ_CLR; 632 } 633 /* Check I2C TX FIFO status */ 634 while((USI_I2C_CheckTXFIFOState(USIx, USI_TXFIFO_ALMOST_EMPTY_COPY)) == 0); 635 636 USIx->TX_FIFO_WRITE = (*pBuf++); 637 } 638 while((USI_I2C_CheckTXFIFOState(USIx, USI_TXFIFO_EMPTY)) == 0); 639 } 640 641 /** 642 * @brief Read data with special length in slave mode through the USIx peripheral. 643 * @param USIx: where USIx can be USI0_DEV. 644 * @param pBuf: point to the buffer to hold the received data. 645 * @param len: the length of data that to be received. 646 * @retval None 647 */ USI_I2C_SlaveRead(USI_TypeDef * USIx,u8 * pBuf,u8 len)648 void USI_I2C_SlaveRead(USI_TypeDef *USIx, u8* pBuf, u8 len) 649 { 650 u8 cnt = 0; 651 652 /* Check the parameters */ 653 assert_param(IS_USI_I2C_ALL_PERIPH(USIx)); 654 655 for(cnt = 0; cnt < len; cnt++) { 656 /* Check I2C RX FIFO status */ 657 while((USI_I2C_CheckRXFIFOState(USIx, USI_RXFIFO_EMPTY)) == 1); 658 659 *pBuf++ = (u8)USIx->RX_FIFO_READ; 660 } 661 } 662 /** 663 * @brief Sends data and read data in master mode through the USIx peripheral. 664 * @param USIx: where USIx can be USI0_DEV to select the I2C peripheral. 665 * @param pWriteBuf: Byte to be transmitted. 666 * @param Writelen: Byte number to be transmitted (the length should less then buffer depth for A CUT). 667 * @param pReadBuf: Byte to be received. 668 * @param Readlen: Byte number to be received. 669 * @retval None 670 */ USI_I2C_MasterRepeatRead(USI_TypeDef * USIx,u8 * pWriteBuf,u8 Writelen,u8 * pReadBuf,u8 Readlen)671 void USI_I2C_MasterRepeatRead(USI_TypeDef* USIx, u8* pWriteBuf, u8 Writelen, u8* pReadBuf, u8 Readlen) 672 { 673 674 u8 cnt = 0; 675 676 /* Check the parameters */ 677 assert_param(IS_USI_I2C_ALL_PERIPH(USIx)); 678 679 /* write in the DR register the data to be sent */ 680 for(cnt = 0; cnt < Writelen; cnt++) 681 { 682 while((USI_I2C_CheckTXFIFOState(USIx, USI_TXFIFO_ALMOST_EMPTY_COPY)) == 0); 683 684 if(cnt >= Writelen - 1) 685 { 686 /*generate restart signal*/ 687 USIx->TX_FIFO_WRITE = (*pWriteBuf++) | (1 << 10); 688 } 689 else 690 { 691 USIx->TX_FIFO_WRITE = (*pWriteBuf++); 692 } 693 } 694 695 /*Wait I2C TX FIFO not full*/ 696 while((USI_I2C_CheckTXFIFOState(USIx, USI_TXFIFO_ALMOST_EMPTY_COPY)) == 0); 697 698 USI_I2C_MasterRead(USIx, pReadBuf, Readlen); 699 } 700 701 /** 702 * @brief Enables or disables the specified I2C peripheral, this is one bit register. 703 * @param USIx: where USIx can be USI0_DEV. 704 * @param NewState: new state of the USIx peripheral. 705 * This parameter can be: ENABLE or DISABLE. 706 * @retval None 707 */ USI_I2C_Cmd(USI_TypeDef * USIx,u8 NewState)708 void USI_I2C_Cmd(USI_TypeDef *USIx, u8 NewState) 709 { 710 /* Check the parameters */ 711 assert_param(IS_USI_I2C_ALL_PERIPH(USIx)); 712 713 if (NewState != DISABLE) 714 { 715 /* Enable the selected I2C peripheral */ 716 USIx->I2C_ENABLE |= USI_I2C_ENABLE; 717 } 718 else 719 { 720 /* Disable the selected I2C peripheral */ 721 USIx->I2C_ENABLE &= ~USI_I2C_ENABLE; 722 } 723 } 724 725 /** 726 * @brief Enable I2C Tx or Rx DMA. 727 * @param USIx: where USIx can be USI0_DEV. 728 * @param DmaCtrl: control Transmit DMA Enable or Receive DMA Enable 729 * This parameter can be one of the following values: 730 * @arg USI_TX_DMA_ENABLE: 731 * @arg USI_RX_DMA_ENABLE: 732 * @param NewState: the new state of the DMA function. 733 * This parameter can be: ENABLE or DISABLE. 734 * @retval None 735 */ USI_I2C_DMAControl(USI_TypeDef * USIx,u32 DmaCtrl,u8 NewState)736 void USI_I2C_DMAControl(USI_TypeDef *USIx, u32 DmaCtrl, u8 NewState) 737 { 738 u32 I2CDMAEn = USIx->DMA_ENABLE; 739 740 /* Check the parameters */ 741 assert_param(IS_USI_I2C_ALL_PERIPH(USIx)); 742 743 if (NewState == ENABLE) 744 I2CDMAEn |= DmaCtrl; 745 else 746 I2CDMAEn &= ~DmaCtrl; 747 748 USIx->DMA_ENABLE = I2CDMAEn; 749 } 750 751 /** 752 * @brief Initializes the USIx Control Register DMA mode. 753 * @param USIx: where USIx can be USI0_DEV. 754 * @param USI_I2C_DmaCmd: Command to control the read or write operation and 755 * the action after the last data transferred. 756 * This parameter can be one or combinations of the following values: 757 * @arg USI_I2C_DMODE_RESTART 758 * @arg USI_I2C_DMODE_STOP 759 * @arg USI_I2C_DMODE_WRITE_CMD 760 * @arg USI_I2C_DMODE_READ_CMD 761 * @arg USI_I2C_DMODE_ENABLE 762 * @param USI_I2C_DmaBLen: length of data. 763 * This parameter must be set to a value in the 0-0xFFFF range. 764 * @retval None 765 */ USI_I2C_DmaRegModeConfig(USI_TypeDef * USIx,u32 USI_I2C_DmaCmd,u32 USI_I2C_DmaBLen)766 void USI_I2C_DmaRegModeConfig(USI_TypeDef *USIx, u32 USI_I2C_DmaCmd, u32 USI_I2C_DmaBLen) 767 { 768 /* Check the parameters */ 769 assert_param(IS_USI_I2C_ALL_PERIPH(USIx)); 770 assert_param(IS_USI_I2C_DMA_DATA_LEN(USI_I2C_DmaBLen)); 771 772 USIx->I2C_DMA_CMD = ((USI_I2C_DmaBLen << 16) | USI_I2C_DMA_CTRL_REG_MODE | USI_I2C_DmaCmd); 773 } 774 775 /** 776 * @brief Init and Enable I2C TX GDMA. 777 * @param Index: 0 . 778 * @param GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that contains 779 * the configuration information for the GDMA peripheral. 780 * @param CallbackData: GDMA callback data. 781 * @param CallbackFunc: GDMA callback function. 782 * @param pTxBuf: Tx Buffer. 783 * @param TxCount: Tx Count. 784 * @retval TRUE/FLASE 785 * @note can not support legacy DMA mode 786 */ USI_I2C_TXGDMA_Init(u8 Index,GDMA_InitTypeDef * GDMA_InitStruct,void * CallbackData,IRQ_FUN CallbackFunc,u8 * pTxBuf,int TxCount)787 BOOL USI_I2C_TXGDMA_Init( 788 u8 Index, 789 GDMA_InitTypeDef *GDMA_InitStruct, 790 void *CallbackData, 791 IRQ_FUN CallbackFunc, 792 u8 *pTxBuf, 793 int TxCount 794 ) 795 { 796 u8 GdmaChnl; 797 798 assert_param(GDMA_InitStruct != NULL); 799 800 GdmaChnl = GDMA_ChnlAlloc(0, (IRQ_FUN)CallbackFunc, (u32)CallbackData, 12); 801 if (GdmaChnl == 0xFF) { 802 /* No Available DMA channel */ 803 return _FALSE; 804 } 805 806 _memset((void *)GDMA_InitStruct, 0, sizeof(GDMA_InitTypeDef)); 807 808 GDMA_InitStruct->MuliBlockCunt = 0; 809 GDMA_InitStruct->MaxMuliBlock = 1; 810 811 GDMA_InitStruct->GDMA_DIR = TTFCMemToPeri; 812 GDMA_InitStruct->GDMA_DstHandshakeInterface = USI_DEV_TABLE[Index].Tx_HandshakeInterface; 813 GDMA_InitStruct->GDMA_DstAddr = (u32)&USI_DEV_TABLE[Index].USIx->TX_FIFO_WRITE; 814 GDMA_InitStruct->GDMA_Index = 0; 815 GDMA_InitStruct->GDMA_ChNum = GdmaChnl; 816 GDMA_InitStruct->GDMA_IsrType = (BlockType|TransferType|ErrType); 817 818 GDMA_InitStruct->GDMA_DstMsize = MsizeFour; 819 GDMA_InitStruct->GDMA_DstDataWidth = TrWidthOneByte; 820 GDMA_InitStruct->GDMA_DstInc = NoChange; 821 GDMA_InitStruct->GDMA_SrcInc = IncType; 822 823 if (((TxCount & 0x03)==0) && (((u32)(pTxBuf) & 0x03)==0)) { 824 /* 4-bytes aligned, move 4 bytes each transfer */ 825 GDMA_InitStruct->GDMA_SrcMsize = MsizeOne; 826 GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthFourBytes; 827 GDMA_InitStruct->GDMA_BlockSize = TxCount >> 2; 828 } else { 829 /* move 1 byte each transfer */ 830 GDMA_InitStruct->GDMA_SrcMsize = MsizeFour; 831 GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthOneByte; 832 GDMA_InitStruct->GDMA_BlockSize = TxCount; 833 } 834 835 assert_param(GDMA_InitStruct->GDMA_BlockSize <= 4096); 836 837 GDMA_InitStruct->GDMA_SrcAddr = (u32)(pTxBuf); 838 839 GDMA_Init(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, GDMA_InitStruct); 840 GDMA_Cmd(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, ENABLE); 841 842 return _TRUE; 843 } 844 845 /** 846 * @brief Init and Enable I2C RX GDMA. 847 * @param I2C: 0. 848 * @param GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that contains 849 * the configuration information for the GDMA peripheral. 850 * @param CallbackData: GDMA callback data. 851 * @param CallbackFunc: GDMA callback function. 852 * @param pRxBuf: Rx Buffer. 853 * @param RxCount: Rx Count. 854 * @retval TRUE/FLASE 855 * @note support Master or Slave RXDMA 856 */ USI_I2C_RXGDMA_Init(u8 Index,GDMA_InitTypeDef * GDMA_InitStruct,void * CallbackData,IRQ_FUN CallbackFunc,u8 * pRxBuf,int RxCount)857 BOOL USI_I2C_RXGDMA_Init( 858 u8 Index, 859 GDMA_InitTypeDef *GDMA_InitStruct, 860 void *CallbackData, 861 IRQ_FUN CallbackFunc, 862 u8 *pRxBuf, 863 int RxCount 864 ) 865 { 866 u8 GdmaChnl; 867 868 assert_param(GDMA_InitStruct != NULL); 869 870 GdmaChnl = GDMA_ChnlAlloc(0, (IRQ_FUN)CallbackFunc, (u32)CallbackData, 12); 871 if (GdmaChnl == 0xFF) { 872 /* No Available DMA channel */ 873 return _FALSE; 874 } 875 876 _memset((void *)GDMA_InitStruct, 0, sizeof(GDMA_InitTypeDef)); 877 878 GDMA_InitStruct->GDMA_DIR = TTFCPeriToMem; 879 GDMA_InitStruct->GDMA_ReloadSrc = 0; 880 GDMA_InitStruct->GDMA_SrcHandshakeInterface = USI_DEV_TABLE[Index].Rx_HandshakeInterface; 881 GDMA_InitStruct->GDMA_SrcAddr = (u32)&USI_DEV_TABLE[Index].USIx->RX_FIFO_READ; 882 GDMA_InitStruct->GDMA_Index = 0; 883 GDMA_InitStruct->GDMA_ChNum = GdmaChnl; 884 GDMA_InitStruct->GDMA_IsrType = (BlockType|TransferType|ErrType); 885 GDMA_InitStruct->GDMA_SrcMsize = MsizeFour; 886 GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthOneByte; 887 GDMA_InitStruct->GDMA_DstInc = IncType; 888 GDMA_InitStruct->GDMA_SrcInc = NoChange; 889 890 if (((u32)(pRxBuf) & 0x03)==0) { 891 /* 4-bytes aligned, move 4 bytes each DMA transaction */ 892 GDMA_InitStruct->GDMA_DstMsize = MsizeOne; 893 GDMA_InitStruct->GDMA_DstDataWidth = TrWidthFourBytes; 894 } else { 895 /* move 1 byte each DMA transaction */ 896 GDMA_InitStruct->GDMA_DstMsize = MsizeFour; 897 GDMA_InitStruct->GDMA_DstDataWidth = TrWidthOneByte; 898 } 899 900 GDMA_InitStruct->GDMA_BlockSize = RxCount; 901 GDMA_InitStruct->GDMA_DstAddr = (u32)(pRxBuf); 902 903 assert_param(GDMA_InitStruct->GDMA_BlockSize <= 4096); 904 905 /* multi block close */ 906 GDMA_InitStruct->MuliBlockCunt = 0; 907 GDMA_InitStruct->GDMA_ReloadSrc = 0; 908 GDMA_InitStruct->MaxMuliBlock = 1; 909 910 GDMA_Init(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, GDMA_InitStruct); 911 GDMA_Cmd(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, ENABLE); 912 913 return _TRUE; 914 } 915 916 /** 917 * @brief Clock-gated I2C clock domain for address matching interrupts wake up. 918 * @param USIx: where USIx can be USI0_DEV. 919 * @param NewState: the new state of the Rx Path. 920 * This parameter can be: ENABLE or DISABLE. 921 * @retval None 922 */ USI_I2C_Sleep_Cmd(USI_TypeDef * USIx,u32 NewStatus)923 void USI_I2C_Sleep_Cmd(USI_TypeDef *USIx, u32 NewStatus) 924 { 925 /* Check the parameters */ 926 assert_param(IS_USI_I2C_ALL_PERIPH(USIx)); 927 928 if (NewStatus != DISABLE) { 929 USI_I2C_INTConfig(USIx, USI_I2C_LP_WAKE_INTER_EN, ENABLE); 930 931 USIx->I2C_DIG_FILTER &= ~ USI_I2C_DIG_FLTR_SEL; 932 USIx->I2C_CTRL &= ~(USI_I2C_SLV_DISABLE); 933 USIx->I2C_ENABLE |= USI_I2C_SLEEP; 934 } else { 935 USI_I2C_INTConfig(USIx, USI_I2C_LP_WAKE_INTER_EN, DISABLE); 936 937 USIx->I2C_DIG_FILTER |= USI_I2C_DIG_FLTR_SEL; 938 USIx->I2C_ENABLE &= ~USI_I2C_SLEEP; 939 } 940 } 941 942 /** 943 * @brief Wake up clock domain of Clock-gated I2C after address matching interrupts. 944 * @param USIx: where USIx can be USI0_DEV. 945 * @retval None 946 */ USI_I2C_WakeUp(USI_TypeDef * USIx)947 void USI_I2C_WakeUp(USI_TypeDef *USIx) 948 { 949 /* Check the parameters */ 950 assert_param(IS_USI_I2C_ALL_PERIPH(USIx)); 951 952 USI_I2C_ClearINT(USIx, USI_I2C_LP_WAKE_CLR); 953 954 USI_I2C_Sleep_Cmd(USIx, DISABLE); 955 } 956 957 /******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/ 958 959