1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2019-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Description: 8 * SoC-level memory map. 9 */ 10 11 #ifndef SYSTEM_MMAP_H 12 #define SYSTEM_MMAP_H 13 14 #include <stdint.h> 15 16 #define PERIPHERAL_BASE UINT32_C(0x44000000) 17 #define EXTERNAL_RAM_BASE UINT32_C(0x60000000) 18 #define EXTERNAL_DEV_BASE UINT32_C(0xA0000000) 19 #define PPB_BASE_INTERNAL UINT32_C(0xE0000000) 20 #define PPB_BASE_EXTERNAL UINT32_C(0xE0040000) 21 #define VENDOR_EXTENSION_BASE UINT32_C(0xE0100000) 22 23 #define TRUSTED_RAM_BASE (EXTERNAL_DEV_BASE + 0x04000000) 24 #define SSC_BASE (EXTERNAL_DEV_BASE + 0x2A420000) 25 #define DMC400_BASE (EXTERNAL_DEV_BASE + 0x2B0A0000) 26 #define NONTRUSTED_RAM_BASE (EXTERNAL_DEV_BASE + 0x2E000000) 27 #define WDOG_BASE (PERIPHERAL_BASE + 0x6000) 28 #define CTI_BASE (PPB_BASE_EXTERNAL + 0x4000) 29 #define CONFIG_BASE (PERIPHERAL_BASE + 0x10000) 30 31 #define REFCLK_CNTCONTROL_BASE (EXTERNAL_DEV_BASE + 0x2A430000) 32 #define REFCLK_CNTCTL_BASE (PERIPHERAL_BASE) 33 #define REFCLK_CNTBASE0_BASE (PERIPHERAL_BASE + 0x1000) 34 #define S32K_CNTCONTROL_BASE (PERIPHERAL_BASE + 0x7000) 35 #define S32K_CNTCTL_BASE (PERIPHERAL_BASE + 0x8000) 36 #define S32K_CNTBASE0_BASE (PERIPHERAL_BASE + 0x9000) 37 #define CS_CNTCONTROL_BASE (PERIPHERAL_BASE + 0xA000) 38 39 #define PPU_BASE (PERIPHERAL_BASE + 0x20000) 40 #define PPU_BIG_CPU0_BASE (PPU_BASE + 0x0000) 41 #define PPU_BIG_CPU1_BASE (PPU_BASE + 0x0020) 42 #define PPU_BIG_SSTOP_BASE (PPU_BASE + 0x0080) 43 #define PPU_LITTLE_CPU0_BASE (PPU_BASE + 0x0100) 44 #define PPU_LITTLE_CPU1_BASE (PPU_BASE + 0x0120) 45 #define PPU_LITTLE_CPU2_BASE (PPU_BASE + 0x0140) 46 #define PPU_LITTLE_CPU3_BASE (PPU_BASE + 0x0160) 47 #define PPU_LITTLE_SSTOP_BASE (PPU_BASE + 0x0180) 48 #define PPU_GPUTOP_BASE (PPU_BASE + 0x0200) 49 #define PPU_SYSTOP_BASE (PPU_BASE + 0x0300) 50 #define PPU_DBGSYS_BASE (PPU_BASE + 0x0320) 51 #define PPU_ID_BASE (PPU_BASE + 0x0FD0) 52 53 #define MHU_BASE (EXTERNAL_DEV_BASE + 0x2B1F0000) 54 #define MHU_SCP_INTR_L_BASE (MHU_BASE + 0x0000) 55 #define MHU_SCP_INTR_H_BASE (MHU_BASE + 0x0020) 56 #define MHU_CPU_INTR_L_BASE (MHU_BASE + 0x0100) 57 #define MHU_CPU_INTR_H_BASE (MHU_BASE + 0x0120) 58 #define MHU_SCP_INTR_S_BASE (MHU_BASE + 0x0200) 59 #define MHU_CPU_INTR_S_BASE (MHU_BASE + 0x0300) 60 61 #define SCS_DEMCR_ADDR UINT32_C(0xE000EDFC) 62 #define DWT_CTRL_ADDR UINT32_C(0xE0001000) 63 #define DWT_CYCCNT UINT32_C(0xE0001004) 64 65 #endif /* SYSTEM_MMAP_H */ 66