1 /**
2   ******************************************************************************
3   * @file    rtl8721d_wdg.h
4   * @author
5   * @version V1.0.0
6   * @date    2016-05-17
7   * @brief   This file contains all the functions prototypes for the WDG firmware
8   *          library.
9   ******************************************************************************
10   * @attention
11   *
12   * This module is a confidential and proprietary property of RealTek and
13   * possession or use of this module requires written permission of RealTek.
14   *
15   * Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
16   ******************************************************************************
17   */
18 
19 #ifndef _RTL8721D_WDG_H_
20 #define _RTL8721D_WDG_H_
21 
22 /** @addtogroup AmebaD_Periph_Driver
23   * @{
24   */
25 
26 /** @defgroup WDG
27   * @brief WDG driver modules
28   * @{
29   */
30 
31 /** @addtogroup WDG
32   * @verbatim
33   *****************************************************************************************
34   * Introduction
35   *****************************************************************************************
36   * WDG:
37   * 	- Base Address: VENDOR_REG_BASE
38   * 	- Timer clk: SDM 32k
39   * 	- Generates MCU reset or WDG interrupt on expiry of a programmed time period,
40   * 	  unless the program refreshes the watchdog
41   * 	- IRQ: WDG_IRQ
42   *
43   *****************************************************************************************
44   * WDG Register
45   *****************************************************************************************
46   *  [31]		 R/W1C	 Wdt_to 			 Watch dog timer timeout. 1 cycle pulse
47   *  [30]		 R/W	 Wdt_mode			 1: Reset system, 0: Interrupt CPU
48   *  [29]		 R/W	 RSVD
49   *  [28:25]	 R/W	 Cnt_limit			 0: 0x001
50   * 										 1: 0x003
51   * 										 2: 0x007
52   * 										 3: 0x00F
53   * 										 4: 0x01F
54   * 										 5: 0x03F
55   * 										 6: 0x07F
56   * 										 7: 0x0FF
57   * 										 8: 0x1FF
58   * 										 9: 0x3FF
59   * 										 10: 0x7FF
60   * 										 11~15: 0xFFF
61   *  [24]		 W		 Wdt_clear			 Write 1 to clear timer
62   *  [23:17]	 R/W	 RSVD
63   *  [16]		 R/W	 Wdt_en_byte			 Set 0x1 to enable watch dog timer
64   *  [15:0] 	 R/W	 BIT_VNDR_divfactor  "Dividing factor.Watch dog timer is count with 32.768KHz/(divfactor+1).
65   * 										 Minimum dividing factor is 1."
66   *
67   *****************************************************************************************
68   * How to use WGD
69   *****************************************************************************************
70   *      To use WDG peripheral, the following steps are mandatory:
71   *
72   *      1.  Get count ID and divisor factor according to WDG timeout period using
73   *			WDG_Scalar(WDG_TEST_TIMEOUT, &CountProcess, &DivFacProcess);
74   *
75   *      2. Configure WDG with the corresponding configuration.
76   *			WDG_Init(&WDG_InitStruct)
77   *
78   *      3. Activate the WDG peripheral:
79   			WDG_Cmd(ENABLE).
80   *
81   *      @note	In interrupt mode, call WDG_IrqInit() function after WDG_Init()
82   *
83   *      @note	WDG_Refresh() function is used to clear timer, if call this function before timeout period,
84   *			then MCU reset or WDG interrupt won't generate
85   *
86   *****************************************************************************************
87   * @endverbatim
88   */
89 
90 /* Exported types ------------------------------------------------------------*/
91 
92 /** @defgroup WDG_Exported_Types WDG Exported Types
93   * @{
94   */
95 
96 /**
97   * @brief  WDG Init structure definition
98   */
99 typedef struct
100 {
101 	u32 CountProcess; 		/*!< WDG parameter get from WDG_Scalar, Specifies count id of WDG
102 								This parameter must be set to a value in the 0-11 range */
103 
104 	u32 DivFacProcess; 	/*!< WDG parameter get from WDG_Scalar, Specifies WDG timeout count divisor factor
105 								This parameter must be set to a value in the 1-65535 range */
106 
107 	u32 RstAllPERI;		/*!< WDG parameter, Specifies WDG reset all the PERIs in HS or not
108 								This parameter must be set to a value of 0 or 1 */
109 } WDG_InitTypeDef;
110 /**
111   * @}
112   */
113 
114 /** @defgroup WDG_Exported_Functions WDG Exported Functions
115   * @{
116   */
117 _LONG_CALL_ void WDG_Scalar(u32 Period, u32 *pCountProcess, u32 *pDivFacProcess);
118 _LONG_CALL_ void WDG_Init(WDG_InitTypeDef *WDG_InitStruct);
119 _LONG_CALL_ void WDG_IrqInit(void *handler, u32 Id);
120 _LONG_CALL_ void WDG_Cmd(u32 NewState);
121 _LONG_CALL_ void WDG_Refresh(void);
122 /**
123   * @}
124   */
125 
126 
127 /* Registers Definitions --------------------------------------------------------*/
128 /**************************************************************************//**
129  * @defgroup WDG_Register_Definitions WDG Register Definitions
130  * @{
131  *****************************************************************************/
132 
133 /**************************************************************************//**
134  * @defgroup WDG_REG
135  * @{
136  *****************************************************************************/
137 #define WDG_BIT_ENABLE			((u32)0x00000001 << 16)
138 #define WDG_BIT_CLEAR			((u32)0x00000001 << 24)
139 #define WDG_BIT_RST_MODE		((u32)0x00000001 << 30)
140 #define WDG_BIT_ISR_CLEAR		((u32)0x00000001 << 31)
141 /** @} */
142 /** @} */
143 
144 /**
145   * @}
146   */
147 
148 /**
149   * @}
150   */
151 
152 #endif //_RTL8721D_WDG_H_
153 /******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
154