1 /** 2 ****************************************************************************** 3 * @file rl6548.h 4 * @author 5 * @version V1.0.0 6 * @date 2018-12-12 7 * @brief This file contains all the functions prototypes for the audio codec firmware 8 * library. 9 ****************************************************************************** 10 * @attention 11 * 12 * This module is a confidential and proprietary property of RealTek and 13 * possession or use of this module requires written permission of RealTek. 14 * 15 * Copyright(c) 2018, Realtek Semiconductor Corporation. All rights reserved. 16 ****************************************************************************** 17 */ 18 19 #ifndef __RL6548_H__ 20 #define __RL6548_H__ 21 22 /** @addtogroup AmebaD_Periph_Driver 23 * @{ 24 */ 25 26 /** @defgroup audio 27 * @brief audio driver modules 28 * @{ 29 */ 30 31 /** @addtogroup audio 32 * @verbatim 33 ***************************************************************************************** 34 * Introduction 35 ***************************************************************************************** 36 * codec: 37 * - Support anti-pop function to reduce audible pop 38 * - Support AMIC-in, DMIC-in, Line-in and Line-out 39 * - Sample rate: 8/16/32/44.1/48/96 KHz 40 * - Sample bit: 16 bit, 24 bit, 8bit 41 * - Channel number: mono or stereo 42 * - Data format: I2S, Left justified, PCM mode A, PCM mode B, PCM mode A-N, PCM mode B-N 43 * - Gain Control in ADC and DAC Path 44 * 45 * audio SI: 46 * - Base Address: AUDIO_SI_DEV 47 * - can use to configure codec register 48 * 49 ***************************************************************************************** 50 * How to use audio SI & codec API 51 ***************************************************************************************** 52 * To use audio codec si, the following steps are mandatory: 53 * 54 * 1. Open audio codec clock and function using 55 * PLLx_Set(0, ENABLE); (x is 0 or 1) 56 * RCC_PeriphClockCmd(APBPeriph_AUDIOC, APBPeriph_AUDIOC_CLOCK, ENABLE); 57 * RCC_PeriphClockCmd(APBPeriph_SPORT, APBPeriph_SPORT_CLOCK, ENABLE); 58 * 59 * 2. AUDIO SI enable: 60 * AUDIO_SI_Cmd(ENABLE). 61 * 62 * 3. Write AUDIO Codec registers using: 63 * AUDIO_SI_WriteReg(address, data); 64 * 65 * 4. Read AUDIO Codec registers using: 66 * AUDIO_SI_ReadReg(address); 67 * 68 * @note Turn on AUDIO Codec register bank clock using: 69 * AUDIO_SI_ClkCmd(ENABLE); 70 * 71 * @note Turn off AUDIO Codec register bank clock using: 72 * AUDIO_SI_ClkCmd(DISABLE); 73 * 74 * To use audio codec si, the following steps are mandatory: 75 * 76 * 1. Codec initialize using 77 * CODEC_Init(sample_rate, word_len, mono_stereo, application); 78 * 79 * 2. Codec set volume using 80 * CODEC_SetVolume(vol_lch, vol_rch); 81 * 82 * 3. Codec get volume using 83 * CODEC_GetVolume(*vol); 84 * 85 * 4. Set codec ADC and DAC sample rate using 86 * CODEC_SetSr(sample_rate); 87 * 88 * 5. Set codec ADC gain using 89 * CODEC_SetAdcGain(ad_gain_left, ad_gain_right); 90 * 91 * 6. Set codec MIC_BIAS output voltage 92 * CODEC_SetMicBias(mic_bias); 93 * 94 * 7. Codec de-initialize using 95 * CODEC_DeInit(application); 96 * 97 * @note All other functions can be used separately to modify, if needed, 98 * a specific feature of the AUDIO 99 ***************************************************************************************** 100 * @endverbatim 101 */ 102 103 /* Exported constants --------------------------------------------------------*/ 104 105 /** @defgroup AUDIO_Exported_Constants AUDIO Exported Constants 106 * @{ 107 */ 108 109 /** @defgroup CODEC_sample_rate AUDIO Codec Sample Rate 110 * @{ 111 */ 112 #define SR_48K ((u32)0x00000000) 113 #define SR_96K ((u32)0x00000001) 114 #define SR_32K ((u32)0x00000003) 115 #define SR_16K ((u32)0x00000005) 116 #define SR_8K ((u32)0x00000007) 117 #define SR_44P1K ((u32)0x00000008) 118 #define SR_88P2K ((u32)0x00000009) 119 120 /** 121 * @} 122 */ 123 124 /** @defgroup CODEC_word_len AUDIO Codec Word Len 125 * @{ 126 */ 127 #define WL_16 ((u32)0x00000000) 128 #define WL_24 ((u32)0x00000002) 129 #define WL_8 ((u32)0x00000003) 130 131 /** 132 * @} 133 */ 134 135 /** @defgroup CODEC_channel_mode AUDIO Codec Channel Mode 136 * @{ 137 */ 138 #define CH_STEREO ((u32)0x00000000) 139 #define CH_MONO ((u32)0x00000001) 140 141 /** 142 * @} 143 */ 144 145 /** @defgroup CODEC_application_mode AUDIO CODEC Application Mode 146 * @{ 147 */ 148 #define APP_AMIC_IN ((u32)0x00000001) 149 #define APP_DMIC_IN ((u32)0x00000002) 150 #define APP_LINE_IN ((u32)0x00000004) 151 #define APP_LINE_OUT ((u32)0x00000008) 152 #define APP_DAAD_LPBK ((u32)0x00000010) 153 154 /** 155 * @} 156 */ 157 158 /** @defgroup CODEC_mute_action AUDIO CODEC mute action per channel 159 * @{ 160 */ 161 #define MUTE_DISABLE ((u32)0x00000000) 162 #define MUTE_ENABLE ((u32)0x00000001) 163 #define MUTE_NO_ACT ((u32)0x00000002) 164 165 /** 166 * @} 167 */ 168 169 170 /** @defgroup Codec_rx_channel_selection AUDIO CODEC Rx Channel Selection 171 * @{ 172 */ 173 #define RX_CH_LR ((u32)0x00000000) 174 #define RX_CH_RL ((u32)0x00000001) 175 #define RX_CH_LL ((u32)0x00000002) 176 #define RX_CH_RR ((u32)0x00000003) 177 178 /** 179 * @} 180 */ 181 182 /** 183 * @} 184 */ 185 186 /** @defgroup Register Macro Definition and Bit Definition 187 * @{ 188 */ 189 #define GEN_CTRL 0x00 190 #define HPO_CTRL 0x01 191 #define HPO_MIC_CTRL 0x02 192 #define MICBST_CTRL 0x03 193 #define DEBUG_BUS_SEL 0x04 194 #define CK_DEPOP_MICBIAS 0x0c 195 #define SIDETONE_CTRL 0x0f 196 #define I2S_CTRL 0x10 197 #define ADC_DMIC_L_FILTER_CTRL 0x11 198 #define ADC_L_CTRL 0x12 199 #define ADC_L_GAIN 0x13 200 #define ADC_DMIC_R_FILTER_CTRL 0x14 201 #define ADC_R_ADJ_D 0x15 202 #define ADC_R_GAIN 0x16 203 #define DAC_ADC_SR_CTRL 0x17 204 #define DAC_ADC_MIC_CLK_CTRL 0x18 205 #define ASRC_FTK_SDM_INI 0x19 206 #define GEN_SRC_CLK_CTRL 0x1a 207 #define ASRC_CTRL 0x1b 208 #define ALC_ATK_CTRL 0x1c 209 #define ALC_ZD_BK 0x1d 210 #define ALC_DRC_CTRL 0x1e 211 #define ALC_NOISE_CTRL 0x1f 212 #define ALC_VAL_CTRL 0x20 213 #define ALC_RATE_CTRL 0x21 214 #define ALC_RC_WD_CTRL 0x22 215 #define ALC_TH_CTRL 0x23 216 #define ALC_ZERO_CTRL 0x24 217 #define ALC_LIMITER_TH1 0x25 218 #define ALC_LIMITER_TH2 0x26 219 #define ALC_MIN_GAIN 0x27 220 #define ALC_MODE_CTRL 0x28 221 #define ALC_STATUS_REG 0x29 222 #define DAC_L_SILENCE_CTRL 0xf6 223 #define DAC_R_SILENCE_CTRL 0Xf7 224 #define ADC_L_SILENCE_CTRL 0xf8 225 #define ADC_R_SILENCE_CTRL 0xf9 226 #define DAC_L_CTRL 0xfa 227 #define DAC_L_MUTE_CTRL 0xfb 228 #define DAC_R_CTRL 0xfc 229 #define DAC_R_MUTE_CTRL 0xfd 230 231 #define DAC_L_BQ_EQ_CTRL 0x2a 232 #define DAC_L_BIQUAD_H0_1L 0x2b 233 #define DAC_L_BIQUAD_H0_1H 0x2c 234 #define DAC_L_BIQUAD_B1_1L 0x2d 235 #define DAC_L_BIQUAD_B1_1H 0x2e 236 #define DAC_L_BIQUAD_B2_1L 0x2f 237 #define DAC_L_BIQUAD_B2_1H 0x30 238 #define DAC_L_BIQUAD_A1_1L 0x31 239 #define DAC_L_BIQUAD_A1_1H 0x32 240 #define DAC_L_BIQUAD_A2_1L 0x33 241 #define DAC_L_BIQUAD_A2_1H 0x34 242 #define DAC_L_BIQUAD_H0_2L 0x35 243 #define DAC_L_BIQUAD_H0_2H 0x36 244 #define DAC_L_BIQUAD_B1_2L 0x37 245 #define DAC_L_BIQUAD_B1_2H 0x38 246 #define DAC_L_BIQUAD_B2_2L 0x39 247 #define DAC_L_BIQUAD_B2_2H 0x3a 248 #define DAC_L_BIQUAD_A1_2L 0x3b 249 #define DAC_L_BIQUAD_A1_2H 0x3c 250 #define DAC_L_BIQUAD_A2_2L 0x3d 251 #define DAC_L_BIQUAD_A2_2H 0x3e 252 #define DAC_L_BIQUAD_H0_3L 0x3f 253 #define DAC_L_BIQUAD_H0_3H 0x40 254 #define DAC_L_BIQUAD_B1_3L 0x41 255 #define DAC_L_BIQUAD_B1_3H 0x42 256 #define DAC_L_BIQUAD_B2_3L 0x43 257 #define DAC_L_BIQUAD_B2_3H 0x44 258 #define DAC_L_BIQUAD_A1_3L 0x45 259 #define DAC_L_BIQUAD_A1_3H 0x46 260 #define DAC_L_BIQUAD_A2_3L 0x47 261 #define DAC_L_BIQUAD_A2_3H 0x48 262 #define DAC_L_BIQUAD_H0_4L 0x49 263 #define DAC_L_BIQUAD_H0_4H 0x4a 264 #define DAC_L_BIQUAD_B1_4L 0x4b 265 #define DAC_L_BIQUAD_B1_4H 0x4c 266 #define DAC_L_BIQUAD_B2_4L 0x4d 267 #define DAC_L_BIQUAD_B2_4H 0x4e 268 #define DAC_L_BIQUAD_A1_4L 0x4f 269 #define DAC_L_BIQUAD_A1_4H 0x50 270 #define DAC_L_BIQUAD_A2_4L 0x51 271 #define DAC_L_BIQUAD_A2_4H 0x52 272 #define DAC_L_BIQUAD_H0_5L 0x53 273 #define DAC_L_BIQUAD_H0_5H 0x54 274 #define DAC_L_BIQUAD_B1_5L 0x55 275 #define DAC_L_BIQUAD_B1_5H 0x56 276 #define DAC_L_BIQUAD_B2_5L 0x57 277 #define DAC_L_BIQUAD_B2_5H 0x58 278 #define DAC_L_BIQUAD_A1_5L 0x59 279 #define DAC_L_BIQUAD_A1_5H 0x5a 280 #define DAC_L_BIQUAD_A2_5L 0x5b 281 #define DAC_L_BIQUAD_A2_5H 0x5c 282 283 #define DAC_R_BQ_EQ_CONTROL 0x5d 284 #define DAC_R_BIQUAD_H0_1L 0x5e 285 #define DAC_R_BIQUAD_H0_1H 0x5f 286 #define DAC_R_BIQUAD_B1_1L 0x60 287 #define DAC_R_BIQUAD_B1_1H 0x61 288 #define DAC_R_BIQUAD_B2_1L 0x62 289 #define DAC_R_BIQUAD_B2_1H 0x63 290 #define DAC_R_BIQUAD_A1_1L 0x64 291 #define DAC_R_BIQUAD_A1_1H 0x65 292 #define DAC_R_BIQUAD_A2_1L 0x66 293 #define DAC_R_BIQUAD_A2_1H 0x67 294 #define DAC_R_BIQUAD_H0_2L 0x68 295 #define DAC_R_BIQUAD_H0_2H 0x69 296 #define DAC_R_BIQUAD_B1_2L 0x6a 297 #define DAC_R_BIQUAD_B1_2H 0x6b 298 #define DAC_R_BIQUAD_B2_2L 0x6c 299 #define DAC_R_BIQUAD_B2_2H 0x6d 300 #define DAC_R_BIQUAD_A1_2L 0x6e 301 #define DAC_R_BIQUAD_A1_2H 0x6f 302 #define DAC_R_BIQUAD_A2_2L 0x70 303 #define DAC_R_BIQUAD_A2_2H 0x71 304 #define DAC_R_BIQUAD_H0_3L 0x72 305 #define DAC_R_BIQUAD_H0_3H 0x73 306 #define DAC_R_BIQUAD_B1_3L 0x74 307 #define DAC_R_BIQUAD_B1_3H 0x75 308 #define DAC_R_BIQUAD_B2_3L 0x76 309 #define DAC_R_BIQUAD_B2_3H 0x77 310 #define DAC_R_BIQUAD_A1_3L 0x78 311 #define DAC_R_BIQUAD_A1_3H 0x79 312 #define DAC_R_BIQUAD_A2_3L 0x7a 313 #define DAC_R_BIQUAD_A2_3H 0x7b 314 #define DAC_R_BIQUAD_H0_4L 0x7c 315 #define DAC_R_BIQUAD_H0_4H 0x7d 316 #define DAC_R_BIQUAD_B1_4L 0x7e 317 #define DAC_R_BIQUAD_B1_4H 0x7f 318 #define DAC_R_BIQUAD_B2_4L 0x80 319 #define DAC_R_BIQUAD_B2_4H 0x81 320 #define DAC_R_BIQUAD_A1_4L 0x82 321 #define DAC_R_BIQUAD_A1_4H 0x83 322 #define DAC_R_BIQUAD_A2_4L 0x84 323 #define DAC_R_BIQUAD_A2_4H 0x85 324 #define DAC_R_BIQUAD_H0_5L 0x86 325 #define DAC_R_BIQUAD_H0_5H 0x87 326 #define DAC_R_BIQUAD_B1_5L 0x88 327 #define DAC_R_BIQUAD_B1_5H 0x89 328 #define DAC_R_BIQUAD_B2_5L 0x8a 329 #define DAC_R_BIQUAD_B2_5H 0x8b 330 #define DAC_R_BIQUAD_A1_5L 0x8c 331 #define DAC_R_BIQUAD_A1_5H 0x8d 332 #define DAC_R_BIQUAD_A2_5L 0x8e 333 #define DAC_R_BIQUAD_A2_5H 0x8f 334 335 #define ADC_L_BQ_EQ_CONTROL 0x90 336 #define ADC_L_BIQUAD_H0_1L 0x91 337 #define ADC_L_BIQUAD_H0_1H 0x92 338 #define ADC_L_BIQUAD_B1_1L 0x93 339 #define ADC_L_BIQUAD_B1_1H 0x94 340 #define ADC_L_BIQUAD_B2_1L 0x95 341 #define ADC_L_BIQUAD_B2_1H 0x96 342 #define ADC_L_BIQUAD_A1_1L 0x97 343 #define ADC_L_BIQUAD_A1_1H 0x98 344 #define ADC_L_BIQUAD_A2_1L 0x99 345 #define ADC_L_BIQUAD_A2_1H 0x9a 346 #define ADC_L_BIQUAD_H0_2L 0x9b 347 #define ADC_L_BIQUAD_H0_2H 0x9c 348 #define ADC_L_BIQUAD_B1_2L 0x9d 349 #define ADC_L_BIQUAD_B1_2H 0x9e 350 #define ADC_L_BIQUAD_B2_2L 0x9f 351 #define ADC_L_BIQUAD_B2_2H 0xa0 352 #define ADC_L_BIQUAD_A1_2L 0xa1 353 #define ADC_L_BIQUAD_A1_2H 0xa2 354 #define ADC_L_BIQUAD_A2_2L 0xa3 355 #define ADC_L_BIQUAD_A2_2H 0xa4 356 #define ADC_L_BIQUAD_H0_3L 0xa5 357 #define ADC_L_BIQUAD_H0_3H 0xa6 358 #define ADC_L_BIQUAD_B1_3L 0xa7 359 #define ADC_L_BIQUAD_B1_3H 0xa8 360 #define ADC_L_BIQUAD_B2_3L 0xa9 361 #define ADC_L_BIQUAD_B2_3H 0xaa 362 #define ADC_L_BIQUAD_A1_3L 0xab 363 #define ADC_L_BIQUAD_A1_3H 0xac 364 #define ADC_L_BIQUAD_A2_3L 0xad 365 #define ADC_L_BIQUAD_A2_3H 0xae 366 #define ADC_L_BIQUAD_H0_4L 0xaf 367 #define ADC_L_BIQUAD_H0_4H 0xb0 368 #define ADC_L_BIQUAD_B1_4L 0xb1 369 #define ADC_L_BIQUAD_B1_4H 0xb2 370 #define ADC_L_BIQUAD_B2_4L 0xb3 371 #define ADC_L_BIQUAD_B2_4H 0xb4 372 #define ADC_L_BIQUAD_A1_4L 0xb5 373 #define ADC_L_BIQUAD_A1_4H 0xb6 374 #define ADC_L_BIQUAD_A2_4L 0xb7 375 #define ADC_L_BIQUAD_A2_4H 0xb8 376 #define ADC_L_BIQUAD_H0_5L 0xb9 377 #define ADC_L_BIQUAD_H0_5H 0xba 378 #define ADC_L_BIQUAD_B1_5L 0xbb 379 #define ADC_L_BIQUAD_B1_5H 0xbc 380 #define ADC_L_BIQUAD_B2_5L 0xbd 381 #define ADC_L_BIQUAD_B2_5H 0xbe 382 #define ADC_L_BIQUAD_A1_5L 0xbf 383 #define ADC_L_BIQUAD_A1_5H 0xc0 384 #define ADC_L_BIQUAD_A2_5L 0xc1 385 #define ADC_L_BIQUAD_A2_5H 0xc2 386 387 #define ADC_R_BQ_EQ_CONTROL 0xc3 388 #define ADC_R_BIQUAD_H0_1L 0xc4 389 #define ADC_R_BIQUAD_H0_1H 0xc5 390 #define ADC_R_BIQUAD_B1_1L 0xc6 391 #define ADC_R_BIQUAD_B1_1H 0xc7 392 #define ADC_R_BIQUAD_B2_1L 0xc8 393 #define ADC_R_BIQUAD_B2_1H 0xc9 394 #define ADC_R_BIQUAD_A1_1L 0xca 395 #define ADC_R_BIQUAD_A1_1H 0xcb 396 #define ADC_R_BIQUAD_A2_1L 0xcc 397 #define ADC_R_BIQUAD_A2_1H 0xcd 398 #define ADC_R_BIQUAD_H0_2L 0xce 399 #define ADC_R_BIQUAD_H0_2H 0xcf 400 #define ADC_R_BIQUAD_B1_2L 0xd0 401 #define ADC_R_BIQUAD_B1_2H 0xd1 402 #define ADC_R_BIQUAD_B2_2L 0xd2 403 #define ADC_R_BIQUAD_B2_2H 0xd3 404 #define ADC_R_BIQUAD_A1_2L 0xd4 405 #define ADC_R_BIQUAD_A1_2H 0xd5 406 #define ADC_R_BIQUAD_A2_2L 0xd6 407 #define ADC_R_BIQUAD_A2_2H 0xd7 408 #define ADC_R_BIQUAD_H0_3L 0xd8 409 #define ADC_R_BIQUAD_H0_3H 0xd9 410 #define ADC_R_BIQUAD_B1_3L 0xda 411 #define ADC_R_BIQUAD_B1_3H 0xdb 412 #define ADC_R_BIQUAD_B2_3L 0xdc 413 #define ADC_R_BIQUAD_B2_3H 0xdd 414 #define ADC_R_BIQUAD_A1_3L 0xde 415 #define ADC_R_BIQUAD_A1_3H 0xdf 416 #define ADC_R_BIQUAD_A2_3L 0xe0 417 #define ADC_R_BIQUAD_A2_3H 0xe1 418 #define ADC_R_BIQUAD_H0_4L 0xe2 419 #define ADC_R_BIQUAD_H0_4H 0xe3 420 #define ADC_R_BIQUAD_B1_4L 0xe4 421 #define ADC_R_BIQUAD_B1_4H 0xe5 422 #define ADC_R_BIQUAD_B2_4L 0xe6 423 #define ADC_R_BIQUAD_B2_4H 0xe7 424 #define ADC_R_BIQUAD_A1_4L 0xe8 425 #define ADC_R_BIQUAD_A1_4H 0xe9 426 #define ADC_R_BIQUAD_A2_4L 0xea 427 #define ADC_R_BIQUAD_A2_4H 0xeb 428 #define ADC_R_BIQUAD_H0_5L 0xec 429 #define ADC_R_BIQUAD_H0_5H 0xed 430 #define ADC_R_BIQUAD_B1_5L 0xee 431 #define ADC_R_BIQUAD_B1_5H 0xef 432 #define ADC_R_BIQUAD_B2_5L 0xf0 433 #define ADC_R_BIQUAD_B2_5H 0xf1 434 #define ADC_R_BIQUAD_A1_5L 0xf2 435 #define ADC_R_BIQUAD_A1_5H 0xf3 436 #define ADC_R_BIQUAD_A2_5L 0xf4 437 #define ADC_R_BIQUAD_A2_5H 0xf5 438 439 //0x00 440 #define BIT_DAC_ADDACK_POW 0 441 #define BIT_DAC_CKXEN 1 442 #define BIT_DAC_CKXSEL 2 443 #define BIT_DAC_L_POW 3 444 #define BIT_DAC_R_POW 4 445 #define BIT_DPRAMP_CSEL 5 446 #define BIT_DPRAMP_ENRAMP 7 447 #define BIT_DPRAMP_POW 8 448 #define BIT_DTSDM_CKXEN 9 449 #define BIT_DTSDM_POW_L 10 450 #define BIT_DTSDM_POW_R 11 451 #define BIT_HPO_CLL 12 452 #define BIT_HPO_CLNDPL 13 453 #define BIT_HPO_CLNDPR 14 454 #define BIT_HPO_CLPDPL 15 455 456 //0x01 457 #define BIT_HPO_CLPDPR 0 458 #define BIT_HPO_CLR 1 459 #define BIT_HPO_DPRSELL 2 460 #define BIT_HPO_DPRSELR 4 461 #define BIT_HPO_ENAL 6 462 #define BIT_HPO_ENAR 7 463 #define BIT_HPO_ENDPL 8 464 #define BIT_HPO_ENDPR 9 465 #define BIT_HPO_L_POW 10 466 #define BIT_HPO_MDPL 11 467 #define BIT_HPO_MDPR 12 468 #define BIT_HPO_OPNDPL 13 469 #define BIT_HPO_OPNDPR 14 470 #define BIT_HPO_OPPDPL 15 471 472 473 //0x02 474 #define BIT_HPO_ML 0 475 #define BIT_HPO_MR 2 476 #define BIT_HPO_OPPDPR 4 477 #define BIT_HPO_R_POW 5 478 #define BIT_HPO_SEL 6 479 #define BIT_HPO_SER 7 480 #define BIT_MBIAS_POW 8 481 #define BIT_MICBIAS_ENCHX 9 482 #define BIT_MICBIAS_POW 10 483 #define BIT_MICBIAS_VSET 11 484 #define BIT_MICBST_ENDFL 13 485 #define BIT_MICBST_ENDFR 14 486 #define BIT_VREF_POW 15 487 488 489 //0x03 490 #define BIT_MICBST_GSELL 0 491 #define BIT_MICBST_GSELR 2 492 #define BIT_MICBST_MUTE_L 4 493 #define BIT_MICBST_MUTE_R 6 494 #define BIT_MICBST_POW 8 495 #define BIT_VREF_VREFSEL 10 496 497 //0x0c 498 #define BIT_SEL_BB_CK_DEPOP 0 499 #define BIT_MICBIAS_OC 2 500 #define BIT_BB_CK_DEPOP_EN 3 501 #define BIT_CKX_MICBIAS_EN 4 502 503 //0x10 504 #define BIT_EN_I2S_MONO 0 505 #define BIT_I2S_EN_PCM_N_MODE 1 506 #define BIT_I2S_DATA_FORMAT_SEL 2 507 #define BIT_I2S_DATA_LEN_SEL 4 508 #define BIT_INV_I2S_SCLK 6 509 #define BIT_I2S_RST_N_REG 7 510 #define BIT_SEL_I2S_RX_CH 8 511 #define BIT_SEL_I2S_TX_CH 10 512 #define BIT_STEREO_I2S_SELF_LPBK_EN 12 513 514 //0x11 515 #define BIT_ADC_L_DMIC_RI_FA_SEL 0 516 #define BIT_ADC_L_DMIC_LPF2ND_EN 3 517 #define BIT_ADC_L_DMIC_LPF1ST_EN 4 518 #define BIT_ADC_L_DMIC_LPF1ST_FC_SEL 5 519 #define BIT_ADC_L_AD_LPF2ND_EN 8 520 #define BIT_ADC_L_AD_LPF1ST_EN 9 521 #define BIT_ADC_L_AD_LPF1ST_FC_SEL 10 522 #define BIT_ADC_L_AD_MIX_MUTE 12 523 #define BIT_ADC_L_DMIC_MIX_MUTE 13 524 #define BIT_ADC_L_AD_DCHPF_EN 14 525 526 527 //0x12 528 #define BIT_ADC_L_AD_COMP_GAIN 0 529 #define BIT_ADC_L_ADJ_HPF_2ND_EN 2 530 #define BIT_ADC_L_ADJ_HPF_COEF_SEL 3 531 #define BIT_ADC_L_DMIC_BOOST_GAIN 6 532 #define BIT_ADC_L_AD_MUTE 8 533 #define BIT_ADC_L_AD_ZDET_FUNC 9 534 #define BIT_ADC_L_AD_ZDET_TOUT 11 535 536 //0x13 537 #define ADC_L_ADJ_HPF_COEF_NUM 0 538 #define ADC_L_AD_GAIN 6 539 540 541 542 //0x14 543 #define BIT_ADC_R_DMIC_RI_FA_SEL 0 544 #define BIT_ADC_R_DMIC_LPF2ND_EN 3 545 #define BIT_ADC_R_DMIC_LPF1ST_EN 4 546 #define BIT_ADC_R_DMIC_LPF1ST_FC_SEL 5 547 #define BIT_ADC_R_AD_LPF2ND_EN 8 548 #define BIT_ADC_R_AD_LPF1ST_EN 9 549 #define BIT_ADC_R_AD_LPF1ST_FC_SEL 10 550 #define BIT_ADC_R_AD_MIX_MUTE 12 551 #define BIT_ADC_R_DMIC_MIX_MUTE 13 552 #define BIT_ADC_R_AD_DCHPF_EN 14 553 554 //0x15 555 #define BIT_ADC_R_AD_COMP_GAIN 0 556 #define BIT_ADC_R_ADJ_HPF_2ND_EN 2 557 #define BIT_ADC_R_ADJ_HPF_COEF_SEL 3 558 #define BIT_ADC_R_DMIC_BOOST_GAIN 6 559 #define BIT_ADC_R_AD_MUTE 8 560 #define BIT_ADC_R_AD_ZDET_FUNC 9 561 #define BIT_ADC_R_AD_ZDET_TOUT 11 562 563 //0x16 564 #define ADC_R_ADJ_HPF_COEF_NUM 0 565 #define ADC_R_AD_GAIN 6 566 567 //0x17 568 #define BIT_DAC_SAMPLE_RATE 0 569 #define BIT_ADC_SAMPLE_RATE 4 570 #define BIT_DMIC_CLK_SEL 8 571 #define BIT_ASRC_FSI_RATE_MANUAL 11 572 #define BIT_ASRC_FSI_GATING_EN 15 573 574 //0x18 575 #define BIT_DA_L_EN 0 576 #define BIT_DA_R_EN 1 577 #define BIT_MOD_L_EN 2 578 #define BIT_MOD_R_EN 3 579 #define BIT_DA_ANA_CLK_EN 4 580 #define BIT_DA_FIFO_EN 5 581 #define BIT_ST_EN 6 582 #define BIT_AD_L_EN 7 583 #define BIT_AD_R_EN 8 584 #define BIT_AD_FIFO_EN 9 585 #define BIT_AD_ANA_CLK_EN 10 586 #define BIT_AD_ANA_L_EN 11 587 #define BIT_AD_ANA_R_EN 12 588 #define BIT_DMIC_L_EN 13 589 #define BIT_DMIC_R_EN 14 590 #define BIT_DMIC_CLK_EN 15 591 592 //0x1b 593 #define BIT_AUDIO_IP_TCON_EN 0 594 #define BIT_ASRC_FTK_LOOP_EN 1 595 #define BIT_ASRC_256FS_SYS_SEL 2 596 #define BIT_ASRC_EN 4 597 #define BIT_SIDETONE_IN_SEL 5 598 599 //0x27 600 #define BIT_ALC_MIN_GAIN 0 601 #define BIT_DA_STEREO_MODE_EN 8 602 603 //0xfa 604 #define BIT_DAC_L_DA_GAIN 0 605 #define BIT_DAC_L_DAHPF_EN 8 606 #define BIT_DAC_L_DA_DITHER_SEL 9 607 #define BIT_DAC_L_DA_ZDET_FUNC 11 608 #define BIT_DAC_L_DA_ZDET_TOUT 13 609 #define BIT_DAC_L_DMIX_IN_SEL 15 610 611 //0xfb 612 #define BIT_DAC_L_DA_MUTE 0 613 #define BIT_DAAD_LPBK_EN 1 614 #define BIT_DAC_L_DMIX_MUTE_128FS_DA 2 615 #define BIT_DAC_L_DMIX_MUTE_128FS_SIDETONE 3 616 617 //0xfd 618 #define BIT_DAC_R_DA_MUTE 0 619 #define BIT_DAC_R_DMIX_MUTE_128FS_DA 2 620 #define BIT_DAC_R_DMIX_MUTE_128FS_SIDETONE 3 621 622 623 /** @defgroup AUDIO_Exported_Functions AUDIO Exported Functions 624 * @{ 625 */ 626 /** @defgroup AUDIO_SI_functions 627 * @{ 628 */ 629 void AUDIO_SI_Cmd(u8 new_state); 630 void AUDIO_SI_WriteReg(u32 address, u32 data); 631 u16 AUDIO_SI_ReadReg(u32 address); 632 void AUDIO_SI_ClkCmd(u8 new_state); 633 /** 634 * @} 635 */ 636 637 /** @defgroup AUDIO_codec_functions 638 * @{ 639 */ 640 void CODEC_Init(u32 sample_rate, u32 word_len, u32 mono_stereo, u32 application); 641 void CODEC_SetVolume(u8 vol_lch, u8 vol_rch); 642 void CODEC_GetVolume(u16 *vol); 643 void CODEC_SetSr(u32 sample_rate); 644 void CODEC_SetAdcGain(u32 ad_gain_left, u32 ad_gain_right); 645 void CODEC_SetAmicBst(u32 amic_bst_left, u32 amic_bst_right); 646 void CODEC_SetDmicBst(u32 dmic_bst_left, u32 dmic_bst_right); 647 void CODEC_SetMicBias(u8 mic_bias); 648 void CODEC_MuteRecord(u32 mute_lch, u32 mute_rch); 649 void CODEC_MutePlay(u32 mute_lch, u32 mute_rch); 650 void CODEC_DeInit(u32 application); 651 void CODEC_DacEqConfig(u32 sample_rate); 652 void CODEC_SetALC(u32 limiter_val); 653 void CODEDC_ALC_deinit(); 654 /** 655 * @} 656 */ 657 658 /** 659 * @} 660 */ 661 662 /** 663 * @} 664 */ 665 666 /** 667 * @} 668 */ 669 #endif 670 671 /******************* (C) COPYRIGHT 2018 Realtek Semiconductor *****END OF FILE****/ 672