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/arm-trusted-firmware-2.8.0/plat/imx/imx8m/include/
A Dddrc.h10 #define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000)) argument
15 #define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00) argument
16 #define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04) argument
17 #define DDRC_MSTR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x08) argument
18 #define DDRC_MRCTRL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x10) argument
19 #define DDRC_MRCTRL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x14) argument
20 #define DDRC_MRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18) argument
21 #define DDRC_MRCTRL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c) argument
22 #define DDRC_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x20) argument
23 #define DDRC_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x24) argument
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/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/include/t194/
A Dtegra194_ras_private.h33 #define IFU_UNCORR_RAS_ERROR_LIST(X) argument
36 #define JSR_RET_UNCORR_RAS_ERROR_LIST(X) \ argument
44 #define JSR_MTS_UNCORR_RAS_ERROR_LIST(X) \ argument
55 #define LSD_STQ_UNCORR_RAS_ERROR_LIST(X) \ argument
74 #define LSD_L1HPF_UNCORR_RAS_ERROR_LIST(X) argument
77 #define L2_UNCORR_RAS_ERROR_LIST(X) \ argument
107 #define MMU_UNCORR_RAS_ERROR_LIST(X) argument
110 #define L3_UNCORR_RAS_ERROR_LIST(X) \ argument
228 #define PER_CORE_RAS_NODE_LIST(X) \ argument
245 #define SCF_L3_BANK_RAS_NODE_LIST(X) X(L3) argument
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