1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (C) Foundries Ltd. 2021 4 * Author: Jorge Ramirez <jorge@foundries.io> 5 */ 6 7 #ifndef __DRIVERS_ZYNQMP_CSU_H_ 8 #define __DRIVERS_ZYNQMP_CSU_H_ 9 10 /* CSU registers */ 11 #define ZYNQMP_CSU_STATUS_OFFSET 0x00 12 #define ZYNQMP_CSU_CTRL_OFFSET 0x04 13 #define ZYNQMP_CSU_SSS_CFG_OFFSET 0x08 14 #define ZYNQMP_CSU_DMA_RESET_OFFSET 0x0c 15 #define ZYNQMP_CSU_MULTI_BOOT_OFFSET 0x10 16 #define ZYNQMP_CSU_TAMPER_TRIG_OFFSET 0x14 17 #define ZYNQMP_CSU_FT_STATUS_OFFSET 0x18 18 #define ZYNQMP_CSU_ISR_OFFSET 0x20 19 20 #define ZYNQMP_CSU_STATUS_AUTH BIT(0) 21 #define ZYNQMP_CSU_SSS_DMA0_STREAM_TO_AES 0x5A0 22 #define ZYNQMP_CSU_DMA_RESET_SET 1 23 #define ZYNQMP_CSU_DMA_RESET_CLR 0 24 #define ZYNQMP_CSU_ISR_PUF_ACC_ERROR_MASK BIT(12) 25 26 /* AES-GCM */ 27 #define ZYNQMP_CSU_AES_BASE (CSU_BASE + 0x1000) 28 #define ZYNQMP_CSU_AES_SIZE 0x1000 29 30 /* SHA */ 31 #define ZYNQMP_CSU_SHA_BASE (CSU_BASE + 0x2000) 32 #define ZYNQMP_CSU_SHA_SIZE 0x1000 33 34 /* PCAP */ 35 #define ZYNQMP_CSU_PCAP_BASE (CSU_BASE + 0x3000) 36 #define ZYNQMP_CSU_PCAP_SIZE 0x1000 37 38 /* PUF */ 39 #define ZYNQMP_CSU_PUF_BASE (CSU_BASE + 0x4000) 40 #define ZYNQMP_CSU_PUF_SIZE 0x1000 41 42 /* TAMPER */ 43 #define ZYNQMP_CSU_TAMPER_BASE (CSU_BASE + 0x5000) 44 #define ZYNQMP_CSU_TAMPER_SIZE 0x38 45 46 #endif 47