1/*
2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/*
8 * The .data section gets copied from ROM to RAM at runtime.
9 * Its LMA should be 16-byte aligned to allow efficient copying of 16-bytes
10 * aligned regions in it.
11 * Its VMA must be page-aligned as it marks the first read/write page.
12 */
13#define DATA_ALIGN	16
14
15#include <common/bl_common.ld.h>
16#include <lib/xlat_tables/xlat_tables_defs.h>
17
18OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
19OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
20ENTRY(bl1_entrypoint)
21
22MEMORY {
23    ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE
24    RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE
25}
26
27SECTIONS
28{
29    . = BL1_RO_BASE;
30    ASSERT(. == ALIGN(PAGE_SIZE),
31           "BL1_RO_BASE address is not aligned on a page boundary.")
32
33#if SEPARATE_CODE_AND_RODATA
34    .text . : {
35        __TEXT_START__ = .;
36        *bl1_entrypoint.o(.text*)
37        *(SORT_BY_ALIGNMENT(.text*))
38        *(.vectors)
39        . = ALIGN(PAGE_SIZE);
40        __TEXT_END__ = .;
41    } >ROM
42
43    /* .ARM.extab and .ARM.exidx are only added because Clang need them */
44    .ARM.extab . : {
45        *(.ARM.extab* .gnu.linkonce.armextab.*)
46    } >ROM
47
48    .ARM.exidx . : {
49        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
50    } >ROM
51
52    .rodata . : {
53        __RODATA_START__ = .;
54        *(SORT_BY_ALIGNMENT(.rodata*))
55
56	RODATA_COMMON
57
58        /*
59         * No need to pad out the .rodata section to a page boundary. Next is
60         * the .data section, which can mapped in ROM with the same memory
61         * attributes as the .rodata section.
62         *
63         * Pad out to 16 bytes though as .data section needs to be 16 byte
64         * aligned and lld does not align the LMA to the aligment specified
65         * on the .data section.
66         */
67        __RODATA_END__ = .;
68         . = ALIGN(16);
69    } >ROM
70#else
71    ro . : {
72        __RO_START__ = .;
73        *bl1_entrypoint.o(.text*)
74        *(SORT_BY_ALIGNMENT(.text*))
75        *(SORT_BY_ALIGNMENT(.rodata*))
76
77	RODATA_COMMON
78
79        *(.vectors)
80        __RO_END__ = .;
81
82        /*
83         * Pad out to 16 bytes as .data section needs to be 16 byte aligned and
84         * lld does not align the LMA to the aligment specified on the .data
85         * section.
86         */
87         . = ALIGN(16);
88    } >ROM
89#endif
90
91    ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
92           "cpu_ops not defined for this platform.")
93
94    . = BL1_RW_BASE;
95    ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE),
96           "BL1_RW_BASE address is not aligned on a page boundary.")
97
98    DATA_SECTION >RAM AT>ROM
99    __DATA_RAM_START__ = __DATA_START__;
100    __DATA_RAM_END__ = __DATA_END__;
101
102    STACK_SECTION >RAM
103    BSS_SECTION >RAM
104    XLAT_TABLE_SECTION >RAM
105
106#if USE_COHERENT_MEM
107    /*
108     * The base address of the coherent memory section must be page-aligned (4K)
109     * to guarantee that the coherent data are stored on their own pages and
110     * are not mixed with normal data.  This is required to set up the correct
111     * memory attributes for the coherent data page tables.
112     */
113    coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
114        __COHERENT_RAM_START__ = .;
115        *(tzfw_coherent_mem)
116        __COHERENT_RAM_END_UNALIGNED__ = .;
117        /*
118         * Memory page(s) mapped to this section will be marked
119         * as device memory.  No other unexpected data must creep in.
120         * Ensure the rest of the current memory page is unused.
121         */
122        . = ALIGN(PAGE_SIZE);
123        __COHERENT_RAM_END__ = .;
124    } >RAM
125#endif
126
127    __BL1_RAM_START__ = ADDR(.data);
128    __BL1_RAM_END__ = .;
129
130    __DATA_ROM_START__ = LOADADDR(.data);
131    __DATA_SIZE__ = SIZEOF(.data);
132
133    /*
134     * The .data section is the last PROGBITS section so its end marks the end
135     * of BL1's actual content in Trusted ROM.
136     */
137    __BL1_ROM_END__ =  __DATA_ROM_START__ + __DATA_SIZE__;
138    ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT,
139           "BL1's ROM content has exceeded its limit.")
140
141    __BSS_SIZE__ = SIZEOF(.bss);
142
143#if USE_COHERENT_MEM
144    __COHERENT_RAM_UNALIGNED_SIZE__ =
145        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
146#endif
147
148    ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.")
149}
150