1/*
2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/bl_common.ld.h>
8#include <lib/xlat_tables/xlat_tables_defs.h>
9
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
12ENTRY(bl31_entrypoint)
13
14
15MEMORY {
16    RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE
17#if SEPARATE_NOBITS_REGION
18    NOBITS (rw!a): ORIGIN = BL31_NOBITS_BASE, LENGTH = BL31_NOBITS_LIMIT - BL31_NOBITS_BASE
19#else
20#define NOBITS RAM
21#endif
22}
23
24#ifdef PLAT_EXTRA_LD_SCRIPT
25#include <plat.ld.S>
26#endif
27
28SECTIONS
29{
30    . = BL31_BASE;
31    ASSERT(. == ALIGN(PAGE_SIZE),
32           "BL31_BASE address is not aligned on a page boundary.")
33
34    __BL31_START__ = .;
35
36#if SEPARATE_CODE_AND_RODATA
37    .text . : {
38        __TEXT_START__ = .;
39        *bl31_entrypoint.o(.text*)
40        *(SORT_BY_ALIGNMENT(SORT(.text*)))
41        *(.vectors)
42        . = ALIGN(PAGE_SIZE);
43        __TEXT_END__ = .;
44    } >RAM
45
46    .rodata . : {
47        __RODATA_START__ = .;
48        *(SORT_BY_ALIGNMENT(.rodata*))
49
50#if PLAT_EXTRA_RODATA_INCLUDES
51#include <plat.ld.rodata.inc>
52#endif
53
54	RODATA_COMMON
55
56        /* Place pubsub sections for events */
57        . = ALIGN(8);
58#include <lib/el3_runtime/pubsub_events.h>
59
60        . = ALIGN(PAGE_SIZE);
61        __RODATA_END__ = .;
62    } >RAM
63#else
64    ro . : {
65        __RO_START__ = .;
66        *bl31_entrypoint.o(.text*)
67        *(SORT_BY_ALIGNMENT(.text*))
68        *(SORT_BY_ALIGNMENT(.rodata*))
69
70	RODATA_COMMON
71
72        /* Place pubsub sections for events */
73        . = ALIGN(8);
74#include <lib/el3_runtime/pubsub_events.h>
75
76        *(.vectors)
77        __RO_END_UNALIGNED__ = .;
78        /*
79         * Memory page(s) mapped to this section will be marked as read-only,
80         * executable.  No RW data from the next section must creep in.
81         * Ensure the rest of the current memory page is unused.
82         */
83        . = ALIGN(PAGE_SIZE);
84        __RO_END__ = .;
85    } >RAM
86#endif
87
88    ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
89           "cpu_ops not defined for this platform.")
90
91#if SPM_MM
92#ifndef SPM_SHIM_EXCEPTIONS_VMA
93#define SPM_SHIM_EXCEPTIONS_VMA         RAM
94#endif
95
96    /*
97     * Exception vectors of the SPM shim layer. They must be aligned to a 2K
98     * address, but we need to place them in a separate page so that we can set
99     * individual permissions to them, so the actual alignment needed is 4K.
100     *
101     * There's no need to include this into the RO section of BL31 because it
102     * doesn't need to be accessed by BL31.
103     */
104    spm_shim_exceptions : ALIGN(PAGE_SIZE) {
105        __SPM_SHIM_EXCEPTIONS_START__ = .;
106        *(.spm_shim_exceptions)
107        . = ALIGN(PAGE_SIZE);
108        __SPM_SHIM_EXCEPTIONS_END__ = .;
109    } >SPM_SHIM_EXCEPTIONS_VMA AT>RAM
110
111    PROVIDE(__SPM_SHIM_EXCEPTIONS_LMA__ = LOADADDR(spm_shim_exceptions));
112    . = LOADADDR(spm_shim_exceptions) + SIZEOF(spm_shim_exceptions);
113#endif
114
115    /*
116     * Define a linker symbol to mark start of the RW memory area for this
117     * image.
118     */
119    __RW_START__ = . ;
120
121    DATA_SECTION >RAM
122    RELA_SECTION >RAM
123
124#ifdef BL31_PROGBITS_LIMIT
125    ASSERT(. <= BL31_PROGBITS_LIMIT, "BL31 progbits has exceeded its limit.")
126#endif
127
128#if SEPARATE_NOBITS_REGION
129    /*
130     * Define a linker symbol to mark end of the RW memory area for this
131     * image.
132     */
133    . = ALIGN(PAGE_SIZE);
134    __RW_END__ = .;
135    __BL31_END__ = .;
136
137    ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.")
138
139    . = BL31_NOBITS_BASE;
140    ASSERT(. == ALIGN(PAGE_SIZE),
141           "BL31 NOBITS base address is not aligned on a page boundary.")
142
143    __NOBITS_START__ = .;
144#endif
145
146    STACK_SECTION >NOBITS
147    BSS_SECTION >NOBITS
148    XLAT_TABLE_SECTION >NOBITS
149
150#if USE_COHERENT_MEM
151    /*
152     * The base address of the coherent memory section must be page-aligned (4K)
153     * to guarantee that the coherent data are stored on their own pages and
154     * are not mixed with normal data.  This is required to set up the correct
155     * memory attributes for the coherent data page tables.
156     */
157    coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
158        __COHERENT_RAM_START__ = .;
159        /*
160         * Bakery locks are stored in coherent memory
161         *
162         * Each lock's data is contiguous and fully allocated by the compiler
163         */
164        *(bakery_lock)
165        *(tzfw_coherent_mem)
166        __COHERENT_RAM_END_UNALIGNED__ = .;
167        /*
168         * Memory page(s) mapped to this section will be marked
169         * as device memory.  No other unexpected data must creep in.
170         * Ensure the rest of the current memory page is unused.
171         */
172        . = ALIGN(PAGE_SIZE);
173        __COHERENT_RAM_END__ = .;
174    } >NOBITS
175#endif
176
177#if SEPARATE_NOBITS_REGION
178    /*
179     * Define a linker symbol to mark end of the NOBITS memory area for this
180     * image.
181     */
182    __NOBITS_END__ = .;
183
184    ASSERT(. <= BL31_NOBITS_LIMIT, "BL31 NOBITS region has exceeded its limit.")
185#else
186    /*
187     * Define a linker symbol to mark end of the RW memory area for this
188     * image.
189     */
190    __RW_END__ = .;
191    __BL31_END__ = .;
192
193    ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.")
194#endif
195
196    /DISCARD/ : {
197        *(.dynsym .dynstr .hash .gnu.hash)
198    }
199}
200