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/linux-6.3-rc2/drivers/clk/sprd/
A Dgate.h31 #define SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument
47 #define SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \ argument
60 #define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \ argument
66 #define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \ argument
90 #define SPRD_SC_GATE_CLK_HW_OPS(_struct, _name, _parent, _reg, \ argument
97 #define SPRD_SC_GATE_CLK_HW(_struct, _name, _parent, _reg, \ argument
104 #define SPRD_GATE_CLK_HW(_struct, _name, _parent, _reg, \ argument
110 #define SPRD_PLL_SC_GATE_CLK_HW(_struct, _name, _parent, _reg, \ argument
119 _reg, _sc_offset, \ argument
135 #define SPRD_SC_GATE_CLK_FW_NAME(_struct, _name, _parent, _reg, \ argument
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A Dcomposite.h21 #define SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \ argument
35 #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \ argument
41 #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \ argument
46 #define SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, _table, \ argument
53 #define SPRD_COMP_CLK_DATA(_struct, _name, _parent, _reg, _mshift, \ argument
A Dmux.h40 _reg, _shift, _width, _flags, _fn) \ argument
52 _reg, _shift, _width, _flags) \ argument
57 #define SPRD_MUX_CLK(_struct, _name, _parents, _reg, \ argument
63 _reg, _shift, _width, _flags) \ argument
68 #define SPRD_MUX_CLK_DATA(_struct, _name, _parents, _reg, \ argument
A Dpll.h64 #define SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument
85 #define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ argument
92 #define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \ argument
99 #define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \ argument
105 #define SPRD_PLL_FW_NAME(_struct, _name, _parent, _reg, _regs_num, \ argument
112 #define SPRD_PLL_HW(_struct, _name, _parent, _reg, _regs_num, _itable, \ argument
A Ddiv.h38 #define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument
50 #define SPRD_DIV_CLK(_struct, _name, _parent, _reg, \ argument
55 #define SPRD_DIV_CLK_HW(_struct, _name, _parent, _reg, \ argument
/linux-6.3-rc2/drivers/clk/meson/
A Daxg-audio.c195 #define AUD_MST_MCLK_MUX(_name, _reg) \ argument
197 #define AUD_MST_MCLK_DIV(_name, _reg) \ argument
200 #define AUD_MST_SYS_MUX(_name, _reg) \ argument
202 #define AUD_MST_SYS_DIV(_name, _reg) \ argument
209 #define AUD_MST_SCLK_DIV(_name, _reg) \ argument
216 #define AUD_MST_SCLK(_name, _reg) \ argument
223 #define AUD_MST_LRCLK(_name, _reg) \ argument
267 #define AUD_TDM_SCLK_MUX(_name, _reg) \ argument
276 #define AUD_TDM_SCLK(_name, _reg) \ argument
280 #define AUD_TDM_SCLK_WS(_name, _reg) \ argument
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A Dclk-regmap.h117 #define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ argument
132 #define MESON_PCLK(_name, _reg, _bit, _pname) \ argument
135 #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ argument
/linux-6.3-rc2/drivers/clk/sunxi-ng/
A Dccu_gate.h19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
59 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ argument
71 #define SUNXI_CCU_GATE_HWS_WITH_PREDIV(_struct, _name, _parent, _reg, \ argument
86 #define SUNXI_CCU_GATE_DATA(_struct, _name, _data, _reg, _gate, _flags) \ argument
99 #define SUNXI_CCU_GATE_DATA_WITH_PREDIV(_struct, _name, _parent, _reg, \ argument
A Dccu_div.h87 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ argument
104 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ argument
111 #define SUNXI_CCU_DIV_TABLE_HW(_struct, _name, _parent, _reg, \ argument
129 _reg, \ argument
146 #define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
155 #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ argument
165 #define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ argument
180 #define SUNXI_CCU_M(_struct, _name, _parent, _reg, _mshift, _mwidth, \ argument
202 #define SUNXI_CCU_M_DATA_WITH_MUX(_struct, _name, _parents, _reg, \ argument
227 #define SUNXI_CCU_M_HWS_WITH_GATE(_struct, _name, _parent, _reg, \ argument
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A Dccu_mp.h34 #define SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, _reg, \ argument
55 #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
74 #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \ argument
85 #define SUNXI_CCU_MP_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
104 #define SUNXI_CCU_MP_DATA_WITH_MUX(_struct, _name, _parents, _reg, \ argument
115 #define SUNXI_CCU_MP_HW_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
152 #define SUNXI_CCU_MP_MMC_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument
A Dccu_mux.h50 _reg, _shift, _width, _gate, \ argument
64 #define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \ argument
70 #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ argument
75 #define SUNXI_CCU_MUX_DATA_WITH_GATE(_struct, _name, _parents, _reg, \ argument
89 #define SUNXI_CCU_MUX_DATA(_struct, _name, _parents, _reg, \ argument
94 #define SUNXI_CCU_MUX_HW_WITH_GATE(_struct, _name, _parents, _reg, \ argument
A Dccu_nm.h38 #define SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
61 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
86 _reg, _min_rate, \ argument
112 _parent, _reg, \ argument
140 #define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
/linux-6.3-rc2/arch/mips/include/asm/mach-pic32/
A Dpic32.h14 #define PIC32_CLR(_reg) ((_reg) + 0x04) argument
15 #define PIC32_SET(_reg) ((_reg) + 0x08) argument
16 #define PIC32_INV(_reg) ((_reg) + 0x0C) argument
/linux-6.3-rc2/drivers/regulator/
A Dmc13xxx.h55 #define MC13xxx_DEFINE(prefix, _name, _node, _reg, _vsel_reg, _voltages, _ops) \ argument
73 #define MC13xxx_FIXED_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ argument
88 #define MC13xxx_GPO_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ argument
103 #define MC13xxx_DEFINE_SW(_name, _node, _reg, _vsel_reg, _voltages, ops) \ argument
105 #define MC13xxx_DEFINE_REGU(_name, _node, _reg, _vsel_reg, _voltages, ops) \ argument
/linux-6.3-rc2/drivers/clk/actions/
A Dowl-gate.h27 #define OWL_GATE_HW(_reg, _bit_idx, _gate_flags) \ argument
34 #define OWL_GATE(_struct, _name, _parent, _reg, \ argument
47 #define OWL_GATE_NO_PARENT(_struct, _name, _reg, \ argument
A Dowl-pll.h41 #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ argument
55 #define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx, \ argument
70 #define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx, \ argument
84 #define OWL_PLL_NO_PARENT_DELAY(_struct, _name, _reg, _bfreq, _bit_idx, \ argument
A Dowl-mux.h27 #define OWL_MUX_HW(_reg, _shift, _width) \ argument
34 #define OWL_MUX(_struct, _name, _parents, _reg, \ argument
A Dowl-divider.h29 #define OWL_DIVIDER_HW(_reg, _shift, _width, _div_flags, _table) \ argument
38 #define OWL_DIVIDER(_struct, _name, _parent, _reg, \ argument
/linux-6.3-rc2/drivers/clk/pistachio/
A Dclk.h19 #define GATE(_id, _name, _pname, _reg, _shift) \ argument
39 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument
59 #define DIV(_id, _name, _pname, _reg, _width) \ argument
69 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ argument
119 #define PLL(_id, _name, _pname, _type, _reg, _rates) \ argument
130 #define PLL_FIXED(_id, _name, _pname, _type, _reg) \ argument
/linux-6.3-rc2/drivers/reset/sti/
A Dreset-stih407.c57 #define STIH407_SRST_CORE(_reg, _bit) \ argument
60 #define STIH407_SRST_SBC(_reg, _bit) \ argument
63 #define STIH407_SRST_LPM(_reg, _bit) \ argument
/linux-6.3-rc2/drivers/net/ethernet/amd/xgbe/
A Dxgbe-common.h1502 #define XGMAC_IOREAD(_pdata, _reg) \ argument
1510 #define XGMAC_IOWRITE(_pdata, _reg, _val) \ argument
1552 #define XGMAC_DMA_IOREAD(_channel, _reg) \ argument
1610 #define XSIR0_IOREAD(_pdata, _reg) \ argument
1630 #define XSIR1_IOREAD(_pdata, _reg) \ argument
1653 #define XRXTX_IOREAD(_pdata, _reg) \ argument
1686 #define XP_IOREAD(_pdata, _reg) \ argument
1694 #define XP_IOWRITE(_pdata, _reg, _val) \ argument
1719 #define XI2C_IOREAD(_pdata, _reg) \ argument
1727 #define XI2C_IOWRITE(_pdata, _reg, _val) \ argument
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/linux-6.3-rc2/drivers/ufs/host/
A Dufs-renesas.c41 #define PARAM_RESTORE(_reg, _index) \ argument
45 #define PARAM_SAVE(_reg, _mask, _index) \ argument
48 #define PARAM_POLL(_reg, _expected, _mask) \ argument
54 #define PARAM_WRITE(_reg, _val) \ argument
/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mtk.h112 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ argument
132 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument
141 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
145 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
149 #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ argument
196 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
/linux-6.3-rc2/drivers/i2c/busses/
A Di2c-brcmstb.c167 #define __bsc_readl(_reg) ioread32be(_reg) argument
168 #define __bsc_writel(_val, _reg) iowrite32be(_val, _reg) argument
170 #define __bsc_readl(_reg) ioread32(_reg) argument
171 #define __bsc_writel(_val, _reg) iowrite32(_val, _reg) argument
174 #define bsc_readl(_dev, _reg) \ argument
177 #define bsc_writel(_dev, _val, _reg) \ argument
/linux-6.3-rc2/drivers/net/ethernet/mediatek/
A Dmtk_wed_debugfs.c27 #define DUMP_REG(_reg, ...) { #_reg, MTK_##_reg, __VA_ARGS__ } argument
34 #define DUMP_WED(_reg) DUMP_REG(_reg, DUMP_TYPE_WED) argument
37 #define DUMP_WDMA(_reg) DUMP_REG(_reg, DUMP_TYPE_WDMA) argument

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