1/*********************************************************************************** 2 * SEGGER Microcontroller GmbH * 3 * The Embedded Experts * 4 *********************************************************************************** 5 * * 6 * (c) 2014 - 2018 SEGGER Microcontroller GmbH * 7 * * 8 * www.segger.com Support: support@segger.com * 9 * * 10 *********************************************************************************** 11 * * 12 * All rights reserved. * 13 * * 14 * Redistribution and use in source and binary forms, with or * 15 * without modification, are permitted provided that the following * 16 * conditions are met: * 17 * * 18 * - Redistributions of source code must retain the above copyright * 19 * notice, this list of conditions and the following disclaimer. * 20 * * 21 * - Neither the name of SEGGER Microcontroller GmbH * 22 * nor the names of its contributors may be used to endorse or * 23 * promote products derived from this software without specific * 24 * prior written permission. * 25 * * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * 27 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * 28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * 29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * 30 * DISCLAIMED. * 31 * IN NO EVENT SHALL SEGGER Microcontroller GmbH BE LIABLE FOR * 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * 34 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * 35 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * 36 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * 38 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * 39 * DAMAGE. * 40 * * 41 *********************************************************************************** 42 * * 43 * This file has been modified by Nordic Semiconductor: * 44 * To separate out device-specific data * 45 * * 46 ***********************************************************************************/ 47 48/************************************************************************************ 49 * Preprocessor Definitions * 50 * ------------------------ * 51 * NO_FPU_ENABLE * 52 * * 53 * If defined, FPU will not be enabled. * 54 * * 55 * NO_STACK_INIT * 56 * * 57 * If defined, the stack pointer will not be initialised. * 58 * * 59 * NO_SYSTEM_INIT * 60 * * 61 * If defined, the SystemInit() function will not be called. By default * 62 * SystemInit() is called after reset to enable the clocks and memories to * 63 * be initialised prior to any C startup initialisation. * 64 * * 65 * NO_VTOR_CONFIG * 66 * * 67 * If defined, the vector table offset register will not be configured. * 68 * * 69 * MEMORY_INIT * 70 * * 71 * If defined, the MemoryInit() function will be called. By default * 72 * MemoryInit() is called after SystemInit() to enable an external memory * 73 * controller. * 74 * * 75 * STACK_INIT_VAL * 76 * * 77 * If defined, specifies the initial stack pointer value. If undefined, * 78 * the stack pointer will be initialised to point to the end of the * 79 * RAM segment. * 80 * * 81 * VECTORS_IN_RAM * 82 * * 83 * If defined, the exception vectors will be copied from Flash to RAM. * 84 * * 85 ************************************************************************************/ 86 87 .syntax unified 88 89 .global Reset_Handler 90#ifdef INITIALIZE_USER_SECTIONS 91 .global InitializeUserMemorySections 92#endif 93 .extern _vectors 94 .extern nRFInitialize 95 .global afterInitialize 96 97 .section .init, "ax" 98 .thumb_func 99 100 .equ VTOR_REG, 0xE000ED08 101 .equ FPU_CPACR_REG, 0xE000ED88 102 103#ifndef STACK_INIT_VAL 104#define STACK_INIT_VAL __RAM1_segment_end__ 105#endif 106 107Reset_Handler: 108 109 /* Perform prestart tasks. */ 110 b nRFInitialize 111 112.thumb_func 113afterInitialize: 114 115#ifndef NO_STACK_INIT 116 /* Initialise main stack */ 117 ldr r0, =STACK_INIT_VAL 118 ldr r1, =0x7 119 bics r0, r1 120 mov sp, r0 121#endif 122 123#ifndef NO_SYSTEM_INIT 124 /* Initialise system */ 125 ldr r0, =SystemInit 126 blx r0 127#endif 128 129#ifdef MEMORY_INIT 130 ldr r0, =MemoryInit 131 blx r0 132#endif 133 134#ifdef VECTORS_IN_RAM 135 /* Copy exception vectors into RAM */ 136 ldr r0, =__vectors_start__ 137 ldr r1, =__vectors_end__ 138 ldr r2, =__vectors_ram_start__ 1391: 140 cmp r0, r1 141 beq 2f 142 ldr r3, [r0] 143 str r3, [r2] 144 adds r0, r0, #4 145 adds r2, r2, #4 146 b 1b 1472: 148#endif 149 150#ifndef NO_VTOR_CONFIG 151 /* Configure vector table offset register */ 152 ldr r0, =VTOR_REG 153#ifdef VECTORS_IN_RAM 154 ldr r1, =_vectors_ram 155#else 156 ldr r1, =_vectors 157#endif 158 str r1, [r0] 159#endif 160 161#if (defined(__ARM_ARCH_FPV4_SP_D16__) || defined(__ARM_ARCH_FPV5_D16__)) && !defined(NO_FPU_ENABLE) 162 /* Enable FPU */ 163 ldr r0, =FPU_CPACR_REG 164 ldr r1, [r0] 165 orr r1, r1, #(0xF << 20) 166 str r1, [r0] 167 dsb 168 isb 169#endif 170 171 /* Jump to program start */ 172 b _start 173 174#ifdef INITIALIZE_USER_SECTIONS 175 .thumb_func 176InitializeUserMemorySections: 177 ldr r0, =__start_nrf_sections 178 ldr r1, =__start_nrf_sections_run 179 ldr r2, =__end_nrf_sections_run 180 cmp r0, r1 181 beq 2f 182 subs r2, r2, r1 183 beq 2f 1841: 185 ldrb r3, [r0] 186 adds r0, r0, #1 187 strb r3, [r1] 188 adds r1, r1, #1 189 subs r2, r2, #1 190 bne 1b 1912: 192 bx lr 193#endif