1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * based on nouveau_prime.c
23 *
24 * Authors: Alex Deucher
25 */
26
27 /**
28 * DOC: PRIME Buffer Sharing
29 *
30 * The following callback implementations are used for :ref:`sharing GEM buffer
31 * objects between different devices via PRIME <prime_buffer_sharing>`.
32 */
33
34 #include "amdgpu.h"
35 #include "amdgpu_display.h"
36 #include "amdgpu_gem.h"
37 #include "amdgpu_dma_buf.h"
38 #include "amdgpu_xgmi.h"
39 #include <drm/amdgpu_drm.h>
40 #include <drm/ttm/ttm_tt.h>
41 #include <linux/dma-buf.h>
42 #include <linux/dma-fence-array.h>
43 #include <linux/pci-p2pdma.h>
44 #include <linux/pm_runtime.h>
45
46 /**
47 * amdgpu_dma_buf_attach - &dma_buf_ops.attach implementation
48 *
49 * @dmabuf: DMA-buf where we attach to
50 * @attach: attachment to add
51 *
52 * Add the attachment as user to the exported DMA-buf.
53 */
amdgpu_dma_buf_attach(struct dma_buf * dmabuf,struct dma_buf_attachment * attach)54 static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf,
55 struct dma_buf_attachment *attach)
56 {
57 struct drm_gem_object *obj = dmabuf->priv;
58 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
59 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
60 int r;
61
62 if (pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0)
63 attach->peer2peer = false;
64
65 r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
66 if (r < 0)
67 goto out;
68
69 return 0;
70
71 out:
72 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
73 return r;
74 }
75
76 /**
77 * amdgpu_dma_buf_detach - &dma_buf_ops.detach implementation
78 *
79 * @dmabuf: DMA-buf where we remove the attachment from
80 * @attach: the attachment to remove
81 *
82 * Called when an attachment is removed from the DMA-buf.
83 */
amdgpu_dma_buf_detach(struct dma_buf * dmabuf,struct dma_buf_attachment * attach)84 static void amdgpu_dma_buf_detach(struct dma_buf *dmabuf,
85 struct dma_buf_attachment *attach)
86 {
87 struct drm_gem_object *obj = dmabuf->priv;
88 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
89 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
90
91 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
92 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
93 }
94
95 /**
96 * amdgpu_dma_buf_pin - &dma_buf_ops.pin implementation
97 *
98 * @attach: attachment to pin down
99 *
100 * Pin the BO which is backing the DMA-buf so that it can't move any more.
101 */
amdgpu_dma_buf_pin(struct dma_buf_attachment * attach)102 static int amdgpu_dma_buf_pin(struct dma_buf_attachment *attach)
103 {
104 struct drm_gem_object *obj = attach->dmabuf->priv;
105 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
106
107 /* pin buffer into GTT */
108 return amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
109 }
110
111 /**
112 * amdgpu_dma_buf_unpin - &dma_buf_ops.unpin implementation
113 *
114 * @attach: attachment to unpin
115 *
116 * Unpin a previously pinned BO to make it movable again.
117 */
amdgpu_dma_buf_unpin(struct dma_buf_attachment * attach)118 static void amdgpu_dma_buf_unpin(struct dma_buf_attachment *attach)
119 {
120 struct drm_gem_object *obj = attach->dmabuf->priv;
121 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
122
123 amdgpu_bo_unpin(bo);
124 }
125
126 /**
127 * amdgpu_dma_buf_map - &dma_buf_ops.map_dma_buf implementation
128 * @attach: DMA-buf attachment
129 * @dir: DMA direction
130 *
131 * Makes sure that the shared DMA buffer can be accessed by the target device.
132 * For now, simply pins it to the GTT domain, where it should be accessible by
133 * all DMA devices.
134 *
135 * Returns:
136 * sg_table filled with the DMA addresses to use or ERR_PRT with negative error
137 * code.
138 */
amdgpu_dma_buf_map(struct dma_buf_attachment * attach,enum dma_data_direction dir)139 static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach,
140 enum dma_data_direction dir)
141 {
142 struct dma_buf *dma_buf = attach->dmabuf;
143 struct drm_gem_object *obj = dma_buf->priv;
144 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
145 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
146 struct sg_table *sgt;
147 long r;
148
149 if (!bo->tbo.pin_count) {
150 /* move buffer into GTT or VRAM */
151 struct ttm_operation_ctx ctx = { false, false };
152 unsigned domains = AMDGPU_GEM_DOMAIN_GTT;
153
154 if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM &&
155 attach->peer2peer) {
156 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
157 domains |= AMDGPU_GEM_DOMAIN_VRAM;
158 }
159 amdgpu_bo_placement_from_domain(bo, domains);
160 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
161 if (r)
162 return ERR_PTR(r);
163
164 } else if (!(amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type) &
165 AMDGPU_GEM_DOMAIN_GTT)) {
166 return ERR_PTR(-EBUSY);
167 }
168
169 switch (bo->tbo.resource->mem_type) {
170 case TTM_PL_TT:
171 sgt = drm_prime_pages_to_sg(obj->dev,
172 bo->tbo.ttm->pages,
173 bo->tbo.ttm->num_pages);
174 if (IS_ERR(sgt))
175 return sgt;
176
177 if (dma_map_sgtable(attach->dev, sgt, dir,
178 DMA_ATTR_SKIP_CPU_SYNC))
179 goto error_free;
180 break;
181
182 case TTM_PL_VRAM:
183 r = amdgpu_vram_mgr_alloc_sgt(adev, bo->tbo.resource, 0,
184 bo->tbo.base.size, attach->dev,
185 dir, &sgt);
186 if (r)
187 return ERR_PTR(r);
188 break;
189 default:
190 return ERR_PTR(-EINVAL);
191 }
192
193 return sgt;
194
195 error_free:
196 sg_free_table(sgt);
197 kfree(sgt);
198 return ERR_PTR(-EBUSY);
199 }
200
201 /**
202 * amdgpu_dma_buf_unmap - &dma_buf_ops.unmap_dma_buf implementation
203 * @attach: DMA-buf attachment
204 * @sgt: sg_table to unmap
205 * @dir: DMA direction
206 *
207 * This is called when a shared DMA buffer no longer needs to be accessible by
208 * another device. For now, simply unpins the buffer from GTT.
209 */
amdgpu_dma_buf_unmap(struct dma_buf_attachment * attach,struct sg_table * sgt,enum dma_data_direction dir)210 static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach,
211 struct sg_table *sgt,
212 enum dma_data_direction dir)
213 {
214 if (sgt->sgl->page_link) {
215 dma_unmap_sgtable(attach->dev, sgt, dir, 0);
216 sg_free_table(sgt);
217 kfree(sgt);
218 } else {
219 amdgpu_vram_mgr_free_sgt(attach->dev, dir, sgt);
220 }
221 }
222
223 /**
224 * amdgpu_dma_buf_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation
225 * @dma_buf: Shared DMA buffer
226 * @direction: Direction of DMA transfer
227 *
228 * This is called before CPU access to the shared DMA buffer's memory. If it's
229 * a read access, the buffer is moved to the GTT domain if possible, for optimal
230 * CPU read performance.
231 *
232 * Returns:
233 * 0 on success or a negative error code on failure.
234 */
amdgpu_dma_buf_begin_cpu_access(struct dma_buf * dma_buf,enum dma_data_direction direction)235 static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf,
236 enum dma_data_direction direction)
237 {
238 struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
239 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
240 struct ttm_operation_ctx ctx = { true, false };
241 u32 domain = amdgpu_display_supported_domains(adev, bo->flags);
242 int ret;
243 bool reads = (direction == DMA_BIDIRECTIONAL ||
244 direction == DMA_FROM_DEVICE);
245
246 if (!reads || !(domain & AMDGPU_GEM_DOMAIN_GTT))
247 return 0;
248
249 /* move to gtt */
250 ret = amdgpu_bo_reserve(bo, false);
251 if (unlikely(ret != 0))
252 return ret;
253
254 if (!bo->tbo.pin_count &&
255 (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) {
256 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
257 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
258 }
259
260 amdgpu_bo_unreserve(bo);
261 return ret;
262 }
263
264 const struct dma_buf_ops amdgpu_dmabuf_ops = {
265 .attach = amdgpu_dma_buf_attach,
266 .detach = amdgpu_dma_buf_detach,
267 .pin = amdgpu_dma_buf_pin,
268 .unpin = amdgpu_dma_buf_unpin,
269 .map_dma_buf = amdgpu_dma_buf_map,
270 .unmap_dma_buf = amdgpu_dma_buf_unmap,
271 .release = drm_gem_dmabuf_release,
272 .begin_cpu_access = amdgpu_dma_buf_begin_cpu_access,
273 .mmap = drm_gem_dmabuf_mmap,
274 .vmap = drm_gem_dmabuf_vmap,
275 .vunmap = drm_gem_dmabuf_vunmap,
276 };
277
278 /**
279 * amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation
280 * @gobj: GEM BO
281 * @flags: Flags such as DRM_CLOEXEC and DRM_RDWR.
282 *
283 * The main work is done by the &drm_gem_prime_export helper.
284 *
285 * Returns:
286 * Shared DMA buffer representing the GEM BO from the given device.
287 */
amdgpu_gem_prime_export(struct drm_gem_object * gobj,int flags)288 struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj,
289 int flags)
290 {
291 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
292 struct dma_buf *buf;
293
294 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
295 bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
296 return ERR_PTR(-EPERM);
297
298 buf = drm_gem_prime_export(gobj, flags);
299 if (!IS_ERR(buf))
300 buf->ops = &amdgpu_dmabuf_ops;
301
302 return buf;
303 }
304
305 /**
306 * amdgpu_dma_buf_create_obj - create BO for DMA-buf import
307 *
308 * @dev: DRM device
309 * @dma_buf: DMA-buf
310 *
311 * Creates an empty SG BO for DMA-buf import.
312 *
313 * Returns:
314 * A new GEM BO of the given DRM device, representing the memory
315 * described by the given DMA-buf attachment and scatter/gather table.
316 */
317 static struct drm_gem_object *
amdgpu_dma_buf_create_obj(struct drm_device * dev,struct dma_buf * dma_buf)318 amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf)
319 {
320 struct dma_resv *resv = dma_buf->resv;
321 struct amdgpu_device *adev = drm_to_adev(dev);
322 struct drm_gem_object *gobj;
323 struct amdgpu_bo *bo;
324 uint64_t flags = 0;
325 int ret;
326
327 dma_resv_lock(resv, NULL);
328
329 if (dma_buf->ops == &amdgpu_dmabuf_ops) {
330 struct amdgpu_bo *other = gem_to_amdgpu_bo(dma_buf->priv);
331
332 flags |= other->flags & (AMDGPU_GEM_CREATE_CPU_GTT_USWC |
333 AMDGPU_GEM_CREATE_COHERENT |
334 AMDGPU_GEM_CREATE_UNCACHED);
335 }
336
337 ret = amdgpu_gem_object_create(adev, dma_buf->size, PAGE_SIZE,
338 AMDGPU_GEM_DOMAIN_CPU, flags,
339 ttm_bo_type_sg, resv, &gobj);
340 if (ret)
341 goto error;
342
343 bo = gem_to_amdgpu_bo(gobj);
344 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
345 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
346
347 dma_resv_unlock(resv);
348 return gobj;
349
350 error:
351 dma_resv_unlock(resv);
352 return ERR_PTR(ret);
353 }
354
355 /**
356 * amdgpu_dma_buf_move_notify - &attach.move_notify implementation
357 *
358 * @attach: the DMA-buf attachment
359 *
360 * Invalidate the DMA-buf attachment, making sure that the we re-create the
361 * mapping before the next use.
362 */
363 static void
amdgpu_dma_buf_move_notify(struct dma_buf_attachment * attach)364 amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach)
365 {
366 struct drm_gem_object *obj = attach->importer_priv;
367 struct ww_acquire_ctx *ticket = dma_resv_locking_ctx(obj->resv);
368 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
369 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
370 struct ttm_operation_ctx ctx = { false, false };
371 struct ttm_placement placement = {};
372 struct amdgpu_vm_bo_base *bo_base;
373 int r;
374
375 if (!bo->tbo.resource || bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
376 return;
377
378 r = ttm_bo_validate(&bo->tbo, &placement, &ctx);
379 if (r) {
380 DRM_ERROR("Failed to invalidate DMA-buf import (%d))\n", r);
381 return;
382 }
383
384 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
385 struct amdgpu_vm *vm = bo_base->vm;
386 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
387
388 if (ticket) {
389 /* When we get an error here it means that somebody
390 * else is holding the VM lock and updating page tables
391 * So we can just continue here.
392 */
393 r = dma_resv_lock(resv, ticket);
394 if (r)
395 continue;
396
397 } else {
398 /* TODO: This is more problematic and we actually need
399 * to allow page tables updates without holding the
400 * lock.
401 */
402 if (!dma_resv_trylock(resv))
403 continue;
404 }
405
406 r = amdgpu_vm_clear_freed(adev, vm, NULL);
407 if (!r)
408 r = amdgpu_vm_handle_moved(adev, vm);
409
410 if (r && r != -EBUSY)
411 DRM_ERROR("Failed to invalidate VM page tables (%d))\n",
412 r);
413
414 dma_resv_unlock(resv);
415 }
416 }
417
418 static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = {
419 .allow_peer2peer = true,
420 .move_notify = amdgpu_dma_buf_move_notify
421 };
422
423 /**
424 * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation
425 * @dev: DRM device
426 * @dma_buf: Shared DMA buffer
427 *
428 * Import a dma_buf into a the driver and potentially create a new GEM object.
429 *
430 * Returns:
431 * GEM BO representing the shared DMA buffer for the given device.
432 */
amdgpu_gem_prime_import(struct drm_device * dev,struct dma_buf * dma_buf)433 struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
434 struct dma_buf *dma_buf)
435 {
436 struct dma_buf_attachment *attach;
437 struct drm_gem_object *obj;
438
439 if (dma_buf->ops == &amdgpu_dmabuf_ops) {
440 obj = dma_buf->priv;
441 if (obj->dev == dev) {
442 /*
443 * Importing dmabuf exported from out own gem increases
444 * refcount on gem itself instead of f_count of dmabuf.
445 */
446 drm_gem_object_get(obj);
447 return obj;
448 }
449 }
450
451 obj = amdgpu_dma_buf_create_obj(dev, dma_buf);
452 if (IS_ERR(obj))
453 return obj;
454
455 attach = dma_buf_dynamic_attach(dma_buf, dev->dev,
456 &amdgpu_dma_buf_attach_ops, obj);
457 if (IS_ERR(attach)) {
458 drm_gem_object_put(obj);
459 return ERR_CAST(attach);
460 }
461
462 get_dma_buf(dma_buf);
463 obj->import_attach = attach;
464 return obj;
465 }
466
467 /**
468 * amdgpu_dmabuf_is_xgmi_accessible - Check if xgmi available for P2P transfer
469 *
470 * @adev: amdgpu_device pointer of the importer
471 * @bo: amdgpu buffer object
472 *
473 * Returns:
474 * True if dmabuf accessible over xgmi, false otherwise.
475 */
amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device * adev,struct amdgpu_bo * bo)476 bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev,
477 struct amdgpu_bo *bo)
478 {
479 struct drm_gem_object *obj = &bo->tbo.base;
480 struct drm_gem_object *gobj;
481
482 if (obj->import_attach) {
483 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
484
485 if (dma_buf->ops != &amdgpu_dmabuf_ops)
486 /* No XGMI with non AMD GPUs */
487 return false;
488
489 gobj = dma_buf->priv;
490 bo = gem_to_amdgpu_bo(gobj);
491 }
492
493 if (amdgpu_xgmi_same_hive(adev, amdgpu_ttm_adev(bo->tbo.bdev)) &&
494 (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM))
495 return true;
496
497 return false;
498 }
499