1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29 #include "amdgpu.h"
30 #include <drm/amdgpu_drm.h>
31 #include <drm/drm_drv.h>
32 #include <drm/drm_fb_helper.h>
33 #include "amdgpu_uvd.h"
34 #include "amdgpu_vce.h"
35 #include "atom.h"
36
37 #include <linux/vga_switcheroo.h>
38 #include <linux/slab.h>
39 #include <linux/uaccess.h>
40 #include <linux/pci.h>
41 #include <linux/pm_runtime.h>
42 #include "amdgpu_amdkfd.h"
43 #include "amdgpu_gem.h"
44 #include "amdgpu_display.h"
45 #include "amdgpu_ras.h"
46 #include "amd_pcie.h"
47
amdgpu_unregister_gpu_instance(struct amdgpu_device * adev)48 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
49 {
50 struct amdgpu_gpu_instance *gpu_instance;
51 int i;
52
53 mutex_lock(&mgpu_info.mutex);
54
55 for (i = 0; i < mgpu_info.num_gpu; i++) {
56 gpu_instance = &(mgpu_info.gpu_ins[i]);
57 if (gpu_instance->adev == adev) {
58 mgpu_info.gpu_ins[i] =
59 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
60 mgpu_info.num_gpu--;
61 if (adev->flags & AMD_IS_APU)
62 mgpu_info.num_apu--;
63 else
64 mgpu_info.num_dgpu--;
65 break;
66 }
67 }
68
69 mutex_unlock(&mgpu_info.mutex);
70 }
71
72 /**
73 * amdgpu_driver_unload_kms - Main unload function for KMS.
74 *
75 * @dev: drm dev pointer
76 *
77 * This is the main unload function for KMS (all asics).
78 * Returns 0 on success.
79 */
amdgpu_driver_unload_kms(struct drm_device * dev)80 void amdgpu_driver_unload_kms(struct drm_device *dev)
81 {
82 struct amdgpu_device *adev = drm_to_adev(dev);
83
84 if (adev == NULL)
85 return;
86
87 amdgpu_unregister_gpu_instance(adev);
88
89 if (adev->rmmio == NULL)
90 return;
91
92 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
93 DRM_WARN("smart shift update failed\n");
94
95 amdgpu_acpi_fini(adev);
96 amdgpu_device_fini_hw(adev);
97 }
98
amdgpu_register_gpu_instance(struct amdgpu_device * adev)99 void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
100 {
101 struct amdgpu_gpu_instance *gpu_instance;
102
103 mutex_lock(&mgpu_info.mutex);
104
105 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
106 DRM_ERROR("Cannot register more gpu instance\n");
107 mutex_unlock(&mgpu_info.mutex);
108 return;
109 }
110
111 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
112 gpu_instance->adev = adev;
113 gpu_instance->mgpu_fan_enabled = 0;
114
115 mgpu_info.num_gpu++;
116 if (adev->flags & AMD_IS_APU)
117 mgpu_info.num_apu++;
118 else
119 mgpu_info.num_dgpu++;
120
121 mutex_unlock(&mgpu_info.mutex);
122 }
123
124 /**
125 * amdgpu_driver_load_kms - Main load function for KMS.
126 *
127 * @adev: pointer to struct amdgpu_device
128 * @flags: device flags
129 *
130 * This is the main load function for KMS (all asics).
131 * Returns 0 on success, error on failure.
132 */
amdgpu_driver_load_kms(struct amdgpu_device * adev,unsigned long flags)133 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
134 {
135 struct drm_device *dev;
136 int r, acpi_status;
137
138 dev = adev_to_drm(adev);
139
140 /* amdgpu_device_init should report only fatal error
141 * like memory allocation failure or iomapping failure,
142 * or memory manager initialization failure, it must
143 * properly initialize the GPU MC controller and permit
144 * VRAM allocation
145 */
146 r = amdgpu_device_init(adev, flags);
147 if (r) {
148 dev_err(dev->dev, "Fatal error during GPU init\n");
149 goto out;
150 }
151
152 adev->pm.rpm_mode = AMDGPU_RUNPM_NONE;
153 if (amdgpu_device_supports_px(dev) &&
154 (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */
155 adev->pm.rpm_mode = AMDGPU_RUNPM_PX;
156 dev_info(adev->dev, "Using ATPX for runtime pm\n");
157 } else if (amdgpu_device_supports_boco(dev) &&
158 (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */
159 adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO;
160 dev_info(adev->dev, "Using BOCO for runtime pm\n");
161 } else if (amdgpu_device_supports_baco(dev) &&
162 (amdgpu_runtime_pm != 0)) {
163 switch (adev->asic_type) {
164 case CHIP_VEGA20:
165 case CHIP_ARCTURUS:
166 /* enable BACO as runpm mode if runpm=1 */
167 if (amdgpu_runtime_pm > 0)
168 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
169 break;
170 case CHIP_VEGA10:
171 /* enable BACO as runpm mode if noretry=0 */
172 if (!adev->gmc.noretry)
173 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
174 break;
175 default:
176 /* enable BACO as runpm mode on CI+ */
177 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO;
178 break;
179 }
180
181 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)
182 dev_info(adev->dev, "Using BACO for runtime pm\n");
183 }
184
185 /* Call ACPI methods: require modeset init
186 * but failure is not fatal
187 */
188
189 acpi_status = amdgpu_acpi_init(adev);
190 if (acpi_status)
191 dev_dbg(dev->dev, "Error during ACPI methods call\n");
192
193 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
194 DRM_WARN("smart shift update failed\n");
195
196 out:
197 if (r)
198 amdgpu_driver_unload_kms(dev);
199
200 return r;
201 }
202
amdgpu_firmware_info(struct drm_amdgpu_info_firmware * fw_info,struct drm_amdgpu_query_fw * query_fw,struct amdgpu_device * adev)203 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
204 struct drm_amdgpu_query_fw *query_fw,
205 struct amdgpu_device *adev)
206 {
207 switch (query_fw->fw_type) {
208 case AMDGPU_INFO_FW_VCE:
209 fw_info->ver = adev->vce.fw_version;
210 fw_info->feature = adev->vce.fb_version;
211 break;
212 case AMDGPU_INFO_FW_UVD:
213 fw_info->ver = adev->uvd.fw_version;
214 fw_info->feature = 0;
215 break;
216 case AMDGPU_INFO_FW_VCN:
217 fw_info->ver = adev->vcn.fw_version;
218 fw_info->feature = 0;
219 break;
220 case AMDGPU_INFO_FW_GMC:
221 fw_info->ver = adev->gmc.fw_version;
222 fw_info->feature = 0;
223 break;
224 case AMDGPU_INFO_FW_GFX_ME:
225 fw_info->ver = adev->gfx.me_fw_version;
226 fw_info->feature = adev->gfx.me_feature_version;
227 break;
228 case AMDGPU_INFO_FW_GFX_PFP:
229 fw_info->ver = adev->gfx.pfp_fw_version;
230 fw_info->feature = adev->gfx.pfp_feature_version;
231 break;
232 case AMDGPU_INFO_FW_GFX_CE:
233 fw_info->ver = adev->gfx.ce_fw_version;
234 fw_info->feature = adev->gfx.ce_feature_version;
235 break;
236 case AMDGPU_INFO_FW_GFX_RLC:
237 fw_info->ver = adev->gfx.rlc_fw_version;
238 fw_info->feature = adev->gfx.rlc_feature_version;
239 break;
240 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
241 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
242 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
243 break;
244 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
245 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
246 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
247 break;
248 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
249 fw_info->ver = adev->gfx.rlc_srls_fw_version;
250 fw_info->feature = adev->gfx.rlc_srls_feature_version;
251 break;
252 case AMDGPU_INFO_FW_GFX_RLCP:
253 fw_info->ver = adev->gfx.rlcp_ucode_version;
254 fw_info->feature = adev->gfx.rlcp_ucode_feature_version;
255 break;
256 case AMDGPU_INFO_FW_GFX_RLCV:
257 fw_info->ver = adev->gfx.rlcv_ucode_version;
258 fw_info->feature = adev->gfx.rlcv_ucode_feature_version;
259 break;
260 case AMDGPU_INFO_FW_GFX_MEC:
261 if (query_fw->index == 0) {
262 fw_info->ver = adev->gfx.mec_fw_version;
263 fw_info->feature = adev->gfx.mec_feature_version;
264 } else if (query_fw->index == 1) {
265 fw_info->ver = adev->gfx.mec2_fw_version;
266 fw_info->feature = adev->gfx.mec2_feature_version;
267 } else
268 return -EINVAL;
269 break;
270 case AMDGPU_INFO_FW_SMC:
271 fw_info->ver = adev->pm.fw_version;
272 fw_info->feature = 0;
273 break;
274 case AMDGPU_INFO_FW_TA:
275 switch (query_fw->index) {
276 case TA_FW_TYPE_PSP_XGMI:
277 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version;
278 fw_info->feature = adev->psp.xgmi_context.context
279 .bin_desc.feature_version;
280 break;
281 case TA_FW_TYPE_PSP_RAS:
282 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version;
283 fw_info->feature = adev->psp.ras_context.context
284 .bin_desc.feature_version;
285 break;
286 case TA_FW_TYPE_PSP_HDCP:
287 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version;
288 fw_info->feature = adev->psp.hdcp_context.context
289 .bin_desc.feature_version;
290 break;
291 case TA_FW_TYPE_PSP_DTM:
292 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version;
293 fw_info->feature = adev->psp.dtm_context.context
294 .bin_desc.feature_version;
295 break;
296 case TA_FW_TYPE_PSP_RAP:
297 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version;
298 fw_info->feature = adev->psp.rap_context.context
299 .bin_desc.feature_version;
300 break;
301 case TA_FW_TYPE_PSP_SECUREDISPLAY:
302 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version;
303 fw_info->feature =
304 adev->psp.securedisplay_context.context.bin_desc
305 .feature_version;
306 break;
307 default:
308 return -EINVAL;
309 }
310 break;
311 case AMDGPU_INFO_FW_SDMA:
312 if (query_fw->index >= adev->sdma.num_instances)
313 return -EINVAL;
314 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
315 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
316 break;
317 case AMDGPU_INFO_FW_SOS:
318 fw_info->ver = adev->psp.sos.fw_version;
319 fw_info->feature = adev->psp.sos.feature_version;
320 break;
321 case AMDGPU_INFO_FW_ASD:
322 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version;
323 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version;
324 break;
325 case AMDGPU_INFO_FW_DMCU:
326 fw_info->ver = adev->dm.dmcu_fw_version;
327 fw_info->feature = 0;
328 break;
329 case AMDGPU_INFO_FW_DMCUB:
330 fw_info->ver = adev->dm.dmcub_fw_version;
331 fw_info->feature = 0;
332 break;
333 case AMDGPU_INFO_FW_TOC:
334 fw_info->ver = adev->psp.toc.fw_version;
335 fw_info->feature = adev->psp.toc.feature_version;
336 break;
337 case AMDGPU_INFO_FW_CAP:
338 fw_info->ver = adev->psp.cap_fw_version;
339 fw_info->feature = adev->psp.cap_feature_version;
340 break;
341 case AMDGPU_INFO_FW_MES_KIQ:
342 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK;
343 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK)
344 >> AMDGPU_MES_FEAT_VERSION_SHIFT;
345 break;
346 case AMDGPU_INFO_FW_MES:
347 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK;
348 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK)
349 >> AMDGPU_MES_FEAT_VERSION_SHIFT;
350 break;
351 case AMDGPU_INFO_FW_IMU:
352 fw_info->ver = adev->gfx.imu_fw_version;
353 fw_info->feature = 0;
354 break;
355 default:
356 return -EINVAL;
357 }
358 return 0;
359 }
360
amdgpu_hw_ip_info(struct amdgpu_device * adev,struct drm_amdgpu_info * info,struct drm_amdgpu_info_hw_ip * result)361 static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
362 struct drm_amdgpu_info *info,
363 struct drm_amdgpu_info_hw_ip *result)
364 {
365 uint32_t ib_start_alignment = 0;
366 uint32_t ib_size_alignment = 0;
367 enum amd_ip_block_type type;
368 unsigned int num_rings = 0;
369 unsigned int i, j;
370
371 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
372 return -EINVAL;
373
374 switch (info->query_hw_ip.type) {
375 case AMDGPU_HW_IP_GFX:
376 type = AMD_IP_BLOCK_TYPE_GFX;
377 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
378 if (adev->gfx.gfx_ring[i].sched.ready)
379 ++num_rings;
380 ib_start_alignment = 32;
381 ib_size_alignment = 32;
382 break;
383 case AMDGPU_HW_IP_COMPUTE:
384 type = AMD_IP_BLOCK_TYPE_GFX;
385 for (i = 0; i < adev->gfx.num_compute_rings; i++)
386 if (adev->gfx.compute_ring[i].sched.ready)
387 ++num_rings;
388 ib_start_alignment = 32;
389 ib_size_alignment = 32;
390 break;
391 case AMDGPU_HW_IP_DMA:
392 type = AMD_IP_BLOCK_TYPE_SDMA;
393 for (i = 0; i < adev->sdma.num_instances; i++)
394 if (adev->sdma.instance[i].ring.sched.ready)
395 ++num_rings;
396 ib_start_alignment = 256;
397 ib_size_alignment = 4;
398 break;
399 case AMDGPU_HW_IP_UVD:
400 type = AMD_IP_BLOCK_TYPE_UVD;
401 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
402 if (adev->uvd.harvest_config & (1 << i))
403 continue;
404
405 if (adev->uvd.inst[i].ring.sched.ready)
406 ++num_rings;
407 }
408 ib_start_alignment = 64;
409 ib_size_alignment = 64;
410 break;
411 case AMDGPU_HW_IP_VCE:
412 type = AMD_IP_BLOCK_TYPE_VCE;
413 for (i = 0; i < adev->vce.num_rings; i++)
414 if (adev->vce.ring[i].sched.ready)
415 ++num_rings;
416 ib_start_alignment = 4;
417 ib_size_alignment = 1;
418 break;
419 case AMDGPU_HW_IP_UVD_ENC:
420 type = AMD_IP_BLOCK_TYPE_UVD;
421 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
422 if (adev->uvd.harvest_config & (1 << i))
423 continue;
424
425 for (j = 0; j < adev->uvd.num_enc_rings; j++)
426 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
427 ++num_rings;
428 }
429 ib_start_alignment = 64;
430 ib_size_alignment = 64;
431 break;
432 case AMDGPU_HW_IP_VCN_DEC:
433 type = AMD_IP_BLOCK_TYPE_VCN;
434 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
435 if (adev->vcn.harvest_config & (1 << i))
436 continue;
437
438 if (adev->vcn.inst[i].ring_dec.sched.ready)
439 ++num_rings;
440 }
441 ib_start_alignment = 16;
442 ib_size_alignment = 16;
443 break;
444 case AMDGPU_HW_IP_VCN_ENC:
445 type = AMD_IP_BLOCK_TYPE_VCN;
446 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
447 if (adev->vcn.harvest_config & (1 << i))
448 continue;
449
450 for (j = 0; j < adev->vcn.num_enc_rings; j++)
451 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
452 ++num_rings;
453 }
454 ib_start_alignment = 64;
455 ib_size_alignment = 1;
456 break;
457 case AMDGPU_HW_IP_VCN_JPEG:
458 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
459 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
460
461 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
462 if (adev->jpeg.harvest_config & (1 << i))
463 continue;
464
465 if (adev->jpeg.inst[i].ring_dec.sched.ready)
466 ++num_rings;
467 }
468 ib_start_alignment = 16;
469 ib_size_alignment = 16;
470 break;
471 default:
472 return -EINVAL;
473 }
474
475 for (i = 0; i < adev->num_ip_blocks; i++)
476 if (adev->ip_blocks[i].version->type == type &&
477 adev->ip_blocks[i].status.valid)
478 break;
479
480 if (i == adev->num_ip_blocks)
481 return 0;
482
483 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
484 num_rings);
485
486 result->hw_ip_version_major = adev->ip_blocks[i].version->major;
487 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
488
489 if (adev->asic_type >= CHIP_VEGA10) {
490 switch (type) {
491 case AMD_IP_BLOCK_TYPE_GFX:
492 result->ip_discovery_version = adev->ip_versions[GC_HWIP][0];
493 break;
494 case AMD_IP_BLOCK_TYPE_SDMA:
495 result->ip_discovery_version = adev->ip_versions[SDMA0_HWIP][0];
496 break;
497 case AMD_IP_BLOCK_TYPE_UVD:
498 case AMD_IP_BLOCK_TYPE_VCN:
499 case AMD_IP_BLOCK_TYPE_JPEG:
500 result->ip_discovery_version = adev->ip_versions[UVD_HWIP][0];
501 break;
502 case AMD_IP_BLOCK_TYPE_VCE:
503 result->ip_discovery_version = adev->ip_versions[VCE_HWIP][0];
504 break;
505 default:
506 result->ip_discovery_version = 0;
507 break;
508 }
509 } else {
510 result->ip_discovery_version = 0;
511 }
512 result->capabilities_flags = 0;
513 result->available_rings = (1 << num_rings) - 1;
514 result->ib_start_alignment = ib_start_alignment;
515 result->ib_size_alignment = ib_size_alignment;
516 return 0;
517 }
518
519 /*
520 * Userspace get information ioctl
521 */
522 /**
523 * amdgpu_info_ioctl - answer a device specific request.
524 *
525 * @dev: drm device pointer
526 * @data: request object
527 * @filp: drm filp
528 *
529 * This function is used to pass device specific parameters to the userspace
530 * drivers. Examples include: pci device id, pipeline parms, tiling params,
531 * etc. (all asics).
532 * Returns 0 on success, -EINVAL on failure.
533 */
amdgpu_info_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)534 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
535 {
536 struct amdgpu_device *adev = drm_to_adev(dev);
537 struct drm_amdgpu_info *info = data;
538 struct amdgpu_mode_info *minfo = &adev->mode_info;
539 void __user *out = (void __user *)(uintptr_t)info->return_pointer;
540 uint32_t size = info->return_size;
541 struct drm_crtc *crtc;
542 uint32_t ui32 = 0;
543 uint64_t ui64 = 0;
544 int i, found;
545 int ui32_size = sizeof(ui32);
546
547 if (!info->return_size || !info->return_pointer)
548 return -EINVAL;
549
550 switch (info->query) {
551 case AMDGPU_INFO_ACCEL_WORKING:
552 ui32 = adev->accel_working;
553 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
554 case AMDGPU_INFO_CRTC_FROM_ID:
555 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
556 crtc = (struct drm_crtc *)minfo->crtcs[i];
557 if (crtc && crtc->base.id == info->mode_crtc.id) {
558 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
559 ui32 = amdgpu_crtc->crtc_id;
560 found = 1;
561 break;
562 }
563 }
564 if (!found) {
565 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
566 return -EINVAL;
567 }
568 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
569 case AMDGPU_INFO_HW_IP_INFO: {
570 struct drm_amdgpu_info_hw_ip ip = {};
571 int ret;
572
573 ret = amdgpu_hw_ip_info(adev, info, &ip);
574 if (ret)
575 return ret;
576
577 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
578 return ret ? -EFAULT : 0;
579 }
580 case AMDGPU_INFO_HW_IP_COUNT: {
581 enum amd_ip_block_type type;
582 uint32_t count = 0;
583
584 switch (info->query_hw_ip.type) {
585 case AMDGPU_HW_IP_GFX:
586 type = AMD_IP_BLOCK_TYPE_GFX;
587 break;
588 case AMDGPU_HW_IP_COMPUTE:
589 type = AMD_IP_BLOCK_TYPE_GFX;
590 break;
591 case AMDGPU_HW_IP_DMA:
592 type = AMD_IP_BLOCK_TYPE_SDMA;
593 break;
594 case AMDGPU_HW_IP_UVD:
595 type = AMD_IP_BLOCK_TYPE_UVD;
596 break;
597 case AMDGPU_HW_IP_VCE:
598 type = AMD_IP_BLOCK_TYPE_VCE;
599 break;
600 case AMDGPU_HW_IP_UVD_ENC:
601 type = AMD_IP_BLOCK_TYPE_UVD;
602 break;
603 case AMDGPU_HW_IP_VCN_DEC:
604 case AMDGPU_HW_IP_VCN_ENC:
605 type = AMD_IP_BLOCK_TYPE_VCN;
606 break;
607 case AMDGPU_HW_IP_VCN_JPEG:
608 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
609 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
610 break;
611 default:
612 return -EINVAL;
613 }
614
615 for (i = 0; i < adev->num_ip_blocks; i++)
616 if (adev->ip_blocks[i].version->type == type &&
617 adev->ip_blocks[i].status.valid &&
618 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
619 count++;
620
621 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
622 }
623 case AMDGPU_INFO_TIMESTAMP:
624 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
625 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
626 case AMDGPU_INFO_FW_VERSION: {
627 struct drm_amdgpu_info_firmware fw_info;
628 int ret;
629
630 /* We only support one instance of each IP block right now. */
631 if (info->query_fw.ip_instance != 0)
632 return -EINVAL;
633
634 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
635 if (ret)
636 return ret;
637
638 return copy_to_user(out, &fw_info,
639 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
640 }
641 case AMDGPU_INFO_NUM_BYTES_MOVED:
642 ui64 = atomic64_read(&adev->num_bytes_moved);
643 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
644 case AMDGPU_INFO_NUM_EVICTIONS:
645 ui64 = atomic64_read(&adev->num_evictions);
646 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
647 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
648 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
649 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
650 case AMDGPU_INFO_VRAM_USAGE:
651 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
652 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
653 case AMDGPU_INFO_VIS_VRAM_USAGE:
654 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
655 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
656 case AMDGPU_INFO_GTT_USAGE:
657 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager);
658 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
659 case AMDGPU_INFO_GDS_CONFIG: {
660 struct drm_amdgpu_info_gds gds_info;
661
662 memset(&gds_info, 0, sizeof(gds_info));
663 gds_info.compute_partition_size = adev->gds.gds_size;
664 gds_info.gds_total_size = adev->gds.gds_size;
665 gds_info.gws_per_compute_partition = adev->gds.gws_size;
666 gds_info.oa_per_compute_partition = adev->gds.oa_size;
667 return copy_to_user(out, &gds_info,
668 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
669 }
670 case AMDGPU_INFO_VRAM_GTT: {
671 struct drm_amdgpu_info_vram_gtt vram_gtt;
672
673 vram_gtt.vram_size = adev->gmc.real_vram_size -
674 atomic64_read(&adev->vram_pin_size) -
675 AMDGPU_VM_RESERVED_VRAM;
676 vram_gtt.vram_cpu_accessible_size =
677 min(adev->gmc.visible_vram_size -
678 atomic64_read(&adev->visible_pin_size),
679 vram_gtt.vram_size);
680 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
681 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
682 return copy_to_user(out, &vram_gtt,
683 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
684 }
685 case AMDGPU_INFO_MEMORY: {
686 struct drm_amdgpu_memory_info mem;
687 struct ttm_resource_manager *gtt_man =
688 &adev->mman.gtt_mgr.manager;
689 struct ttm_resource_manager *vram_man =
690 &adev->mman.vram_mgr.manager;
691
692 memset(&mem, 0, sizeof(mem));
693 mem.vram.total_heap_size = adev->gmc.real_vram_size;
694 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
695 atomic64_read(&adev->vram_pin_size) -
696 AMDGPU_VM_RESERVED_VRAM;
697 mem.vram.heap_usage =
698 ttm_resource_manager_usage(vram_man);
699 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
700
701 mem.cpu_accessible_vram.total_heap_size =
702 adev->gmc.visible_vram_size;
703 mem.cpu_accessible_vram.usable_heap_size =
704 min(adev->gmc.visible_vram_size -
705 atomic64_read(&adev->visible_pin_size),
706 mem.vram.usable_heap_size);
707 mem.cpu_accessible_vram.heap_usage =
708 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
709 mem.cpu_accessible_vram.max_allocation =
710 mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
711
712 mem.gtt.total_heap_size = gtt_man->size;
713 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
714 atomic64_read(&adev->gart_pin_size);
715 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man);
716 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
717
718 return copy_to_user(out, &mem,
719 min((size_t)size, sizeof(mem)))
720 ? -EFAULT : 0;
721 }
722 case AMDGPU_INFO_READ_MMR_REG: {
723 unsigned n, alloc_size;
724 uint32_t *regs;
725 unsigned se_num = (info->read_mmr_reg.instance >>
726 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
727 AMDGPU_INFO_MMR_SE_INDEX_MASK;
728 unsigned sh_num = (info->read_mmr_reg.instance >>
729 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
730 AMDGPU_INFO_MMR_SH_INDEX_MASK;
731
732 /* set full masks if the userspace set all bits
733 * in the bitfields */
734 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
735 se_num = 0xffffffff;
736 else if (se_num >= AMDGPU_GFX_MAX_SE)
737 return -EINVAL;
738 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
739 sh_num = 0xffffffff;
740 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
741 return -EINVAL;
742
743 if (info->read_mmr_reg.count > 128)
744 return -EINVAL;
745
746 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
747 if (!regs)
748 return -ENOMEM;
749 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
750
751 amdgpu_gfx_off_ctrl(adev, false);
752 for (i = 0; i < info->read_mmr_reg.count; i++) {
753 if (amdgpu_asic_read_register(adev, se_num, sh_num,
754 info->read_mmr_reg.dword_offset + i,
755 ®s[i])) {
756 DRM_DEBUG_KMS("unallowed offset %#x\n",
757 info->read_mmr_reg.dword_offset + i);
758 kfree(regs);
759 amdgpu_gfx_off_ctrl(adev, true);
760 return -EFAULT;
761 }
762 }
763 amdgpu_gfx_off_ctrl(adev, true);
764 n = copy_to_user(out, regs, min(size, alloc_size));
765 kfree(regs);
766 return n ? -EFAULT : 0;
767 }
768 case AMDGPU_INFO_DEV_INFO: {
769 struct drm_amdgpu_info_device *dev_info;
770 uint64_t vm_size;
771 uint32_t pcie_gen_mask;
772 int ret;
773
774 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
775 if (!dev_info)
776 return -ENOMEM;
777
778 dev_info->device_id = adev->pdev->device;
779 dev_info->chip_rev = adev->rev_id;
780 dev_info->external_rev = adev->external_rev_id;
781 dev_info->pci_rev = adev->pdev->revision;
782 dev_info->family = adev->family;
783 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
784 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
785 /* return all clocks in KHz */
786 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
787 if (adev->pm.dpm_enabled) {
788 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
789 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
790 dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10;
791 dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10;
792 } else {
793 dev_info->max_engine_clock =
794 dev_info->min_engine_clock =
795 adev->clock.default_sclk * 10;
796 dev_info->max_memory_clock =
797 dev_info->min_memory_clock =
798 adev->clock.default_mclk * 10;
799 }
800 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
801 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
802 adev->gfx.config.max_shader_engines;
803 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
804 dev_info->ids_flags = 0;
805 if (adev->flags & AMD_IS_APU)
806 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
807 if (amdgpu_mcbp)
808 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
809 if (amdgpu_is_tmz(adev))
810 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
811 if (adev->gfx.config.ta_cntl2_truncate_coord_mode)
812 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD;
813
814 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
815 vm_size -= AMDGPU_VA_RESERVED_SIZE;
816
817 /* Older VCE FW versions are buggy and can handle only 40bits */
818 if (adev->vce.fw_version &&
819 adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
820 vm_size = min(vm_size, 1ULL << 40);
821
822 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
823 dev_info->virtual_address_max =
824 min(vm_size, AMDGPU_GMC_HOLE_START);
825
826 if (vm_size > AMDGPU_GMC_HOLE_START) {
827 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
828 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
829 }
830 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
831 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
832 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
833 dev_info->cu_active_number = adev->gfx.cu_info.number;
834 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
835 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
836 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
837 sizeof(adev->gfx.cu_info.ao_cu_bitmap));
838 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
839 sizeof(adev->gfx.cu_info.bitmap));
840 dev_info->vram_type = adev->gmc.vram_type;
841 dev_info->vram_bit_width = adev->gmc.vram_width;
842 dev_info->vce_harvest_config = adev->vce.harvest_config;
843 dev_info->gc_double_offchip_lds_buf =
844 adev->gfx.config.double_offchip_lds_buf;
845 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
846 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
847 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
848 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
849 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
850 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
851 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
852
853 if (adev->family >= AMDGPU_FAMILY_NV)
854 dev_info->pa_sc_tile_steering_override =
855 adev->gfx.config.pa_sc_tile_steering_override;
856
857 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
858
859 /* Combine the chip gen mask with the platform (CPU/mobo) mask. */
860 pcie_gen_mask = adev->pm.pcie_gen_mask & (adev->pm.pcie_gen_mask >> 16);
861 dev_info->pcie_gen = fls(pcie_gen_mask);
862 dev_info->pcie_num_lanes =
863 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 :
864 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 :
865 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 :
866 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 :
867 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 :
868 adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1;
869
870 dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size;
871 dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp;
872 dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc;
873 dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc;
874 dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance *
875 adev->gfx.config.gc_gl1c_per_sa;
876 dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu;
877 dev_info->mall_size = adev->gmc.mall_size;
878
879 ret = copy_to_user(out, dev_info,
880 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
881 kfree(dev_info);
882 return ret;
883 }
884 case AMDGPU_INFO_VCE_CLOCK_TABLE: {
885 unsigned i;
886 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
887 struct amd_vce_state *vce_state;
888
889 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
890 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
891 if (vce_state) {
892 vce_clk_table.entries[i].sclk = vce_state->sclk;
893 vce_clk_table.entries[i].mclk = vce_state->mclk;
894 vce_clk_table.entries[i].eclk = vce_state->evclk;
895 vce_clk_table.num_valid_entries++;
896 }
897 }
898
899 return copy_to_user(out, &vce_clk_table,
900 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
901 }
902 case AMDGPU_INFO_VBIOS: {
903 uint32_t bios_size = adev->bios_size;
904
905 switch (info->vbios_info.type) {
906 case AMDGPU_INFO_VBIOS_SIZE:
907 return copy_to_user(out, &bios_size,
908 min((size_t)size, sizeof(bios_size)))
909 ? -EFAULT : 0;
910 case AMDGPU_INFO_VBIOS_IMAGE: {
911 uint8_t *bios;
912 uint32_t bios_offset = info->vbios_info.offset;
913
914 if (bios_offset >= bios_size)
915 return -EINVAL;
916
917 bios = adev->bios + bios_offset;
918 return copy_to_user(out, bios,
919 min((size_t)size, (size_t)(bios_size - bios_offset)))
920 ? -EFAULT : 0;
921 }
922 case AMDGPU_INFO_VBIOS_INFO: {
923 struct drm_amdgpu_info_vbios vbios_info = {};
924 struct atom_context *atom_context;
925
926 atom_context = adev->mode_info.atom_context;
927 memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name));
928 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn));
929 vbios_info.version = atom_context->version;
930 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
931 sizeof(atom_context->vbios_ver_str));
932 memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date));
933
934 return copy_to_user(out, &vbios_info,
935 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
936 }
937 default:
938 DRM_DEBUG_KMS("Invalid request %d\n",
939 info->vbios_info.type);
940 return -EINVAL;
941 }
942 }
943 case AMDGPU_INFO_NUM_HANDLES: {
944 struct drm_amdgpu_info_num_handles handle;
945
946 switch (info->query_hw_ip.type) {
947 case AMDGPU_HW_IP_UVD:
948 /* Starting Polaris, we support unlimited UVD handles */
949 if (adev->asic_type < CHIP_POLARIS10) {
950 handle.uvd_max_handles = adev->uvd.max_handles;
951 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
952
953 return copy_to_user(out, &handle,
954 min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
955 } else {
956 return -ENODATA;
957 }
958
959 break;
960 default:
961 return -EINVAL;
962 }
963 }
964 case AMDGPU_INFO_SENSOR: {
965 if (!adev->pm.dpm_enabled)
966 return -ENOENT;
967
968 switch (info->sensor_info.type) {
969 case AMDGPU_INFO_SENSOR_GFX_SCLK:
970 /* get sclk in Mhz */
971 if (amdgpu_dpm_read_sensor(adev,
972 AMDGPU_PP_SENSOR_GFX_SCLK,
973 (void *)&ui32, &ui32_size)) {
974 return -EINVAL;
975 }
976 ui32 /= 100;
977 break;
978 case AMDGPU_INFO_SENSOR_GFX_MCLK:
979 /* get mclk in Mhz */
980 if (amdgpu_dpm_read_sensor(adev,
981 AMDGPU_PP_SENSOR_GFX_MCLK,
982 (void *)&ui32, &ui32_size)) {
983 return -EINVAL;
984 }
985 ui32 /= 100;
986 break;
987 case AMDGPU_INFO_SENSOR_GPU_TEMP:
988 /* get temperature in millidegrees C */
989 if (amdgpu_dpm_read_sensor(adev,
990 AMDGPU_PP_SENSOR_GPU_TEMP,
991 (void *)&ui32, &ui32_size)) {
992 return -EINVAL;
993 }
994 break;
995 case AMDGPU_INFO_SENSOR_GPU_LOAD:
996 /* get GPU load */
997 if (amdgpu_dpm_read_sensor(adev,
998 AMDGPU_PP_SENSOR_GPU_LOAD,
999 (void *)&ui32, &ui32_size)) {
1000 return -EINVAL;
1001 }
1002 break;
1003 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
1004 /* get average GPU power */
1005 if (amdgpu_dpm_read_sensor(adev,
1006 AMDGPU_PP_SENSOR_GPU_POWER,
1007 (void *)&ui32, &ui32_size)) {
1008 return -EINVAL;
1009 }
1010 ui32 >>= 8;
1011 break;
1012 case AMDGPU_INFO_SENSOR_VDDNB:
1013 /* get VDDNB in millivolts */
1014 if (amdgpu_dpm_read_sensor(adev,
1015 AMDGPU_PP_SENSOR_VDDNB,
1016 (void *)&ui32, &ui32_size)) {
1017 return -EINVAL;
1018 }
1019 break;
1020 case AMDGPU_INFO_SENSOR_VDDGFX:
1021 /* get VDDGFX in millivolts */
1022 if (amdgpu_dpm_read_sensor(adev,
1023 AMDGPU_PP_SENSOR_VDDGFX,
1024 (void *)&ui32, &ui32_size)) {
1025 return -EINVAL;
1026 }
1027 break;
1028 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
1029 /* get stable pstate sclk in Mhz */
1030 if (amdgpu_dpm_read_sensor(adev,
1031 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
1032 (void *)&ui32, &ui32_size)) {
1033 return -EINVAL;
1034 }
1035 ui32 /= 100;
1036 break;
1037 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
1038 /* get stable pstate mclk in Mhz */
1039 if (amdgpu_dpm_read_sensor(adev,
1040 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
1041 (void *)&ui32, &ui32_size)) {
1042 return -EINVAL;
1043 }
1044 ui32 /= 100;
1045 break;
1046 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK:
1047 /* get peak pstate sclk in Mhz */
1048 if (amdgpu_dpm_read_sensor(adev,
1049 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
1050 (void *)&ui32, &ui32_size)) {
1051 return -EINVAL;
1052 }
1053 ui32 /= 100;
1054 break;
1055 case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK:
1056 /* get peak pstate mclk in Mhz */
1057 if (amdgpu_dpm_read_sensor(adev,
1058 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
1059 (void *)&ui32, &ui32_size)) {
1060 return -EINVAL;
1061 }
1062 ui32 /= 100;
1063 break;
1064 default:
1065 DRM_DEBUG_KMS("Invalid request %d\n",
1066 info->sensor_info.type);
1067 return -EINVAL;
1068 }
1069 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1070 }
1071 case AMDGPU_INFO_VRAM_LOST_COUNTER:
1072 ui32 = atomic_read(&adev->vram_lost_counter);
1073 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1074 case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
1075 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1076 uint64_t ras_mask;
1077
1078 if (!ras)
1079 return -EINVAL;
1080 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
1081
1082 return copy_to_user(out, &ras_mask,
1083 min_t(u64, size, sizeof(ras_mask))) ?
1084 -EFAULT : 0;
1085 }
1086 case AMDGPU_INFO_VIDEO_CAPS: {
1087 const struct amdgpu_video_codecs *codecs;
1088 struct drm_amdgpu_info_video_caps *caps;
1089 int r;
1090
1091 switch (info->video_cap.type) {
1092 case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1093 r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1094 if (r)
1095 return -EINVAL;
1096 break;
1097 case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1098 r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1099 if (r)
1100 return -EINVAL;
1101 break;
1102 default:
1103 DRM_DEBUG_KMS("Invalid request %d\n",
1104 info->video_cap.type);
1105 return -EINVAL;
1106 }
1107
1108 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1109 if (!caps)
1110 return -ENOMEM;
1111
1112 for (i = 0; i < codecs->codec_count; i++) {
1113 int idx = codecs->codec_array[i].codec_type;
1114
1115 switch (idx) {
1116 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1117 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1118 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1119 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1120 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1121 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1122 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1123 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1124 caps->codec_info[idx].valid = 1;
1125 caps->codec_info[idx].max_width =
1126 codecs->codec_array[i].max_width;
1127 caps->codec_info[idx].max_height =
1128 codecs->codec_array[i].max_height;
1129 caps->codec_info[idx].max_pixels_per_frame =
1130 codecs->codec_array[i].max_pixels_per_frame;
1131 caps->codec_info[idx].max_level =
1132 codecs->codec_array[i].max_level;
1133 break;
1134 default:
1135 break;
1136 }
1137 }
1138 r = copy_to_user(out, caps,
1139 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1140 kfree(caps);
1141 return r;
1142 }
1143 default:
1144 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1145 return -EINVAL;
1146 }
1147 return 0;
1148 }
1149
1150
1151 /*
1152 * Outdated mess for old drm with Xorg being in charge (void function now).
1153 */
1154 /**
1155 * amdgpu_driver_lastclose_kms - drm callback for last close
1156 *
1157 * @dev: drm dev pointer
1158 *
1159 * Switch vga_switcheroo state after last close (all asics).
1160 */
amdgpu_driver_lastclose_kms(struct drm_device * dev)1161 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
1162 {
1163 drm_fb_helper_lastclose(dev);
1164 vga_switcheroo_process_delayed_switch();
1165 }
1166
1167 /**
1168 * amdgpu_driver_open_kms - drm callback for open
1169 *
1170 * @dev: drm dev pointer
1171 * @file_priv: drm file
1172 *
1173 * On device open, init vm on cayman+ (all asics).
1174 * Returns 0 on success, error on failure.
1175 */
amdgpu_driver_open_kms(struct drm_device * dev,struct drm_file * file_priv)1176 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1177 {
1178 struct amdgpu_device *adev = drm_to_adev(dev);
1179 struct amdgpu_fpriv *fpriv;
1180 int r, pasid;
1181
1182 /* Ensure IB tests are run on ring */
1183 flush_delayed_work(&adev->delayed_init_work);
1184
1185
1186 if (amdgpu_ras_intr_triggered()) {
1187 DRM_ERROR("RAS Intr triggered, device disabled!!");
1188 return -EHWPOISON;
1189 }
1190
1191 file_priv->driver_priv = NULL;
1192
1193 r = pm_runtime_get_sync(dev->dev);
1194 if (r < 0)
1195 goto pm_put;
1196
1197 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1198 if (unlikely(!fpriv)) {
1199 r = -ENOMEM;
1200 goto out_suspend;
1201 }
1202
1203 pasid = amdgpu_pasid_alloc(16);
1204 if (pasid < 0) {
1205 dev_warn(adev->dev, "No more PASIDs available!");
1206 pasid = 0;
1207 }
1208
1209 r = amdgpu_vm_init(adev, &fpriv->vm);
1210 if (r)
1211 goto error_pasid;
1212
1213 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid);
1214 if (r)
1215 goto error_vm;
1216
1217 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1218 if (!fpriv->prt_va) {
1219 r = -ENOMEM;
1220 goto error_vm;
1221 }
1222
1223 if (amdgpu_mcbp) {
1224 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1225
1226 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1227 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1228 if (r)
1229 goto error_vm;
1230 }
1231
1232 mutex_init(&fpriv->bo_list_lock);
1233 idr_init_base(&fpriv->bo_list_handles, 1);
1234
1235 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev);
1236
1237 file_priv->driver_priv = fpriv;
1238 goto out_suspend;
1239
1240 error_vm:
1241 amdgpu_vm_fini(adev, &fpriv->vm);
1242
1243 error_pasid:
1244 if (pasid) {
1245 amdgpu_pasid_free(pasid);
1246 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0);
1247 }
1248
1249 kfree(fpriv);
1250
1251 out_suspend:
1252 pm_runtime_mark_last_busy(dev->dev);
1253 pm_put:
1254 pm_runtime_put_autosuspend(dev->dev);
1255
1256 return r;
1257 }
1258
1259 /**
1260 * amdgpu_driver_postclose_kms - drm callback for post close
1261 *
1262 * @dev: drm dev pointer
1263 * @file_priv: drm file
1264 *
1265 * On device post close, tear down vm on cayman+ (all asics).
1266 */
amdgpu_driver_postclose_kms(struct drm_device * dev,struct drm_file * file_priv)1267 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1268 struct drm_file *file_priv)
1269 {
1270 struct amdgpu_device *adev = drm_to_adev(dev);
1271 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1272 struct amdgpu_bo_list *list;
1273 struct amdgpu_bo *pd;
1274 u32 pasid;
1275 int handle;
1276
1277 if (!fpriv)
1278 return;
1279
1280 pm_runtime_get_sync(dev->dev);
1281
1282 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1283 amdgpu_uvd_free_handles(adev, file_priv);
1284 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1285 amdgpu_vce_free_handles(adev, file_priv);
1286
1287 if (amdgpu_mcbp) {
1288 /* TODO: how to handle reserve failure */
1289 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1290 amdgpu_vm_bo_del(adev, fpriv->csa_va);
1291 fpriv->csa_va = NULL;
1292 amdgpu_bo_unreserve(adev->virt.csa_obj);
1293 }
1294
1295 pasid = fpriv->vm.pasid;
1296 pd = amdgpu_bo_ref(fpriv->vm.root.bo);
1297 if (!WARN_ON(amdgpu_bo_reserve(pd, true))) {
1298 amdgpu_vm_bo_del(adev, fpriv->prt_va);
1299 amdgpu_bo_unreserve(pd);
1300 }
1301
1302 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1303 amdgpu_vm_fini(adev, &fpriv->vm);
1304
1305 if (pasid)
1306 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1307 amdgpu_bo_unref(&pd);
1308
1309 idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1310 amdgpu_bo_list_put(list);
1311
1312 idr_destroy(&fpriv->bo_list_handles);
1313 mutex_destroy(&fpriv->bo_list_lock);
1314
1315 kfree(fpriv);
1316 file_priv->driver_priv = NULL;
1317
1318 pm_runtime_mark_last_busy(dev->dev);
1319 pm_runtime_put_autosuspend(dev->dev);
1320 }
1321
1322
amdgpu_driver_release_kms(struct drm_device * dev)1323 void amdgpu_driver_release_kms(struct drm_device *dev)
1324 {
1325 struct amdgpu_device *adev = drm_to_adev(dev);
1326
1327 amdgpu_device_fini_sw(adev);
1328 pci_set_drvdata(adev->pdev, NULL);
1329 }
1330
1331 /*
1332 * VBlank related functions.
1333 */
1334 /**
1335 * amdgpu_get_vblank_counter_kms - get frame count
1336 *
1337 * @crtc: crtc to get the frame count from
1338 *
1339 * Gets the frame count on the requested crtc (all asics).
1340 * Returns frame count on success, -EINVAL on failure.
1341 */
amdgpu_get_vblank_counter_kms(struct drm_crtc * crtc)1342 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1343 {
1344 struct drm_device *dev = crtc->dev;
1345 unsigned int pipe = crtc->index;
1346 struct amdgpu_device *adev = drm_to_adev(dev);
1347 int vpos, hpos, stat;
1348 u32 count;
1349
1350 if (pipe >= adev->mode_info.num_crtc) {
1351 DRM_ERROR("Invalid crtc %u\n", pipe);
1352 return -EINVAL;
1353 }
1354
1355 /* The hw increments its frame counter at start of vsync, not at start
1356 * of vblank, as is required by DRM core vblank counter handling.
1357 * Cook the hw count here to make it appear to the caller as if it
1358 * incremented at start of vblank. We measure distance to start of
1359 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1360 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1361 * result by 1 to give the proper appearance to caller.
1362 */
1363 if (adev->mode_info.crtcs[pipe]) {
1364 /* Repeat readout if needed to provide stable result if
1365 * we cross start of vsync during the queries.
1366 */
1367 do {
1368 count = amdgpu_display_vblank_get_counter(adev, pipe);
1369 /* Ask amdgpu_display_get_crtc_scanoutpos to return
1370 * vpos as distance to start of vblank, instead of
1371 * regular vertical scanout pos.
1372 */
1373 stat = amdgpu_display_get_crtc_scanoutpos(
1374 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1375 &vpos, &hpos, NULL, NULL,
1376 &adev->mode_info.crtcs[pipe]->base.hwmode);
1377 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1378
1379 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1380 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1381 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1382 } else {
1383 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1384 pipe, vpos);
1385
1386 /* Bump counter if we are at >= leading edge of vblank,
1387 * but before vsync where vpos would turn negative and
1388 * the hw counter really increments.
1389 */
1390 if (vpos >= 0)
1391 count++;
1392 }
1393 } else {
1394 /* Fallback to use value as is. */
1395 count = amdgpu_display_vblank_get_counter(adev, pipe);
1396 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1397 }
1398
1399 return count;
1400 }
1401
1402 /**
1403 * amdgpu_enable_vblank_kms - enable vblank interrupt
1404 *
1405 * @crtc: crtc to enable vblank interrupt for
1406 *
1407 * Enable the interrupt on the requested crtc (all asics).
1408 * Returns 0 on success, -EINVAL on failure.
1409 */
amdgpu_enable_vblank_kms(struct drm_crtc * crtc)1410 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1411 {
1412 struct drm_device *dev = crtc->dev;
1413 unsigned int pipe = crtc->index;
1414 struct amdgpu_device *adev = drm_to_adev(dev);
1415 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1416
1417 return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1418 }
1419
1420 /**
1421 * amdgpu_disable_vblank_kms - disable vblank interrupt
1422 *
1423 * @crtc: crtc to disable vblank interrupt for
1424 *
1425 * Disable the interrupt on the requested crtc (all asics).
1426 */
amdgpu_disable_vblank_kms(struct drm_crtc * crtc)1427 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1428 {
1429 struct drm_device *dev = crtc->dev;
1430 unsigned int pipe = crtc->index;
1431 struct amdgpu_device *adev = drm_to_adev(dev);
1432 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1433
1434 amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1435 }
1436
1437 /*
1438 * Debugfs info
1439 */
1440 #if defined(CONFIG_DEBUG_FS)
1441
amdgpu_debugfs_firmware_info_show(struct seq_file * m,void * unused)1442 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1443 {
1444 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1445 struct drm_amdgpu_info_firmware fw_info;
1446 struct drm_amdgpu_query_fw query_fw;
1447 struct atom_context *ctx = adev->mode_info.atom_context;
1448 uint8_t smu_program, smu_major, smu_minor, smu_debug;
1449 int ret, i;
1450
1451 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1452 #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type
1453 TA_FW_NAME(XGMI),
1454 TA_FW_NAME(RAS),
1455 TA_FW_NAME(HDCP),
1456 TA_FW_NAME(DTM),
1457 TA_FW_NAME(RAP),
1458 TA_FW_NAME(SECUREDISPLAY),
1459 #undef TA_FW_NAME
1460 };
1461
1462 /* VCE */
1463 query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1464 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1465 if (ret)
1466 return ret;
1467 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1468 fw_info.feature, fw_info.ver);
1469
1470 /* UVD */
1471 query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1472 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1473 if (ret)
1474 return ret;
1475 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1476 fw_info.feature, fw_info.ver);
1477
1478 /* GMC */
1479 query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1480 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1481 if (ret)
1482 return ret;
1483 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1484 fw_info.feature, fw_info.ver);
1485
1486 /* ME */
1487 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1488 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1489 if (ret)
1490 return ret;
1491 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1492 fw_info.feature, fw_info.ver);
1493
1494 /* PFP */
1495 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1496 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1497 if (ret)
1498 return ret;
1499 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1500 fw_info.feature, fw_info.ver);
1501
1502 /* CE */
1503 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1504 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1505 if (ret)
1506 return ret;
1507 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1508 fw_info.feature, fw_info.ver);
1509
1510 /* RLC */
1511 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1512 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1513 if (ret)
1514 return ret;
1515 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1516 fw_info.feature, fw_info.ver);
1517
1518 /* RLC SAVE RESTORE LIST CNTL */
1519 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1520 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1521 if (ret)
1522 return ret;
1523 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1524 fw_info.feature, fw_info.ver);
1525
1526 /* RLC SAVE RESTORE LIST GPM MEM */
1527 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1528 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1529 if (ret)
1530 return ret;
1531 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1532 fw_info.feature, fw_info.ver);
1533
1534 /* RLC SAVE RESTORE LIST SRM MEM */
1535 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1536 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1537 if (ret)
1538 return ret;
1539 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1540 fw_info.feature, fw_info.ver);
1541
1542 /* RLCP */
1543 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP;
1544 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1545 if (ret)
1546 return ret;
1547 seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n",
1548 fw_info.feature, fw_info.ver);
1549
1550 /* RLCV */
1551 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV;
1552 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1553 if (ret)
1554 return ret;
1555 seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n",
1556 fw_info.feature, fw_info.ver);
1557
1558 /* MEC */
1559 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1560 query_fw.index = 0;
1561 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1562 if (ret)
1563 return ret;
1564 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1565 fw_info.feature, fw_info.ver);
1566
1567 /* MEC2 */
1568 if (adev->gfx.mec2_fw) {
1569 query_fw.index = 1;
1570 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1571 if (ret)
1572 return ret;
1573 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1574 fw_info.feature, fw_info.ver);
1575 }
1576
1577 /* IMU */
1578 query_fw.fw_type = AMDGPU_INFO_FW_IMU;
1579 query_fw.index = 0;
1580 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1581 if (ret)
1582 return ret;
1583 seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n",
1584 fw_info.feature, fw_info.ver);
1585
1586 /* PSP SOS */
1587 query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1588 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1589 if (ret)
1590 return ret;
1591 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1592 fw_info.feature, fw_info.ver);
1593
1594
1595 /* PSP ASD */
1596 query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1597 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1598 if (ret)
1599 return ret;
1600 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1601 fw_info.feature, fw_info.ver);
1602
1603 query_fw.fw_type = AMDGPU_INFO_FW_TA;
1604 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1605 query_fw.index = i;
1606 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1607 if (ret)
1608 continue;
1609
1610 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1611 ta_fw_name[i], fw_info.feature, fw_info.ver);
1612 }
1613
1614 /* SMC */
1615 query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1616 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1617 if (ret)
1618 return ret;
1619 smu_program = (fw_info.ver >> 24) & 0xff;
1620 smu_major = (fw_info.ver >> 16) & 0xff;
1621 smu_minor = (fw_info.ver >> 8) & 0xff;
1622 smu_debug = (fw_info.ver >> 0) & 0xff;
1623 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n",
1624 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug);
1625
1626 /* SDMA */
1627 query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1628 for (i = 0; i < adev->sdma.num_instances; i++) {
1629 query_fw.index = i;
1630 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1631 if (ret)
1632 return ret;
1633 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1634 i, fw_info.feature, fw_info.ver);
1635 }
1636
1637 /* VCN */
1638 query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1639 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1640 if (ret)
1641 return ret;
1642 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1643 fw_info.feature, fw_info.ver);
1644
1645 /* DMCU */
1646 query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1647 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1648 if (ret)
1649 return ret;
1650 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1651 fw_info.feature, fw_info.ver);
1652
1653 /* DMCUB */
1654 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1655 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1656 if (ret)
1657 return ret;
1658 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1659 fw_info.feature, fw_info.ver);
1660
1661 /* TOC */
1662 query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1663 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1664 if (ret)
1665 return ret;
1666 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1667 fw_info.feature, fw_info.ver);
1668
1669 /* CAP */
1670 if (adev->psp.cap_fw) {
1671 query_fw.fw_type = AMDGPU_INFO_FW_CAP;
1672 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1673 if (ret)
1674 return ret;
1675 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n",
1676 fw_info.feature, fw_info.ver);
1677 }
1678
1679 /* MES_KIQ */
1680 query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ;
1681 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1682 if (ret)
1683 return ret;
1684 seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n",
1685 fw_info.feature, fw_info.ver);
1686
1687 /* MES */
1688 query_fw.fw_type = AMDGPU_INFO_FW_MES;
1689 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1690 if (ret)
1691 return ret;
1692 seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n",
1693 fw_info.feature, fw_info.ver);
1694
1695 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1696
1697 return 0;
1698 }
1699
1700 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1701
1702 #endif
1703
amdgpu_debugfs_firmware_init(struct amdgpu_device * adev)1704 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1705 {
1706 #if defined(CONFIG_DEBUG_FS)
1707 struct drm_minor *minor = adev_to_drm(adev)->primary;
1708 struct dentry *root = minor->debugfs_root;
1709
1710 debugfs_create_file("amdgpu_firmware_info", 0444, root,
1711 adev, &amdgpu_debugfs_firmware_info_fops);
1712
1713 #endif
1714 }
1715