1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24 #include <linux/list.h>
25 #include "amdgpu.h"
26 #include "amdgpu_xgmi.h"
27 #include "amdgpu_ras.h"
28 #include "soc15.h"
29 #include "df/df_3_6_offset.h"
30 #include "xgmi/xgmi_4_0_0_smn.h"
31 #include "xgmi/xgmi_4_0_0_sh_mask.h"
32 #include "xgmi/xgmi_6_1_0_sh_mask.h"
33 #include "wafl/wafl2_4_0_0_smn.h"
34 #include "wafl/wafl2_4_0_0_sh_mask.h"
35
36 #include "amdgpu_reset.h"
37
38 #define smnPCS_XGMI3X16_PCS_ERROR_STATUS 0x11a0020c
39 #define smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK 0x11a00218
40 #define smnPCS_GOPX1_PCS_ERROR_STATUS 0x12200210
41 #define smnPCS_GOPX1_PCS_ERROR_NONCORRECTABLE_MASK 0x12200218
42
43 static DEFINE_MUTEX(xgmi_mutex);
44
45 #define AMDGPU_MAX_XGMI_DEVICE_PER_HIVE 4
46
47 static LIST_HEAD(xgmi_hive_list);
48
49 static const int xgmi_pcs_err_status_reg_vg20[] = {
50 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS,
51 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000,
52 };
53
54 static const int wafl_pcs_err_status_reg_vg20[] = {
55 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS,
56 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000,
57 };
58
59 static const int xgmi_pcs_err_status_reg_arct[] = {
60 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS,
61 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000,
62 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x500000,
63 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x600000,
64 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x700000,
65 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x800000,
66 };
67
68 /* same as vg20*/
69 static const int wafl_pcs_err_status_reg_arct[] = {
70 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS,
71 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000,
72 };
73
74 static const int xgmi3x16_pcs_err_status_reg_aldebaran[] = {
75 smnPCS_XGMI3X16_PCS_ERROR_STATUS,
76 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x100000,
77 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x200000,
78 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x300000,
79 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x400000,
80 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x500000,
81 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x600000,
82 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x700000
83 };
84
85 static const int xgmi3x16_pcs_err_noncorrectable_mask_reg_aldebaran[] = {
86 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK,
87 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x100000,
88 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x200000,
89 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x300000,
90 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x400000,
91 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x500000,
92 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x600000,
93 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x700000
94 };
95
96 static const int walf_pcs_err_status_reg_aldebaran[] = {
97 smnPCS_GOPX1_PCS_ERROR_STATUS,
98 smnPCS_GOPX1_PCS_ERROR_STATUS + 0x100000
99 };
100
101 static const int walf_pcs_err_noncorrectable_mask_reg_aldebaran[] = {
102 smnPCS_GOPX1_PCS_ERROR_NONCORRECTABLE_MASK,
103 smnPCS_GOPX1_PCS_ERROR_NONCORRECTABLE_MASK + 0x100000
104 };
105
106 static const struct amdgpu_pcs_ras_field xgmi_pcs_ras_fields[] = {
107 {"XGMI PCS DataLossErr",
108 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataLossErr)},
109 {"XGMI PCS TrainingErr",
110 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TrainingErr)},
111 {"XGMI PCS CRCErr",
112 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, CRCErr)},
113 {"XGMI PCS BERExceededErr",
114 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, BERExceededErr)},
115 {"XGMI PCS TxMetaDataErr",
116 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TxMetaDataErr)},
117 {"XGMI PCS ReplayBufParityErr",
118 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayBufParityErr)},
119 {"XGMI PCS DataParityErr",
120 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataParityErr)},
121 {"XGMI PCS ReplayFifoOverflowErr",
122 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoOverflowErr)},
123 {"XGMI PCS ReplayFifoUnderflowErr",
124 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)},
125 {"XGMI PCS ElasticFifoOverflowErr",
126 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ElasticFifoOverflowErr)},
127 {"XGMI PCS DeskewErr",
128 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DeskewErr)},
129 {"XGMI PCS DataStartupLimitErr",
130 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataStartupLimitErr)},
131 {"XGMI PCS FCInitTimeoutErr",
132 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, FCInitTimeoutErr)},
133 {"XGMI PCS RecoveryTimeoutErr",
134 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryTimeoutErr)},
135 {"XGMI PCS ReadySerialTimeoutErr",
136 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialTimeoutErr)},
137 {"XGMI PCS ReadySerialAttemptErr",
138 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialAttemptErr)},
139 {"XGMI PCS RecoveryAttemptErr",
140 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryAttemptErr)},
141 {"XGMI PCS RecoveryRelockAttemptErr",
142 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)},
143 };
144
145 static const struct amdgpu_pcs_ras_field wafl_pcs_ras_fields[] = {
146 {"WAFL PCS DataLossErr",
147 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataLossErr)},
148 {"WAFL PCS TrainingErr",
149 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TrainingErr)},
150 {"WAFL PCS CRCErr",
151 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, CRCErr)},
152 {"WAFL PCS BERExceededErr",
153 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, BERExceededErr)},
154 {"WAFL PCS TxMetaDataErr",
155 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TxMetaDataErr)},
156 {"WAFL PCS ReplayBufParityErr",
157 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayBufParityErr)},
158 {"WAFL PCS DataParityErr",
159 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataParityErr)},
160 {"WAFL PCS ReplayFifoOverflowErr",
161 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoOverflowErr)},
162 {"WAFL PCS ReplayFifoUnderflowErr",
163 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)},
164 {"WAFL PCS ElasticFifoOverflowErr",
165 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ElasticFifoOverflowErr)},
166 {"WAFL PCS DeskewErr",
167 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DeskewErr)},
168 {"WAFL PCS DataStartupLimitErr",
169 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataStartupLimitErr)},
170 {"WAFL PCS FCInitTimeoutErr",
171 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, FCInitTimeoutErr)},
172 {"WAFL PCS RecoveryTimeoutErr",
173 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryTimeoutErr)},
174 {"WAFL PCS ReadySerialTimeoutErr",
175 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialTimeoutErr)},
176 {"WAFL PCS ReadySerialAttemptErr",
177 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialAttemptErr)},
178 {"WAFL PCS RecoveryAttemptErr",
179 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryAttemptErr)},
180 {"WAFL PCS RecoveryRelockAttemptErr",
181 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)},
182 };
183
184 static const struct amdgpu_pcs_ras_field xgmi3x16_pcs_ras_fields[] = {
185 {"XGMI3X16 PCS DataLossErr",
186 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, DataLossErr)},
187 {"XGMI3X16 PCS TrainingErr",
188 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, TrainingErr)},
189 {"XGMI3X16 PCS FlowCtrlAckErr",
190 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, FlowCtrlAckErr)},
191 {"XGMI3X16 PCS RxFifoUnderflowErr",
192 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RxFifoUnderflowErr)},
193 {"XGMI3X16 PCS RxFifoOverflowErr",
194 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RxFifoOverflowErr)},
195 {"XGMI3X16 PCS CRCErr",
196 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, CRCErr)},
197 {"XGMI3X16 PCS BERExceededErr",
198 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, BERExceededErr)},
199 {"XGMI3X16 PCS TxVcidDataErr",
200 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, TxVcidDataErr)},
201 {"XGMI3X16 PCS ReplayBufParityErr",
202 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReplayBufParityErr)},
203 {"XGMI3X16 PCS DataParityErr",
204 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, DataParityErr)},
205 {"XGMI3X16 PCS ReplayFifoOverflowErr",
206 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReplayFifoOverflowErr)},
207 {"XGMI3X16 PCS ReplayFifoUnderflowErr",
208 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)},
209 {"XGMI3X16 PCS ElasticFifoOverflowErr",
210 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ElasticFifoOverflowErr)},
211 {"XGMI3X16 PCS DeskewErr",
212 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, DeskewErr)},
213 {"XGMI3X16 PCS FlowCtrlCRCErr",
214 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, FlowCtrlCRCErr)},
215 {"XGMI3X16 PCS DataStartupLimitErr",
216 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, DataStartupLimitErr)},
217 {"XGMI3X16 PCS FCInitTimeoutErr",
218 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, FCInitTimeoutErr)},
219 {"XGMI3X16 PCS RecoveryTimeoutErr",
220 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RecoveryTimeoutErr)},
221 {"XGMI3X16 PCS ReadySerialTimeoutErr",
222 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReadySerialTimeoutErr)},
223 {"XGMI3X16 PCS ReadySerialAttemptErr",
224 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReadySerialAttemptErr)},
225 {"XGMI3X16 PCS RecoveryAttemptErr",
226 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RecoveryAttemptErr)},
227 {"XGMI3X16 PCS RecoveryRelockAttemptErr",
228 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)},
229 {"XGMI3X16 PCS ReplayAttemptErr",
230 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReplayAttemptErr)},
231 {"XGMI3X16 PCS SyncHdrErr",
232 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, SyncHdrErr)},
233 {"XGMI3X16 PCS TxReplayTimeoutErr",
234 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, TxReplayTimeoutErr)},
235 {"XGMI3X16 PCS RxReplayTimeoutErr",
236 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RxReplayTimeoutErr)},
237 {"XGMI3X16 PCS LinkSubTxTimeoutErr",
238 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, LinkSubTxTimeoutErr)},
239 {"XGMI3X16 PCS LinkSubRxTimeoutErr",
240 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, LinkSubRxTimeoutErr)},
241 {"XGMI3X16 PCS RxCMDPktErr",
242 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RxCMDPktErr)},
243 };
244
245 /**
246 * DOC: AMDGPU XGMI Support
247 *
248 * XGMI is a high speed interconnect that joins multiple GPU cards
249 * into a homogeneous memory space that is organized by a collective
250 * hive ID and individual node IDs, both of which are 64-bit numbers.
251 *
252 * The file xgmi_device_id contains the unique per GPU device ID and
253 * is stored in the /sys/class/drm/card${cardno}/device/ directory.
254 *
255 * Inside the device directory a sub-directory 'xgmi_hive_info' is
256 * created which contains the hive ID and the list of nodes.
257 *
258 * The hive ID is stored in:
259 * /sys/class/drm/card${cardno}/device/xgmi_hive_info/xgmi_hive_id
260 *
261 * The node information is stored in numbered directories:
262 * /sys/class/drm/card${cardno}/device/xgmi_hive_info/node${nodeno}/xgmi_device_id
263 *
264 * Each device has their own xgmi_hive_info direction with a mirror
265 * set of node sub-directories.
266 *
267 * The XGMI memory space is built by contiguously adding the power of
268 * two padded VRAM space from each node to each other.
269 *
270 */
271
272 static struct attribute amdgpu_xgmi_hive_id = {
273 .name = "xgmi_hive_id",
274 .mode = S_IRUGO
275 };
276
277 static struct attribute *amdgpu_xgmi_hive_attrs[] = {
278 &amdgpu_xgmi_hive_id,
279 NULL
280 };
281 ATTRIBUTE_GROUPS(amdgpu_xgmi_hive);
282
amdgpu_xgmi_show_attrs(struct kobject * kobj,struct attribute * attr,char * buf)283 static ssize_t amdgpu_xgmi_show_attrs(struct kobject *kobj,
284 struct attribute *attr, char *buf)
285 {
286 struct amdgpu_hive_info *hive = container_of(
287 kobj, struct amdgpu_hive_info, kobj);
288
289 if (attr == &amdgpu_xgmi_hive_id)
290 return snprintf(buf, PAGE_SIZE, "%llu\n", hive->hive_id);
291
292 return 0;
293 }
294
amdgpu_xgmi_hive_release(struct kobject * kobj)295 static void amdgpu_xgmi_hive_release(struct kobject *kobj)
296 {
297 struct amdgpu_hive_info *hive = container_of(
298 kobj, struct amdgpu_hive_info, kobj);
299
300 amdgpu_reset_put_reset_domain(hive->reset_domain);
301 hive->reset_domain = NULL;
302
303 mutex_destroy(&hive->hive_lock);
304 kfree(hive);
305 }
306
307 static const struct sysfs_ops amdgpu_xgmi_hive_ops = {
308 .show = amdgpu_xgmi_show_attrs,
309 };
310
311 struct kobj_type amdgpu_xgmi_hive_type = {
312 .release = amdgpu_xgmi_hive_release,
313 .sysfs_ops = &amdgpu_xgmi_hive_ops,
314 .default_groups = amdgpu_xgmi_hive_groups,
315 };
316
amdgpu_xgmi_show_device_id(struct device * dev,struct device_attribute * attr,char * buf)317 static ssize_t amdgpu_xgmi_show_device_id(struct device *dev,
318 struct device_attribute *attr,
319 char *buf)
320 {
321 struct drm_device *ddev = dev_get_drvdata(dev);
322 struct amdgpu_device *adev = drm_to_adev(ddev);
323
324 return sysfs_emit(buf, "%llu\n", adev->gmc.xgmi.node_id);
325
326 }
327
328 #define AMDGPU_XGMI_SET_FICAA(o) ((o) | 0x456801)
amdgpu_xgmi_show_error(struct device * dev,struct device_attribute * attr,char * buf)329 static ssize_t amdgpu_xgmi_show_error(struct device *dev,
330 struct device_attribute *attr,
331 char *buf)
332 {
333 struct drm_device *ddev = dev_get_drvdata(dev);
334 struct amdgpu_device *adev = drm_to_adev(ddev);
335 uint32_t ficaa_pie_ctl_in, ficaa_pie_status_in;
336 uint64_t fica_out;
337 unsigned int error_count = 0;
338
339 ficaa_pie_ctl_in = AMDGPU_XGMI_SET_FICAA(0x200);
340 ficaa_pie_status_in = AMDGPU_XGMI_SET_FICAA(0x208);
341
342 if ((!adev->df.funcs) ||
343 (!adev->df.funcs->get_fica) ||
344 (!adev->df.funcs->set_fica))
345 return -EINVAL;
346
347 fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_ctl_in);
348 if (fica_out != 0x1f)
349 pr_err("xGMI error counters not enabled!\n");
350
351 fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_status_in);
352
353 if ((fica_out & 0xffff) == 2)
354 error_count = ((fica_out >> 62) & 0x1) + (fica_out >> 63);
355
356 adev->df.funcs->set_fica(adev, ficaa_pie_status_in, 0, 0);
357
358 return sysfs_emit(buf, "%u\n", error_count);
359 }
360
361
362 static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL);
363 static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL);
364
amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device * adev,struct amdgpu_hive_info * hive)365 static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev,
366 struct amdgpu_hive_info *hive)
367 {
368 int ret = 0;
369 char node[10] = { 0 };
370
371 /* Create xgmi device id file */
372 ret = device_create_file(adev->dev, &dev_attr_xgmi_device_id);
373 if (ret) {
374 dev_err(adev->dev, "XGMI: Failed to create device file xgmi_device_id\n");
375 return ret;
376 }
377
378 /* Create xgmi error file */
379 ret = device_create_file(adev->dev, &dev_attr_xgmi_error);
380 if (ret)
381 pr_err("failed to create xgmi_error\n");
382
383
384 /* Create sysfs link to hive info folder on the first device */
385 if (hive->kobj.parent != (&adev->dev->kobj)) {
386 ret = sysfs_create_link(&adev->dev->kobj, &hive->kobj,
387 "xgmi_hive_info");
388 if (ret) {
389 dev_err(adev->dev, "XGMI: Failed to create link to hive info");
390 goto remove_file;
391 }
392 }
393
394 sprintf(node, "node%d", atomic_read(&hive->number_devices));
395 /* Create sysfs link form the hive folder to yourself */
396 ret = sysfs_create_link(&hive->kobj, &adev->dev->kobj, node);
397 if (ret) {
398 dev_err(adev->dev, "XGMI: Failed to create link from hive info");
399 goto remove_link;
400 }
401
402 goto success;
403
404
405 remove_link:
406 sysfs_remove_link(&adev->dev->kobj, adev_to_drm(adev)->unique);
407
408 remove_file:
409 device_remove_file(adev->dev, &dev_attr_xgmi_device_id);
410
411 success:
412 return ret;
413 }
414
amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device * adev,struct amdgpu_hive_info * hive)415 static void amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device *adev,
416 struct amdgpu_hive_info *hive)
417 {
418 char node[10];
419 memset(node, 0, sizeof(node));
420
421 device_remove_file(adev->dev, &dev_attr_xgmi_device_id);
422 device_remove_file(adev->dev, &dev_attr_xgmi_error);
423
424 if (hive->kobj.parent != (&adev->dev->kobj))
425 sysfs_remove_link(&adev->dev->kobj,"xgmi_hive_info");
426
427 sprintf(node, "node%d", atomic_read(&hive->number_devices));
428 sysfs_remove_link(&hive->kobj, node);
429
430 }
431
432
433
amdgpu_get_xgmi_hive(struct amdgpu_device * adev)434 struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev)
435 {
436 struct amdgpu_hive_info *hive = NULL;
437 int ret;
438
439 if (!adev->gmc.xgmi.hive_id)
440 return NULL;
441
442 if (adev->hive) {
443 kobject_get(&adev->hive->kobj);
444 return adev->hive;
445 }
446
447 mutex_lock(&xgmi_mutex);
448
449 list_for_each_entry(hive, &xgmi_hive_list, node) {
450 if (hive->hive_id == adev->gmc.xgmi.hive_id)
451 goto pro_end;
452 }
453
454 hive = kzalloc(sizeof(*hive), GFP_KERNEL);
455 if (!hive) {
456 dev_err(adev->dev, "XGMI: allocation failed\n");
457 hive = NULL;
458 goto pro_end;
459 }
460
461 /* initialize new hive if not exist */
462 ret = kobject_init_and_add(&hive->kobj,
463 &amdgpu_xgmi_hive_type,
464 &adev->dev->kobj,
465 "%s", "xgmi_hive_info");
466 if (ret) {
467 dev_err(adev->dev, "XGMI: failed initializing kobject for xgmi hive\n");
468 kobject_put(&hive->kobj);
469 hive = NULL;
470 goto pro_end;
471 }
472
473 /**
474 * Only init hive->reset_domain for none SRIOV configuration. For SRIOV,
475 * Host driver decide how to reset the GPU either through FLR or chain reset.
476 * Guest side will get individual notifications from the host for the FLR
477 * if necessary.
478 */
479 if (!amdgpu_sriov_vf(adev)) {
480 /**
481 * Avoid recreating reset domain when hive is reconstructed for the case
482 * of reset the devices in the XGMI hive during probe for passthrough GPU
483 * See https://www.spinics.net/lists/amd-gfx/msg58836.html
484 */
485 if (adev->reset_domain->type != XGMI_HIVE) {
486 hive->reset_domain =
487 amdgpu_reset_create_reset_domain(XGMI_HIVE, "amdgpu-reset-hive");
488 if (!hive->reset_domain) {
489 dev_err(adev->dev, "XGMI: failed initializing reset domain for xgmi hive\n");
490 ret = -ENOMEM;
491 kobject_put(&hive->kobj);
492 hive = NULL;
493 goto pro_end;
494 }
495 } else {
496 amdgpu_reset_get_reset_domain(adev->reset_domain);
497 hive->reset_domain = adev->reset_domain;
498 }
499 }
500
501 hive->hive_id = adev->gmc.xgmi.hive_id;
502 INIT_LIST_HEAD(&hive->device_list);
503 INIT_LIST_HEAD(&hive->node);
504 mutex_init(&hive->hive_lock);
505 atomic_set(&hive->number_devices, 0);
506 task_barrier_init(&hive->tb);
507 hive->pstate = AMDGPU_XGMI_PSTATE_UNKNOWN;
508 hive->hi_req_gpu = NULL;
509
510 /*
511 * hive pstate on boot is high in vega20 so we have to go to low
512 * pstate on after boot.
513 */
514 hive->hi_req_count = AMDGPU_MAX_XGMI_DEVICE_PER_HIVE;
515 list_add_tail(&hive->node, &xgmi_hive_list);
516
517 pro_end:
518 if (hive)
519 kobject_get(&hive->kobj);
520 mutex_unlock(&xgmi_mutex);
521 return hive;
522 }
523
amdgpu_put_xgmi_hive(struct amdgpu_hive_info * hive)524 void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive)
525 {
526 if (hive)
527 kobject_put(&hive->kobj);
528 }
529
amdgpu_xgmi_set_pstate(struct amdgpu_device * adev,int pstate)530 int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
531 {
532 int ret = 0;
533 struct amdgpu_hive_info *hive;
534 struct amdgpu_device *request_adev;
535 bool is_hi_req = pstate == AMDGPU_XGMI_PSTATE_MAX_VEGA20;
536 bool init_low;
537
538 hive = amdgpu_get_xgmi_hive(adev);
539 if (!hive)
540 return 0;
541
542 request_adev = hive->hi_req_gpu ? hive->hi_req_gpu : adev;
543 init_low = hive->pstate == AMDGPU_XGMI_PSTATE_UNKNOWN;
544 amdgpu_put_xgmi_hive(hive);
545 /* fw bug so temporarily disable pstate switching */
546 return 0;
547
548 if (!hive || adev->asic_type != CHIP_VEGA20)
549 return 0;
550
551 mutex_lock(&hive->hive_lock);
552
553 if (is_hi_req)
554 hive->hi_req_count++;
555 else
556 hive->hi_req_count--;
557
558 /*
559 * Vega20 only needs single peer to request pstate high for the hive to
560 * go high but all peers must request pstate low for the hive to go low
561 */
562 if (hive->pstate == pstate ||
563 (!is_hi_req && hive->hi_req_count && !init_low))
564 goto out;
565
566 dev_dbg(request_adev->dev, "Set xgmi pstate %d.\n", pstate);
567
568 ret = amdgpu_dpm_set_xgmi_pstate(request_adev, pstate);
569 if (ret) {
570 dev_err(request_adev->dev,
571 "XGMI: Set pstate failure on device %llx, hive %llx, ret %d",
572 request_adev->gmc.xgmi.node_id,
573 request_adev->gmc.xgmi.hive_id, ret);
574 goto out;
575 }
576
577 if (init_low)
578 hive->pstate = hive->hi_req_count ?
579 hive->pstate : AMDGPU_XGMI_PSTATE_MIN;
580 else {
581 hive->pstate = pstate;
582 hive->hi_req_gpu = pstate != AMDGPU_XGMI_PSTATE_MIN ?
583 adev : NULL;
584 }
585 out:
586 mutex_unlock(&hive->hive_lock);
587 return ret;
588 }
589
amdgpu_xgmi_update_topology(struct amdgpu_hive_info * hive,struct amdgpu_device * adev)590 int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev)
591 {
592 int ret;
593
594 if (amdgpu_sriov_vf(adev))
595 return 0;
596
597 /* Each psp need to set the latest topology */
598 ret = psp_xgmi_set_topology_info(&adev->psp,
599 atomic_read(&hive->number_devices),
600 &adev->psp.xgmi_context.top_info);
601 if (ret)
602 dev_err(adev->dev,
603 "XGMI: Set topology failure on device %llx, hive %llx, ret %d",
604 adev->gmc.xgmi.node_id,
605 adev->gmc.xgmi.hive_id, ret);
606
607 return ret;
608 }
609
610
611 /*
612 * NOTE psp_xgmi_node_info.num_hops layout is as follows:
613 * num_hops[7:6] = link type (0 = xGMI2, 1 = xGMI3, 2/3 = reserved)
614 * num_hops[5:3] = reserved
615 * num_hops[2:0] = number of hops
616 */
amdgpu_xgmi_get_hops_count(struct amdgpu_device * adev,struct amdgpu_device * peer_adev)617 int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev,
618 struct amdgpu_device *peer_adev)
619 {
620 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info;
621 uint8_t num_hops_mask = 0x7;
622 int i;
623
624 for (i = 0 ; i < top->num_nodes; ++i)
625 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id)
626 return top->nodes[i].num_hops & num_hops_mask;
627 return -EINVAL;
628 }
629
amdgpu_xgmi_get_num_links(struct amdgpu_device * adev,struct amdgpu_device * peer_adev)630 int amdgpu_xgmi_get_num_links(struct amdgpu_device *adev,
631 struct amdgpu_device *peer_adev)
632 {
633 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info;
634 int i;
635
636 for (i = 0 ; i < top->num_nodes; ++i)
637 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id)
638 return top->nodes[i].num_links;
639 return -EINVAL;
640 }
641
642 /*
643 * Devices that support extended data require the entire hive to initialize with
644 * the shared memory buffer flag set.
645 *
646 * Hive locks and conditions apply - see amdgpu_xgmi_add_device
647 */
amdgpu_xgmi_initialize_hive_get_data_partition(struct amdgpu_hive_info * hive,bool set_extended_data)648 static int amdgpu_xgmi_initialize_hive_get_data_partition(struct amdgpu_hive_info *hive,
649 bool set_extended_data)
650 {
651 struct amdgpu_device *tmp_adev;
652 int ret;
653
654 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
655 ret = psp_xgmi_initialize(&tmp_adev->psp, set_extended_data, false);
656 if (ret) {
657 dev_err(tmp_adev->dev,
658 "XGMI: Failed to initialize xgmi session for data partition %i\n",
659 set_extended_data);
660 return ret;
661 }
662
663 }
664
665 return 0;
666 }
667
amdgpu_xgmi_add_device(struct amdgpu_device * adev)668 int amdgpu_xgmi_add_device(struct amdgpu_device *adev)
669 {
670 struct psp_xgmi_topology_info *top_info;
671 struct amdgpu_hive_info *hive;
672 struct amdgpu_xgmi *entry;
673 struct amdgpu_device *tmp_adev = NULL;
674
675 int count = 0, ret = 0;
676
677 if (!adev->gmc.xgmi.supported)
678 return 0;
679
680 if (!adev->gmc.xgmi.pending_reset &&
681 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
682 ret = psp_xgmi_initialize(&adev->psp, false, true);
683 if (ret) {
684 dev_err(adev->dev,
685 "XGMI: Failed to initialize xgmi session\n");
686 return ret;
687 }
688
689 ret = psp_xgmi_get_hive_id(&adev->psp, &adev->gmc.xgmi.hive_id);
690 if (ret) {
691 dev_err(adev->dev,
692 "XGMI: Failed to get hive id\n");
693 return ret;
694 }
695
696 ret = psp_xgmi_get_node_id(&adev->psp, &adev->gmc.xgmi.node_id);
697 if (ret) {
698 dev_err(adev->dev,
699 "XGMI: Failed to get node id\n");
700 return ret;
701 }
702 } else {
703 adev->gmc.xgmi.hive_id = 16;
704 adev->gmc.xgmi.node_id = adev->gmc.xgmi.physical_node_id + 16;
705 }
706
707 hive = amdgpu_get_xgmi_hive(adev);
708 if (!hive) {
709 ret = -EINVAL;
710 dev_err(adev->dev,
711 "XGMI: node 0x%llx, can not match hive 0x%llx in the hive list.\n",
712 adev->gmc.xgmi.node_id, adev->gmc.xgmi.hive_id);
713 goto exit;
714 }
715 mutex_lock(&hive->hive_lock);
716
717 top_info = &adev->psp.xgmi_context.top_info;
718
719 list_add_tail(&adev->gmc.xgmi.head, &hive->device_list);
720 list_for_each_entry(entry, &hive->device_list, head)
721 top_info->nodes[count++].node_id = entry->node_id;
722 top_info->num_nodes = count;
723 atomic_set(&hive->number_devices, count);
724
725 task_barrier_add_task(&hive->tb);
726
727 if (!adev->gmc.xgmi.pending_reset &&
728 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) {
729 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
730 /* update node list for other device in the hive */
731 if (tmp_adev != adev) {
732 top_info = &tmp_adev->psp.xgmi_context.top_info;
733 top_info->nodes[count - 1].node_id =
734 adev->gmc.xgmi.node_id;
735 top_info->num_nodes = count;
736 }
737 ret = amdgpu_xgmi_update_topology(hive, tmp_adev);
738 if (ret)
739 goto exit_unlock;
740 }
741
742 /* get latest topology info for each device from psp */
743 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
744 ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count,
745 &tmp_adev->psp.xgmi_context.top_info, false);
746 if (ret) {
747 dev_err(tmp_adev->dev,
748 "XGMI: Get topology failure on device %llx, hive %llx, ret %d",
749 tmp_adev->gmc.xgmi.node_id,
750 tmp_adev->gmc.xgmi.hive_id, ret);
751 /* To do : continue with some node failed or disable the whole hive */
752 goto exit_unlock;
753 }
754 }
755
756 /* get topology again for hives that support extended data */
757 if (adev->psp.xgmi_context.supports_extended_data) {
758
759 /* initialize the hive to get extended data. */
760 ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, true);
761 if (ret)
762 goto exit_unlock;
763
764 /* get the extended data. */
765 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
766 ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count,
767 &tmp_adev->psp.xgmi_context.top_info, true);
768 if (ret) {
769 dev_err(tmp_adev->dev,
770 "XGMI: Get topology for extended data failure on device %llx, hive %llx, ret %d",
771 tmp_adev->gmc.xgmi.node_id,
772 tmp_adev->gmc.xgmi.hive_id, ret);
773 goto exit_unlock;
774 }
775 }
776
777 /* initialize the hive to get non-extended data for the next round. */
778 ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, false);
779 if (ret)
780 goto exit_unlock;
781
782 }
783 }
784
785 if (!ret && !adev->gmc.xgmi.pending_reset)
786 ret = amdgpu_xgmi_sysfs_add_dev_info(adev, hive);
787
788 exit_unlock:
789 mutex_unlock(&hive->hive_lock);
790 exit:
791 if (!ret) {
792 adev->hive = hive;
793 dev_info(adev->dev, "XGMI: Add node %d, hive 0x%llx.\n",
794 adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id);
795 } else {
796 amdgpu_put_xgmi_hive(hive);
797 dev_err(adev->dev, "XGMI: Failed to add node %d, hive 0x%llx ret: %d\n",
798 adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id,
799 ret);
800 }
801
802 return ret;
803 }
804
amdgpu_xgmi_remove_device(struct amdgpu_device * adev)805 int amdgpu_xgmi_remove_device(struct amdgpu_device *adev)
806 {
807 struct amdgpu_hive_info *hive = adev->hive;
808
809 if (!adev->gmc.xgmi.supported)
810 return -EINVAL;
811
812 if (!hive)
813 return -EINVAL;
814
815 mutex_lock(&hive->hive_lock);
816 task_barrier_rem_task(&hive->tb);
817 amdgpu_xgmi_sysfs_rem_dev_info(adev, hive);
818 if (hive->hi_req_gpu == adev)
819 hive->hi_req_gpu = NULL;
820 list_del(&adev->gmc.xgmi.head);
821 mutex_unlock(&hive->hive_lock);
822
823 amdgpu_put_xgmi_hive(hive);
824 adev->hive = NULL;
825
826 if (atomic_dec_return(&hive->number_devices) == 0) {
827 /* Remove the hive from global hive list */
828 mutex_lock(&xgmi_mutex);
829 list_del(&hive->node);
830 mutex_unlock(&xgmi_mutex);
831
832 amdgpu_put_xgmi_hive(hive);
833 }
834
835 return 0;
836 }
837
amdgpu_xgmi_ras_late_init(struct amdgpu_device * adev,struct ras_common_if * ras_block)838 static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
839 {
840 if (!adev->gmc.xgmi.supported ||
841 adev->gmc.xgmi.num_physical_nodes == 0)
842 return 0;
843
844 adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev);
845
846 return amdgpu_ras_block_late_init(adev, ras_block);
847 }
848
amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device * adev,uint64_t addr)849 uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev,
850 uint64_t addr)
851 {
852 struct amdgpu_xgmi *xgmi = &adev->gmc.xgmi;
853 return (addr + xgmi->physical_node_id * xgmi->node_segment_size);
854 }
855
pcs_clear_status(struct amdgpu_device * adev,uint32_t pcs_status_reg)856 static void pcs_clear_status(struct amdgpu_device *adev, uint32_t pcs_status_reg)
857 {
858 WREG32_PCIE(pcs_status_reg, 0xFFFFFFFF);
859 WREG32_PCIE(pcs_status_reg, 0);
860 }
861
amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device * adev)862 static void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev)
863 {
864 uint32_t i;
865
866 switch (adev->asic_type) {
867 case CHIP_ARCTURUS:
868 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++)
869 pcs_clear_status(adev,
870 xgmi_pcs_err_status_reg_arct[i]);
871 break;
872 case CHIP_VEGA20:
873 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++)
874 pcs_clear_status(adev,
875 xgmi_pcs_err_status_reg_vg20[i]);
876 break;
877 case CHIP_ALDEBARAN:
878 for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++)
879 pcs_clear_status(adev,
880 xgmi3x16_pcs_err_status_reg_aldebaran[i]);
881 for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++)
882 pcs_clear_status(adev,
883 walf_pcs_err_status_reg_aldebaran[i]);
884 break;
885 default:
886 break;
887 }
888 }
889
amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device * adev,uint32_t value,uint32_t mask_value,uint32_t * ue_count,uint32_t * ce_count,bool is_xgmi_pcs,bool check_mask)890 static int amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device *adev,
891 uint32_t value,
892 uint32_t mask_value,
893 uint32_t *ue_count,
894 uint32_t *ce_count,
895 bool is_xgmi_pcs,
896 bool check_mask)
897 {
898 int i;
899 int ue_cnt = 0;
900 const struct amdgpu_pcs_ras_field *pcs_ras_fields = NULL;
901 uint32_t field_array_size = 0;
902
903 if (is_xgmi_pcs) {
904 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(6, 1, 0)) {
905 pcs_ras_fields = &xgmi3x16_pcs_ras_fields[0];
906 field_array_size = ARRAY_SIZE(xgmi3x16_pcs_ras_fields);
907 } else {
908 pcs_ras_fields = &xgmi_pcs_ras_fields[0];
909 field_array_size = ARRAY_SIZE(xgmi_pcs_ras_fields);
910 }
911 } else {
912 pcs_ras_fields = &wafl_pcs_ras_fields[0];
913 field_array_size = ARRAY_SIZE(wafl_pcs_ras_fields);
914 }
915
916 if (check_mask)
917 value = value & ~mask_value;
918
919 /* query xgmi/walf pcs error status,
920 * only ue is supported */
921 for (i = 0; value && i < field_array_size; i++) {
922 ue_cnt = (value &
923 pcs_ras_fields[i].pcs_err_mask) >>
924 pcs_ras_fields[i].pcs_err_shift;
925 if (ue_cnt) {
926 dev_info(adev->dev, "%s detected\n",
927 pcs_ras_fields[i].err_name);
928 *ue_count += ue_cnt;
929 }
930
931 /* reset bit value if the bit is checked */
932 value &= ~(pcs_ras_fields[i].pcs_err_mask);
933 }
934
935 return 0;
936 }
937
amdgpu_xgmi_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)938 static void amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev,
939 void *ras_error_status)
940 {
941 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
942 int i;
943 uint32_t data, mask_data = 0;
944 uint32_t ue_cnt = 0, ce_cnt = 0;
945
946 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL))
947 return ;
948
949 err_data->ue_count = 0;
950 err_data->ce_count = 0;
951
952 switch (adev->asic_type) {
953 case CHIP_ARCTURUS:
954 /* check xgmi pcs error */
955 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) {
956 data = RREG32_PCIE(xgmi_pcs_err_status_reg_arct[i]);
957 if (data)
958 amdgpu_xgmi_query_pcs_error_status(adev, data,
959 mask_data, &ue_cnt, &ce_cnt, true, false);
960 }
961 /* check wafl pcs error */
962 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_arct); i++) {
963 data = RREG32_PCIE(wafl_pcs_err_status_reg_arct[i]);
964 if (data)
965 amdgpu_xgmi_query_pcs_error_status(adev, data,
966 mask_data, &ue_cnt, &ce_cnt, false, false);
967 }
968 break;
969 case CHIP_VEGA20:
970 /* check xgmi pcs error */
971 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) {
972 data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]);
973 if (data)
974 amdgpu_xgmi_query_pcs_error_status(adev, data,
975 mask_data, &ue_cnt, &ce_cnt, true, false);
976 }
977 /* check wafl pcs error */
978 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_vg20); i++) {
979 data = RREG32_PCIE(wafl_pcs_err_status_reg_vg20[i]);
980 if (data)
981 amdgpu_xgmi_query_pcs_error_status(adev, data,
982 mask_data, &ue_cnt, &ce_cnt, false, false);
983 }
984 break;
985 case CHIP_ALDEBARAN:
986 /* check xgmi3x16 pcs error */
987 for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++) {
988 data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_aldebaran[i]);
989 mask_data =
990 RREG32_PCIE(xgmi3x16_pcs_err_noncorrectable_mask_reg_aldebaran[i]);
991 if (data)
992 amdgpu_xgmi_query_pcs_error_status(adev, data,
993 mask_data, &ue_cnt, &ce_cnt, true, true);
994 }
995 /* check wafl pcs error */
996 for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++) {
997 data = RREG32_PCIE(walf_pcs_err_status_reg_aldebaran[i]);
998 mask_data =
999 RREG32_PCIE(walf_pcs_err_noncorrectable_mask_reg_aldebaran[i]);
1000 if (data)
1001 amdgpu_xgmi_query_pcs_error_status(adev, data,
1002 mask_data, &ue_cnt, &ce_cnt, false, true);
1003 }
1004 break;
1005 default:
1006 dev_warn(adev->dev, "XGMI RAS error query not supported");
1007 break;
1008 }
1009
1010 adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev);
1011
1012 err_data->ue_count += ue_cnt;
1013 err_data->ce_count += ce_cnt;
1014 }
1015
1016 /* Trigger XGMI/WAFL error */
amdgpu_ras_error_inject_xgmi(struct amdgpu_device * adev,void * inject_if)1017 static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev, void *inject_if)
1018 {
1019 int ret = 0;
1020 struct ta_ras_trigger_error_input *block_info =
1021 (struct ta_ras_trigger_error_input *)inject_if;
1022
1023 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
1024 dev_warn(adev->dev, "Failed to disallow df cstate");
1025
1026 if (amdgpu_dpm_allow_xgmi_power_down(adev, false))
1027 dev_warn(adev->dev, "Failed to disallow XGMI power down");
1028
1029 ret = psp_ras_trigger_error(&adev->psp, block_info);
1030
1031 if (amdgpu_ras_intr_triggered())
1032 return ret;
1033
1034 if (amdgpu_dpm_allow_xgmi_power_down(adev, true))
1035 dev_warn(adev->dev, "Failed to allow XGMI power down");
1036
1037 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW))
1038 dev_warn(adev->dev, "Failed to allow df cstate");
1039
1040 return ret;
1041 }
1042
1043 struct amdgpu_ras_block_hw_ops xgmi_ras_hw_ops = {
1044 .query_ras_error_count = amdgpu_xgmi_query_ras_error_count,
1045 .reset_ras_error_count = amdgpu_xgmi_reset_ras_error_count,
1046 .ras_error_inject = amdgpu_ras_error_inject_xgmi,
1047 };
1048
1049 struct amdgpu_xgmi_ras xgmi_ras = {
1050 .ras_block = {
1051 .ras_comm = {
1052 .name = "xgmi_wafl",
1053 .block = AMDGPU_RAS_BLOCK__XGMI_WAFL,
1054 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
1055 },
1056 .hw_ops = &xgmi_ras_hw_ops,
1057 .ras_late_init = amdgpu_xgmi_ras_late_init,
1058 },
1059 };
1060