1 /* ========================================================================== 2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $ 3 * $Revision: #99 $ 4 * $Date: 2012/12/10 $ 5 * $Change: 2123206 $ 6 * 7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, 8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless 9 * otherwise expressly agreed to in writing between Synopsys and you. 10 * 11 * The Software IS NOT an item of Licensed Software or Licensed Product under 12 * any End User Software License Agreement or Agreement for Licensed Product 13 * with Synopsys or any supplement thereto. You are permitted to use and 14 * redistribute this Software in source and binary forms, with or without 15 * modification, provided that redistributions of source code must retain this 16 * notice. You may not view, use, disclose, copy or distribute this file or 17 * any information contained herein except pursuant to this license grant from 18 * Synopsys. If you do not agree with this notice, including the disclaimer 19 * below, then you are not authorized to use the Software. 20 * 21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 31 * DAMAGE. 32 * ========================================================================== */ 33 34 #ifndef __DWC_OTG_REGS_H__ 35 #define __DWC_OTG_REGS_H__ 36 37 #include "dwc_otg_core_if.h" 38 39 40 41 42 /** 43 * @file 44 * 45 * This file contains the data structures for accessing the DWC_otg core registers. 46 * 47 * The application interfaces with the HS OTG core by reading from and 48 * writing to the Control and Status Register (CSR) space through the 49 * AHB Slave interface. These registers are 32 bits wide, and the 50 * addresses are 32-bit-block aligned. 51 * CSRs are classified as follows: 52 * - Core Global Registers 53 * - Device Mode Registers 54 * - Device Global Registers 55 * - Device Endpoint Specific Registers 56 * - Host Mode Registers 57 * - Host Global Registers 58 * - Host Port CSRs 59 * - Host Channel Specific Registers 60 * 61 * Only the Core Global registers can be accessed in both Device and 62 * Host modes. When the HS OTG core is operating in one mode, either 63 * Device or Host, the application must not access registers from the 64 * other mode. When the core switches from one mode to another, the 65 * registers in the new mode of operation must be reprogrammed as they 66 * would be after a power-on reset. 67 */ 68 69 /****************************************************************************/ 70 /** DWC_otg Core registers . 71 * The dwc_otg_core_global_regs structure defines the size 72 * and relative field offsets for the Core Global registers. 73 */ 74 typedef struct dwc_otg_core_global_regs { 75 /** OTG Control and Status Register. <i>Offset: 000h</i> */ 76 volatile uint32_t gotgctl; 77 /** OTG Interrupt Register. <i>Offset: 004h</i> */ 78 volatile uint32_t gotgint; 79 /**Core AHB Configuration Register. <i>Offset: 008h</i> */ 80 volatile uint32_t gahbcfg; 81 82 #define DWC_GLBINTRMASK 0x0001 83 #define DWC_DMAENABLE 0x0020 84 #define DWC_NPTXEMPTYLVL_EMPTY 0x0080 85 #define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000 86 #define DWC_PTXEMPTYLVL_EMPTY 0x0100 87 #define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000 88 89 /**Core USB Configuration Register. <i>Offset: 00Ch</i> */ 90 volatile uint32_t gusbcfg; 91 /**Core Reset Register. <i>Offset: 010h</i> */ 92 volatile uint32_t grstctl; 93 /**Core Interrupt Register. <i>Offset: 014h</i> */ 94 volatile uint32_t gintsts; 95 /**Core Interrupt Mask Register. <i>Offset: 018h</i> */ 96 volatile uint32_t gintmsk; 97 /**Receive Status Queue Read Register (Read Only). <i>Offset: 01Ch</i> */ 98 volatile uint32_t grxstsr; 99 /**Receive Status Queue Read & POP Register (Read Only). <i>Offset: 020h</i>*/ 100 volatile uint32_t grxstsp; 101 /**Receive FIFO Size Register. <i>Offset: 024h</i> */ 102 volatile uint32_t grxfsiz; 103 /**Non Periodic Transmit FIFO Size Register. <i>Offset: 028h</i> */ 104 volatile uint32_t gnptxfsiz; 105 /**Non Periodic Transmit FIFO/Queue Status Register (Read 106 * Only). <i>Offset: 02Ch</i> */ 107 volatile uint32_t gnptxsts; 108 /**I2C Access Register. <i>Offset: 030h</i> */ 109 volatile uint32_t gi2cctl; 110 /**PHY Vendor Control Register. <i>Offset: 034h</i> */ 111 volatile uint32_t gpvndctl; 112 /**General Purpose Input/Output Register. <i>Offset: 038h</i> */ 113 volatile uint32_t ggpio; 114 /**User ID Register. <i>Offset: 03Ch</i> */ 115 volatile uint32_t guid; 116 /**Synopsys ID Register (Read Only). <i>Offset: 040h</i> */ 117 volatile uint32_t gsnpsid; 118 /**User HW Config1 Register (Read Only). <i>Offset: 044h</i> */ 119 volatile uint32_t ghwcfg1; 120 /**User HW Config2 Register (Read Only). <i>Offset: 048h</i> */ 121 volatile uint32_t ghwcfg2; 122 #define DWC_SLAVE_ONLY_ARCH 0 123 #define DWC_EXT_DMA_ARCH 1 124 #define DWC_INT_DMA_ARCH 2 125 126 #define DWC_MODE_HNP_SRP_CAPABLE 0 127 #define DWC_MODE_SRP_ONLY_CAPABLE 1 128 #define DWC_MODE_NO_HNP_SRP_CAPABLE 2 129 #define DWC_MODE_SRP_CAPABLE_DEVICE 3 130 #define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4 131 #define DWC_MODE_SRP_CAPABLE_HOST 5 132 #define DWC_MODE_NO_SRP_CAPABLE_HOST 6 133 134 /**User HW Config3 Register (Read Only). <i>Offset: 04Ch</i> */ 135 volatile uint32_t ghwcfg3; 136 /**User HW Config4 Register (Read Only). <i>Offset: 050h</i>*/ 137 volatile uint32_t ghwcfg4; 138 /** Core LPM Configuration register <i>Offset: 054h</i>*/ 139 volatile uint32_t glpmcfg; 140 /** Global PowerDn Register <i>Offset: 058h</i> */ 141 volatile uint32_t gpwrdn; 142 /** Global DFIFO SW Config Register <i>Offset: 05Ch</i> */ 143 volatile uint32_t gdfifocfg; 144 /** ADP Control Register <i>Offset: 060h</i> */ 145 volatile uint32_t adpctl; 146 /** Reserved <i>Offset: 064h-0FFh</i> */ 147 volatile uint32_t reserved39[39]; 148 /** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */ 149 volatile uint32_t hptxfsiz; 150 /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled, 151 otherwise Device Transmit FIFO#n Register. 152 * <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */ 153 volatile uint32_t dtxfsiz[15]; 154 } dwc_otg_core_global_regs_t; 155 156 /** 157 * This union represents the bit fields of the Core OTG Control 158 * and Status Register (GOTGCTL). Set the bits using the bit 159 * fields then write the <i>d32</i> value to the register. 160 */ 161 typedef union gotgctl_data { 162 /** raw register data */ 163 uint32_t d32; 164 /** register bits */ 165 struct { 166 unsigned sesreqscs:1; 167 unsigned sesreq:1; 168 unsigned vbvalidoven:1; 169 unsigned vbvalidovval:1; 170 unsigned avalidoven:1; 171 unsigned avalidovval:1; 172 unsigned bvalidoven:1; 173 unsigned bvalidovval:1; 174 unsigned hstnegscs:1; 175 unsigned hnpreq:1; 176 unsigned hstsethnpen:1; 177 unsigned devhnpen:1; 178 unsigned reserved12_15:4; 179 unsigned conidsts:1; 180 unsigned dbnctime:1; 181 unsigned asesvld:1; 182 unsigned bsesvld:1; 183 unsigned otgver:1; 184 unsigned reserved1:1; 185 unsigned multvalidbc:5; 186 unsigned chirpen:1; 187 unsigned reserved28_31:4; 188 } b; 189 } gotgctl_data_t; 190 191 /** 192 * This union represents the bit fields of the Core OTG Interrupt Register 193 * (GOTGINT). Set/clear the bits using the bit fields then write the <i>d32</i> 194 * value to the register. 195 */ 196 typedef union gotgint_data { 197 /** raw register data */ 198 uint32_t d32; 199 /** register bits */ 200 struct { 201 /** Current Mode */ 202 unsigned reserved0_1:2; 203 204 /** Session End Detected */ 205 unsigned sesenddet:1; 206 207 unsigned reserved3_7:5; 208 209 /** Session Request Success Status Change */ 210 unsigned sesreqsucstschng:1; 211 /** Host Negotiation Success Status Change */ 212 unsigned hstnegsucstschng:1; 213 214 unsigned reserved10_16:7; 215 216 /** Host Negotiation Detected */ 217 unsigned hstnegdet:1; 218 /** A-Device Timeout Change */ 219 unsigned adevtoutchng:1; 220 /** Debounce Done */ 221 unsigned debdone:1; 222 /** Multi-Valued input changed */ 223 unsigned mvic:1; 224 225 unsigned reserved31_21:11; 226 227 } b; 228 } gotgint_data_t; 229 230 /** 231 * This union represents the bit fields of the Core AHB Configuration 232 * Register (GAHBCFG). Set/clear the bits using the bit fields then 233 * write the <i>d32</i> value to the register. 234 */ 235 typedef union gahbcfg_data { 236 /** raw register data */ 237 uint32_t d32; 238 /** register bits */ 239 struct { 240 unsigned glblintrmsk:1; 241 #define DWC_GAHBCFG_GLBINT_ENABLE 1 242 243 unsigned hburstlen:4; 244 #define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0 245 #define DWC_GAHBCFG_INT_DMA_BURST_INCR 1 246 #define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3 247 #define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5 248 #define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7 249 250 unsigned dmaenable:1; 251 #define DWC_GAHBCFG_DMAENABLE 1 252 unsigned reserved:1; 253 unsigned nptxfemplvl_txfemplvl:1; 254 unsigned ptxfemplvl:1; 255 #define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1 256 #define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 257 unsigned reserved9_20:12; 258 unsigned remmemsupp:1; 259 unsigned notialldmawrit:1; 260 unsigned ahbsingle:1; 261 unsigned reserved24_31:8; 262 } b; 263 } gahbcfg_data_t; 264 265 /** 266 * This union represents the bit fields of the Core USB Configuration 267 * Register (GUSBCFG). Set the bits using the bit fields then write 268 * the <i>d32</i> value to the register. 269 */ 270 typedef union gusbcfg_data { 271 /** raw register data */ 272 uint32_t d32; 273 /** register bits */ 274 struct { 275 unsigned toutcal:3; 276 unsigned phyif:1; 277 unsigned ulpi_utmi_sel:1; 278 unsigned fsintf:1; 279 unsigned physel:1; 280 unsigned ddrsel:1; 281 unsigned srpcap:1; 282 unsigned hnpcap:1; 283 unsigned usbtrdtim:4; 284 unsigned reserved1:1; 285 unsigned phylpwrclksel:1; 286 unsigned otgutmifssel:1; 287 unsigned ulpi_fsls:1; 288 unsigned ulpi_auto_res:1; 289 unsigned ulpi_clk_sus_m:1; 290 unsigned ulpi_ext_vbus_drv:1; 291 unsigned ulpi_int_vbus_indicator:1; 292 unsigned term_sel_dl_pulse:1; 293 unsigned indicator_complement:1; 294 unsigned indicator_pass_through:1; 295 unsigned ulpi_int_prot_dis:1; 296 unsigned ic_usb_cap:1; 297 unsigned ic_traffic_pull_remove:1; 298 unsigned tx_end_delay:1; 299 unsigned force_host_mode:1; 300 unsigned force_dev_mode:1; 301 unsigned reserved31:1; 302 } b; 303 } gusbcfg_data_t; 304 305 /** 306 * This union represents the bit fields of the Core Reset Register 307 * (GRSTCTL). Set/clear the bits using the bit fields then write the 308 * <i>d32</i> value to the register. 309 */ 310 typedef union grstctl_data { 311 /** raw register data */ 312 uint32_t d32; 313 /** register bits */ 314 struct { 315 /** Core Soft Reset (CSftRst) (Device and Host) 316 * 317 * The application can flush the control logic in the 318 * entire core using this bit. This bit resets the 319 * pipelines in the AHB Clock domain as well as the 320 * PHY Clock domain. 321 * 322 * The state machines are reset to an IDLE state, the 323 * control bits in the CSRs are cleared, all the 324 * transmit FIFOs and the receive FIFO are flushed. 325 * 326 * The status mask bits that control the generation of 327 * the interrupt, are cleared, to clear the 328 * interrupt. The interrupt status bits are not 329 * cleared, so the application can get the status of 330 * any events that occurred in the core after it has 331 * set this bit. 332 * 333 * Any transactions on the AHB are terminated as soon 334 * as possible following the protocol. Any 335 * transactions on the USB are terminated immediately. 336 * 337 * The configuration settings in the CSRs are 338 * unchanged, so the software doesn't have to 339 * reprogram these registers (Device 340 * Configuration/Host Configuration/Core System 341 * Configuration/Core PHY Configuration). 342 * 343 * The application can write to this bit, any time it 344 * wants to reset the core. This is a self clearing 345 * bit and the core clears this bit after all the 346 * necessary logic is reset in the core, which may 347 * take several clocks, depending on the current state 348 * of the core. 349 */ 350 unsigned csftrst:1; 351 /** Hclk Soft Reset 352 * 353 * The application uses this bit to reset the control logic in 354 * the AHB clock domain. Only AHB clock domain pipelines are 355 * reset. 356 */ 357 unsigned hsftrst:1; 358 /** Host Frame Counter Reset (Host Only)<br> 359 * 360 * The application can reset the (micro)frame number 361 * counter inside the core, using this bit. When the 362 * (micro)frame counter is reset, the subsequent SOF 363 * sent out by the core, will have a (micro)frame 364 * number of 0. 365 */ 366 unsigned hstfrm:1; 367 /** In Token Sequence Learning Queue Flush 368 * (INTknQFlsh) (Device Only) 369 */ 370 unsigned intknqflsh:1; 371 /** RxFIFO Flush (RxFFlsh) (Device and Host) 372 * 373 * The application can flush the entire Receive FIFO 374 * using this bit. The application must first 375 * ensure that the core is not in the middle of a 376 * transaction. The application should write into 377 * this bit, only after making sure that neither the 378 * DMA engine is reading from the RxFIFO nor the MAC 379 * is writing the data in to the FIFO. The 380 * application should wait until the bit is cleared 381 * before performing any other operations. This bit 382 * will takes 8 clocks (slowest of PHY or AHB clock) 383 * to clear. 384 */ 385 unsigned rxfflsh:1; 386 /** TxFIFO Flush (TxFFlsh) (Device and Host). 387 * 388 * This bit is used to selectively flush a single or 389 * all transmit FIFOs. The application must first 390 * ensure that the core is not in the middle of a 391 * transaction. The application should write into 392 * this bit, only after making sure that neither the 393 * DMA engine is writing into the TxFIFO nor the MAC 394 * is reading the data out of the FIFO. The 395 * application should wait until the core clears this 396 * bit, before performing any operations. This bit 397 * will takes 8 clocks (slowest of PHY or AHB clock) 398 * to clear. 399 */ 400 unsigned txfflsh:1; 401 402 /** TxFIFO Number (TxFNum) (Device and Host). 403 * 404 * This is the FIFO number which needs to be flushed, 405 * using the TxFIFO Flush bit. This field should not 406 * be changed until the TxFIFO Flush bit is cleared by 407 * the core. 408 * - 0x0 : Non Periodic TxFIFO Flush 409 * - 0x1 : Periodic TxFIFO #1 Flush in device mode 410 * or Periodic TxFIFO in host mode 411 * - 0x2 : Periodic TxFIFO #2 Flush in device mode. 412 * - ... 413 * - 0xF : Periodic TxFIFO #15 Flush in device mode 414 * - 0x10: Flush all the Transmit NonPeriodic and 415 * Transmit Periodic FIFOs in the core 416 */ 417 unsigned txfnum:5; 418 /** Reserved */ 419 unsigned reserved11_29:19; 420 /** DMA Request Signal. Indicated DMA request is in 421 * probress. Used for debug purpose. */ 422 unsigned dmareq:1; 423 /** AHB Master Idle. Indicates the AHB Master State 424 * Machine is in IDLE condition. */ 425 unsigned ahbidle:1; 426 } b; 427 } grstctl_t; 428 429 /** 430 * This union represents the bit fields of the Core Interrupt Mask 431 * Register (GINTMSK). Set/clear the bits using the bit fields then 432 * write the <i>d32</i> value to the register. 433 */ 434 typedef union gintmsk_data { 435 /** raw register data */ 436 uint32_t d32; 437 /** register bits */ 438 struct { 439 unsigned reserved0:1; 440 unsigned modemismatch:1; 441 unsigned otgintr:1; 442 unsigned sofintr:1; 443 unsigned rxstsqlvl:1; 444 unsigned nptxfempty:1; 445 unsigned ginnakeff:1; 446 unsigned goutnakeff:1; 447 unsigned ulpickint:1; 448 unsigned i2cintr:1; 449 unsigned erlysuspend:1; 450 unsigned usbsuspend:1; 451 unsigned usbreset:1; 452 unsigned enumdone:1; 453 unsigned isooutdrop:1; 454 unsigned eopframe:1; 455 unsigned restoredone:1; 456 unsigned epmismatch:1; 457 unsigned inepintr:1; 458 unsigned outepintr:1; 459 unsigned incomplisoin:1; 460 unsigned incomplisoout:1; 461 unsigned fetsusp:1; 462 unsigned resetdet:1; 463 unsigned portintr:1; 464 unsigned hcintr:1; 465 unsigned ptxfempty:1; 466 unsigned lpmtranrcvd:1; 467 unsigned conidstschng:1; 468 unsigned disconnect:1; 469 unsigned sessreqintr:1; 470 unsigned wkupintr:1; 471 } b; 472 } gintmsk_data_t; 473 /** 474 * This union represents the bit fields of the Core Interrupt Register 475 * (GINTSTS). Set/clear the bits using the bit fields then write the 476 * <i>d32</i> value to the register. 477 */ 478 typedef union gintsts_data { 479 /** raw register data */ 480 uint32_t d32; 481 #define DWC_SOF_INTR_MASK 0x0008 482 /** register bits */ 483 struct { 484 #define DWC_HOST_MODE 1 485 unsigned curmode:1; 486 unsigned modemismatch:1; 487 unsigned otgintr:1; 488 unsigned sofintr:1; 489 unsigned rxstsqlvl:1; 490 unsigned nptxfempty:1; 491 unsigned ginnakeff:1; 492 unsigned goutnakeff:1; 493 unsigned ulpickint:1; 494 unsigned i2cintr:1; 495 unsigned erlysuspend:1; 496 unsigned usbsuspend:1; 497 unsigned usbreset:1; 498 unsigned enumdone:1; 499 unsigned isooutdrop:1; 500 unsigned eopframe:1; 501 unsigned restoredone:1; 502 unsigned epmismatch:1; 503 unsigned inepint:1; 504 unsigned outepintr:1; 505 unsigned incomplisoin:1; 506 unsigned incomplisoout:1; 507 unsigned fetsusp:1; 508 unsigned resetdet:1; 509 unsigned portintr:1; 510 unsigned hcintr:1; 511 unsigned ptxfempty:1; 512 unsigned lpmtranrcvd:1; 513 unsigned conidstschng:1; 514 unsigned disconnect:1; 515 unsigned sessreqintr:1; 516 unsigned wkupintr:1; 517 } b; 518 } gintsts_data_t; 519 520 /** 521 * This union represents the bit fields in the Device Receive Status Read and 522 * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i> 523 * element then read out the bits using the <i>b</i>it elements. 524 */ 525 typedef union device_grxsts_data { 526 /** raw register data */ 527 uint32_t d32; 528 /** register bits */ 529 struct { 530 unsigned epnum:4; 531 unsigned bcnt:11; 532 unsigned dpid:2; 533 534 #define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet 535 #define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete 536 537 #define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK 538 #define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete 539 #define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet 540 unsigned pktsts:4; 541 unsigned fn:4; 542 unsigned reserved25_31:7; 543 } b; 544 } device_grxsts_data_t; 545 546 /** 547 * This union represents the bit fields in the Host Receive Status Read and 548 * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i> 549 * element then read out the bits using the <i>b</i>it elements. 550 */ 551 typedef union host_grxsts_data { 552 /** raw register data */ 553 uint32_t d32; 554 /** register bits */ 555 struct { 556 unsigned chnum:4; 557 unsigned bcnt:11; 558 unsigned dpid:2; 559 560 unsigned pktsts:4; 561 #define DWC_GRXSTS_PKTSTS_IN 0x2 562 #define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3 563 #define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5 564 #define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7 565 566 unsigned reserved21_31:11; 567 } b; 568 } host_grxsts_data_t; 569 570 /** 571 * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, 572 * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the <i>d32</i> element 573 * then read out the bits using the <i>b</i>it elements. 574 */ 575 typedef union fifosize_data { 576 /** raw register data */ 577 uint32_t d32; 578 /** register bits */ 579 struct { 580 unsigned startaddr:16; 581 unsigned depth:16; 582 } b; 583 } fifosize_data_t; 584 585 /** 586 * This union represents the bit fields in the Non-Periodic Transmit 587 * FIFO/Queue Status Register (GNPTXSTS). Read the register into the 588 * <i>d32</i> element then read out the bits using the <i>b</i>it 589 * elements. 590 */ 591 typedef union gnptxsts_data { 592 /** raw register data */ 593 uint32_t d32; 594 /** register bits */ 595 struct { 596 unsigned nptxfspcavail:16; 597 unsigned nptxqspcavail:8; 598 /** Top of the Non-Periodic Transmit Request Queue 599 * - bit 24 - Terminate (Last entry for the selected 600 * channel/EP) 601 * - bits 26:25 - Token Type 602 * - 2'b00 - IN/OUT 603 * - 2'b01 - Zero Length OUT 604 * - 2'b10 - PING/Complete Split 605 * - 2'b11 - Channel Halt 606 * - bits 30:27 - Channel/EP Number 607 */ 608 unsigned nptxqtop_terminate:1; 609 unsigned nptxqtop_token:2; 610 unsigned nptxqtop_chnep:4; 611 unsigned reserved:1; 612 } b; 613 } gnptxsts_data_t; 614 615 /** 616 * This union represents the bit fields in the Transmit 617 * FIFO Status Register (DTXFSTS). Read the register into the 618 * <i>d32</i> element then read out the bits using the <i>b</i>it 619 * elements. 620 */ 621 typedef union dtxfsts_data { 622 /** raw register data */ 623 uint32_t d32; 624 /** register bits */ 625 struct { 626 unsigned txfspcavail:16; 627 unsigned reserved:16; 628 } b; 629 } dtxfsts_data_t; 630 631 /** 632 * This union represents the bit fields in the I2C Control Register 633 * (I2CCTL). Read the register into the <i>d32</i> element then read out the 634 * bits using the <i>b</i>it elements. 635 */ 636 typedef union gi2cctl_data { 637 /** raw register data */ 638 uint32_t d32; 639 /** register bits */ 640 struct { 641 unsigned rwdata:8; 642 unsigned regaddr:8; 643 unsigned addr:7; 644 unsigned i2cen:1; 645 unsigned ack:1; 646 unsigned i2csuspctl:1; 647 unsigned i2cdevaddr:2; 648 unsigned i2cdatse0:1; 649 unsigned reserved:1; 650 unsigned rw:1; 651 unsigned bsydne:1; 652 } b; 653 } gi2cctl_data_t; 654 655 /** 656 * This union represents the bit fields in the PHY Vendor Control Register 657 * (GPVNDCTL). Read the register into the <i>d32</i> element then read out the 658 * bits using the <i>b</i>it elements. 659 */ 660 typedef union gpvndctl_data { 661 /** raw register data */ 662 uint32_t d32; 663 /** register bits */ 664 struct { 665 unsigned regdata:8; 666 unsigned vctrl:8; 667 unsigned regaddr16_21:6; 668 unsigned regwr:1; 669 unsigned reserved23_24:2; 670 unsigned newregreq:1; 671 unsigned vstsbsy:1; 672 unsigned vstsdone:1; 673 unsigned reserved28_30:3; 674 unsigned disulpidrvr:1; 675 } b; 676 } gpvndctl_data_t; 677 678 /** 679 * This union represents the bit fields in the General Purpose 680 * Input/Output Register (GGPIO). 681 * Read the register into the <i>d32</i> element then read out the 682 * bits using the <i>b</i>it elements. 683 */ 684 typedef union ggpio_data { 685 /** raw register data */ 686 uint32_t d32; 687 /** register bits */ 688 struct { 689 unsigned gpi:16; 690 unsigned gpo:16; 691 } b; 692 } ggpio_data_t; 693 694 /** 695 * This union represents the bit fields in the User ID Register 696 * (GUID). Read the register into the <i>d32</i> element then read out the 697 * bits using the <i>b</i>it elements. 698 */ 699 typedef union guid_data { 700 /** raw register data */ 701 uint32_t d32; 702 /** register bits */ 703 struct { 704 unsigned rwdata:32; 705 } b; 706 } guid_data_t; 707 708 /** 709 * This union represents the bit fields in the Synopsys ID Register 710 * (GSNPSID). Read the register into the <i>d32</i> element then read out the 711 * bits using the <i>b</i>it elements. 712 */ 713 typedef union gsnpsid_data { 714 /** raw register data */ 715 uint32_t d32; 716 /** register bits */ 717 struct { 718 unsigned rwdata:32; 719 } b; 720 } gsnpsid_data_t; 721 722 /** 723 * This union represents the bit fields in the User HW Config1 724 * Register. Read the register into the <i>d32</i> element then read 725 * out the bits using the <i>b</i>it elements. 726 */ 727 typedef union hwcfg1_data { 728 /** raw register data */ 729 uint32_t d32; 730 /** register bits */ 731 struct { 732 unsigned ep_dir0:2; 733 unsigned ep_dir1:2; 734 unsigned ep_dir2:2; 735 unsigned ep_dir3:2; 736 unsigned ep_dir4:2; 737 unsigned ep_dir5:2; 738 unsigned ep_dir6:2; 739 unsigned ep_dir7:2; 740 unsigned ep_dir8:2; 741 unsigned ep_dir9:2; 742 unsigned ep_dir10:2; 743 unsigned ep_dir11:2; 744 unsigned ep_dir12:2; 745 unsigned ep_dir13:2; 746 unsigned ep_dir14:2; 747 unsigned ep_dir15:2; 748 } b; 749 } hwcfg1_data_t; 750 751 /** 752 * This union represents the bit fields in the User HW Config2 753 * Register. Read the register into the <i>d32</i> element then read 754 * out the bits using the <i>b</i>it elements. 755 */ 756 typedef union hwcfg2_data { 757 /** raw register data */ 758 uint32_t d32; 759 /** register bits */ 760 struct { 761 /* GHWCFG2 */ 762 unsigned op_mode:3; 763 #define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0 764 #define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1 765 #define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2 766 #define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 767 #define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 768 #define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 769 #define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 770 771 unsigned architecture:2; 772 unsigned point2point:1; 773 unsigned hs_phy_type:2; 774 #define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 775 #define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1 776 #define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2 777 #define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 778 779 unsigned fs_phy_type:2; 780 unsigned num_dev_ep:4; 781 unsigned num_host_chan:4; 782 unsigned perio_ep_supported:1; 783 unsigned dynamic_fifo:1; 784 unsigned multi_proc_int:1; 785 unsigned reserved21:1; 786 unsigned nonperio_tx_q_depth:2; 787 unsigned host_perio_tx_q_depth:2; 788 unsigned dev_token_q_depth:5; 789 unsigned otg_enable_ic_usb:1; 790 } b; 791 } hwcfg2_data_t; 792 793 /** 794 * This union represents the bit fields in the User HW Config3 795 * Register. Read the register into the <i>d32</i> element then read 796 * out the bits using the <i>b</i>it elements. 797 */ 798 typedef union hwcfg3_data { 799 /** raw register data */ 800 uint32_t d32; 801 /** register bits */ 802 struct { 803 /* GHWCFG3 */ 804 unsigned xfer_size_cntr_width:4; 805 unsigned packet_size_cntr_width:3; 806 unsigned otg_func:1; 807 unsigned i2c:1; 808 unsigned vendor_ctrl_if:1; 809 unsigned optional_features:1; 810 unsigned synch_reset_type:1; 811 unsigned adp_supp:1; 812 unsigned otg_enable_hsic:1; 813 unsigned bc_support:1; 814 unsigned otg_lpm_en:1; 815 unsigned dfifo_depth:16; 816 } b; 817 } hwcfg3_data_t; 818 819 /** 820 * This union represents the bit fields in the User HW Config4 821 * Register. Read the register into the <i>d32</i> element then read 822 * out the bits using the <i>b</i>it elements. 823 */ 824 typedef union hwcfg4_data { 825 /** raw register data */ 826 uint32_t d32; 827 /** register bits */ 828 struct { 829 unsigned num_dev_perio_in_ep:4; 830 unsigned power_optimiz:1; 831 unsigned min_ahb_freq:1; 832 unsigned hiber:1; 833 unsigned xhiber:1; 834 unsigned reserved:6; 835 unsigned utmi_phy_data_width:2; 836 unsigned num_dev_mode_ctrl_ep:4; 837 unsigned iddig_filt_en:1; 838 unsigned vbus_valid_filt_en:1; 839 unsigned a_valid_filt_en:1; 840 unsigned b_valid_filt_en:1; 841 unsigned session_end_filt_en:1; 842 unsigned ded_fifo_en:1; 843 unsigned num_in_eps:4; 844 unsigned desc_dma:1; 845 unsigned desc_dma_dyn:1; 846 } b; 847 } hwcfg4_data_t; 848 849 /** 850 * This union represents the bit fields of the Core LPM Configuration 851 * Register (GLPMCFG). Set the bits using bit fields then write 852 * the <i>d32</i> value to the register. 853 */ 854 typedef union glpmctl_data { 855 /** raw register data */ 856 uint32_t d32; 857 /** register bits */ 858 struct { 859 /** LPM-Capable (LPMCap) (Device and Host) 860 * The application uses this bit to control 861 * the DWC_otg core LPM capabilities. 862 */ 863 unsigned lpm_cap_en:1; 864 /** LPM response programmed by application (AppL1Res) (Device) 865 * Handshake response to LPM token pre-programmed 866 * by device application software. 867 */ 868 unsigned appl_resp:1; 869 /** Host Initiated Resume Duration (HIRD) (Device and Host) 870 * In Host mode this field indicates the value of HIRD 871 * to be sent in an LPM transaction. 872 * In Device mode this field is updated with the 873 * Received LPM Token HIRD bmAttribute 874 * when an ACK/NYET/STALL response is sent 875 * to an LPM transaction. 876 */ 877 unsigned hird:4; 878 /** RemoteWakeEnable (bRemoteWake) (Device and Host) 879 * In Host mode this bit indicates the value of remote 880 * wake up to be sent in wIndex field of LPM transaction. 881 * In Device mode this field is updated with the 882 * Received LPM Token bRemoteWake bmAttribute 883 * when an ACK/NYET/STALL response is sent 884 * to an LPM transaction. 885 */ 886 unsigned rem_wkup_en:1; 887 /** Enable utmi_sleep_n (EnblSlpM) (Device and Host) 888 * The application uses this bit to control 889 * the utmi_sleep_n assertion to the PHY when in L1 state. 890 */ 891 unsigned en_utmi_sleep:1; 892 /** HIRD Threshold (HIRD_Thres) (Device and Host) 893 */ 894 unsigned hird_thres:5; 895 /** LPM Response (CoreL1Res) (Device and Host) 896 * In Host mode this bit contains handsake response to 897 * LPM transaction. 898 * In Device mode the response of the core to 899 * LPM transaction received is reflected in these two bits. 900 - 0x0 : ERROR (No handshake response) 901 - 0x1 : STALL 902 - 0x2 : NYET 903 - 0x3 : ACK 904 */ 905 unsigned lpm_resp:2; 906 /** Port Sleep Status (SlpSts) (Device and Host) 907 * This bit is set as long as a Sleep condition 908 * is present on the USB bus. 909 */ 910 unsigned prt_sleep_sts:1; 911 /** Sleep State Resume OK (L1ResumeOK) (Device and Host) 912 * Indicates that the application or host 913 * can start resume from Sleep state. 914 */ 915 unsigned sleep_state_resumeok:1; 916 /** LPM channel Index (LPM_Chnl_Indx) (Host) 917 * The channel number on which the LPM transaction 918 * has to be applied while sending 919 * an LPM transaction to the local device. 920 */ 921 unsigned lpm_chan_index:4; 922 /** LPM Retry Count (LPM_Retry_Cnt) (Host) 923 * Number host retries that would be performed 924 * if the device response was not valid response. 925 */ 926 unsigned retry_count:3; 927 /** Send LPM Transaction (SndLPM) (Host) 928 * When set by application software, 929 * an LPM transaction containing two tokens 930 * is sent. 931 */ 932 unsigned send_lpm:1; 933 /** LPM Retry status (LPM_RetryCnt_Sts) (Host) 934 * Number of LPM Host Retries still remaining 935 * to be transmitted for the current LPM sequence 936 */ 937 unsigned retry_count_sts:3; 938 /** Enable Best Effort Service Latency (BESL) (Device and Host) 939 * This bit enables the BESL features as defined in the LPM errata 940 */ 941 unsigned en_besl:1; 942 943 unsigned reserved29:1; 944 /** In host mode once this bit is set, the host 945 * configures to drive the HSIC Idle state on the bus. 946 * It then waits for the device to initiate the Connect sequence. 947 * In device mode once this bit is set, the device waits for 948 * the HSIC Idle line state on the bus. Upon receving the Idle 949 * line state, it initiates the HSIC Connect sequence. 950 */ 951 unsigned hsic_connect:1; 952 /** This bit overrides and functionally inverts 953 * the if_select_hsic input port signal. 954 */ 955 unsigned inv_sel_hsic:1; 956 } b; 957 } glpmcfg_data_t; 958 959 /** 960 * This union represents the bit fields of the Core ADP Timer, Control and 961 * Status Register (ADPTIMCTLSTS). Set the bits using bit fields then write 962 * the <i>d32</i> value to the register. 963 */ 964 typedef union adpctl_data { 965 /** raw register data */ 966 uint32_t d32; 967 /** register bits */ 968 struct { 969 /** Probe Discharge (PRB_DSCHG) 970 * These bits set the times for TADP_DSCHG. 971 * These bits are defined as follows: 972 * 2'b00 - 4 msec 973 * 2'b01 - 8 msec 974 * 2'b10 - 16 msec 975 * 2'b11 - 32 msec 976 */ 977 unsigned prb_dschg:2; 978 /** Probe Delta (PRB_DELTA) 979 * These bits set the resolution for RTIM value. 980 * The bits are defined in units of 32 kHz clock cycles as follows: 981 * 2'b00 - 1 cycles 982 * 2'b01 - 2 cycles 983 * 2'b10 - 3 cycles 984 * 2'b11 - 4 cycles 985 * For example if this value is chosen to 2'b01, it means that RTIM 986 * increments for every 3(three) 32Khz clock cycles. 987 */ 988 unsigned prb_delta:2; 989 /** Probe Period (PRB_PER) 990 * These bits sets the TADP_PRD as shown in Figure 4 as follows: 991 * 2'b00 - 0.625 to 0.925 sec (typical 0.775 sec) 992 * 2'b01 - 1.25 to 1.85 sec (typical 1.55 sec) 993 * 2'b10 - 1.9 to 2.6 sec (typical 2.275 sec) 994 * 2'b11 - Reserved 995 */ 996 unsigned prb_per:2; 997 /** These bits capture the latest time it took for VBUS to ramp from 998 * VADP_SINK to VADP_PRB. 999 * 0x000 - 1 cycles 1000 * 0x001 - 2 cycles 1001 * 0x002 - 3 cycles 1002 * etc 1003 * 0x7FF - 2048 cycles 1004 * A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec. 1005 */ 1006 unsigned rtim:11; 1007 /** Enable Probe (EnaPrb) 1008 * When programmed to 1'b1, the core performs a probe operation. 1009 * This bit is valid only if OTG_Ver = 1'b1. 1010 */ 1011 unsigned enaprb:1; 1012 /** Enable Sense (EnaSns) 1013 * When programmed to 1'b1, the core performs a Sense operation. 1014 * This bit is valid only if OTG_Ver = 1'b1. 1015 */ 1016 unsigned enasns:1; 1017 /** ADP Reset (ADPRes) 1018 * When set, ADP controller is reset. 1019 * This bit is valid only if OTG_Ver = 1'b1. 1020 */ 1021 unsigned adpres:1; 1022 /** ADP Enable (ADPEn) 1023 * When set, the core performs either ADP probing or sensing 1024 * based on EnaPrb or EnaSns. 1025 * This bit is valid only if OTG_Ver = 1'b1. 1026 */ 1027 unsigned adpen:1; 1028 /** ADP Probe Interrupt (ADP_PRB_INT) 1029 * When this bit is set, it means that the VBUS 1030 * voltage is greater than VADP_PRB or VADP_PRB is reached. 1031 * This bit is valid only if OTG_Ver = 1'b1. 1032 */ 1033 unsigned adp_prb_int:1; 1034 /** 1035 * ADP Sense Interrupt (ADP_SNS_INT) 1036 * When this bit is set, it means that the VBUS voltage is greater than 1037 * VADP_SNS value or VADP_SNS is reached. 1038 * This bit is valid only if OTG_Ver = 1'b1. 1039 */ 1040 unsigned adp_sns_int:1; 1041 /** ADP Tomeout Interrupt (ADP_TMOUT_INT) 1042 * This bit is relevant only for an ADP probe. 1043 * When this bit is set, it means that the ramp time has 1044 * completed ie ADPCTL.RTIM has reached its terminal value 1045 * of 0x7FF. This is a debug feature that allows software 1046 * to read the ramp time after each cycle. 1047 * This bit is valid only if OTG_Ver = 1'b1. 1048 */ 1049 unsigned adp_tmout_int:1; 1050 /** ADP Probe Interrupt Mask (ADP_PRB_INT_MSK) 1051 * When this bit is set, it unmasks the interrupt due to ADP_PRB_INT. 1052 * This bit is valid only if OTG_Ver = 1'b1. 1053 */ 1054 unsigned adp_prb_int_msk:1; 1055 /** ADP Sense Interrupt Mask (ADP_SNS_INT_MSK) 1056 * When this bit is set, it unmasks the interrupt due to ADP_SNS_INT. 1057 * This bit is valid only if OTG_Ver = 1'b1. 1058 */ 1059 unsigned adp_sns_int_msk:1; 1060 /** ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK) 1061 * When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT. 1062 * This bit is valid only if OTG_Ver = 1'b1. 1063 */ 1064 unsigned adp_tmout_int_msk:1; 1065 /** Access Request 1066 * 2'b00 - Read/Write Valid (updated by the core) 1067 * 2'b01 - Read 1068 * 2'b00 - Write 1069 * 2'b00 - Reserved 1070 */ 1071 unsigned ar:2; 1072 /** Reserved */ 1073 unsigned reserved29_31:3; 1074 } b; 1075 } adpctl_data_t; 1076 1077 //////////////////////////////////////////// 1078 // Device Registers 1079 /** 1080 * Device Global Registers. <i>Offsets 800h-BFFh</i> 1081 * 1082 * The following structures define the size and relative field offsets 1083 * for the Device Mode Registers. 1084 * 1085 * <i>These registers are visible only in Device mode and must not be 1086 * accessed in Host mode, as the results are unknown.</i> 1087 */ 1088 typedef struct dwc_otg_dev_global_regs { 1089 /** Device Configuration Register. <i>Offset 800h</i> */ 1090 volatile uint32_t dcfg; 1091 /** Device Control Register. <i>Offset: 804h</i> */ 1092 volatile uint32_t dctl; 1093 /** Device Status Register (Read Only). <i>Offset: 808h</i> */ 1094 volatile uint32_t dsts; 1095 /** Reserved. <i>Offset: 80Ch</i> */ 1096 uint32_t unused; 1097 /** Device IN Endpoint Common Interrupt Mask 1098 * Register. <i>Offset: 810h</i> */ 1099 volatile uint32_t diepmsk; 1100 /** Device OUT Endpoint Common Interrupt Mask 1101 * Register. <i>Offset: 814h</i> */ 1102 volatile uint32_t doepmsk; 1103 /** Device All Endpoints Interrupt Register. <i>Offset: 818h</i> */ 1104 volatile uint32_t daint; 1105 /** Device All Endpoints Interrupt Mask Register. <i>Offset: 1106 * 81Ch</i> */ 1107 volatile uint32_t daintmsk; 1108 /** Device IN Token Queue Read Register-1 (Read Only). 1109 * <i>Offset: 820h</i> */ 1110 volatile uint32_t dtknqr1; 1111 /** Device IN Token Queue Read Register-2 (Read Only). 1112 * <i>Offset: 824h</i> */ 1113 volatile uint32_t dtknqr2; 1114 /** Device VBUS discharge Register. <i>Offset: 828h</i> */ 1115 volatile uint32_t dvbusdis; 1116 /** Device VBUS Pulse Register. <i>Offset: 82Ch</i> */ 1117 volatile uint32_t dvbuspulse; 1118 /** Device IN Token Queue Read Register-3 (Read Only). / 1119 * Device Thresholding control register (Read/Write) 1120 * <i>Offset: 830h</i> */ 1121 volatile uint32_t dtknqr3_dthrctl; 1122 /** Device IN Token Queue Read Register-4 (Read Only). / 1123 * Device IN EPs empty Inr. Mask Register (Read/Write) 1124 * <i>Offset: 834h</i> */ 1125 volatile uint32_t dtknqr4_fifoemptymsk; 1126 /** Device Each Endpoint Interrupt Register (Read Only). / 1127 * <i>Offset: 838h</i> */ 1128 volatile uint32_t deachint; 1129 /** Device Each Endpoint Interrupt mask Register (Read/Write). / 1130 * <i>Offset: 83Ch</i> */ 1131 volatile uint32_t deachintmsk; 1132 /** Device Each In Endpoint Interrupt mask Register (Read/Write). / 1133 * <i>Offset: 840h</i> */ 1134 volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS]; 1135 /** Device Each Out Endpoint Interrupt mask Register (Read/Write). / 1136 * <i>Offset: 880h</i> */ 1137 volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS]; 1138 } dwc_otg_device_global_regs_t; 1139 1140 /** 1141 * This union represents the bit fields in the Device Configuration 1142 * Register. Read the register into the <i>d32</i> member then 1143 * set/clear the bits using the <i>b</i>it elements. Write the 1144 * <i>d32</i> member to the dcfg register. 1145 */ 1146 typedef union dcfg_data { 1147 /** raw register data */ 1148 uint32_t d32; 1149 /** register bits */ 1150 struct { 1151 /** Device Speed */ 1152 unsigned devspd:2; 1153 /** Non Zero Length Status OUT Handshake */ 1154 unsigned nzstsouthshk:1; 1155 #define DWC_DCFG_SEND_STALL 1 1156 1157 unsigned ena32khzs:1; 1158 /** Device Addresses */ 1159 unsigned devaddr:7; 1160 /** Periodic Frame Interval */ 1161 unsigned perfrint:2; 1162 #define DWC_DCFG_FRAME_INTERVAL_80 0 1163 #define DWC_DCFG_FRAME_INTERVAL_85 1 1164 #define DWC_DCFG_FRAME_INTERVAL_90 2 1165 #define DWC_DCFG_FRAME_INTERVAL_95 3 1166 1167 /** Enable Device OUT NAK for bulk in DDMA mode */ 1168 unsigned endevoutnak:1; 1169 1170 unsigned reserved14_17:4; 1171 /** In Endpoint Mis-match count */ 1172 unsigned epmscnt:5; 1173 /** Enable Descriptor DMA in Device mode */ 1174 unsigned descdma:1; 1175 unsigned perschintvl:2; 1176 unsigned resvalid:6; 1177 } b; 1178 } dcfg_data_t; 1179 1180 /** 1181 * This union represents the bit fields in the Device Control 1182 * Register. Read the register into the <i>d32</i> member then 1183 * set/clear the bits using the <i>b</i>it elements. 1184 */ 1185 typedef union dctl_data { 1186 /** raw register data */ 1187 uint32_t d32; 1188 /** register bits */ 1189 struct { 1190 /** Remote Wakeup */ 1191 unsigned rmtwkupsig:1; 1192 /** Soft Disconnect */ 1193 unsigned sftdiscon:1; 1194 /** Global Non-Periodic IN NAK Status */ 1195 unsigned gnpinnaksts:1; 1196 /** Global OUT NAK Status */ 1197 unsigned goutnaksts:1; 1198 /** Test Control */ 1199 unsigned tstctl:3; 1200 /** Set Global Non-Periodic IN NAK */ 1201 unsigned sgnpinnak:1; 1202 /** Clear Global Non-Periodic IN NAK */ 1203 unsigned cgnpinnak:1; 1204 /** Set Global OUT NAK */ 1205 unsigned sgoutnak:1; 1206 /** Clear Global OUT NAK */ 1207 unsigned cgoutnak:1; 1208 /** Power-On Programming Done */ 1209 unsigned pwronprgdone:1; 1210 /** Reserved */ 1211 unsigned reserved:1; 1212 /** Global Multi Count */ 1213 unsigned gmc:2; 1214 /** Ignore Frame Number for ISOC EPs */ 1215 unsigned ifrmnum:1; 1216 /** NAK on Babble */ 1217 unsigned nakonbble:1; 1218 /** Enable Continue on BNA */ 1219 unsigned encontonbna:1; 1220 /** Enable deep sleep besl reject feature*/ 1221 unsigned besl_reject:1; 1222 1223 unsigned reserved17_31:13; 1224 } b; 1225 } dctl_data_t; 1226 1227 /** 1228 * This union represents the bit fields in the Device Status 1229 * Register. Read the register into the <i>d32</i> member then 1230 * set/clear the bits using the <i>b</i>it elements. 1231 */ 1232 typedef union dsts_data { 1233 /** raw register data */ 1234 uint32_t d32; 1235 /** register bits */ 1236 struct { 1237 /** Suspend Status */ 1238 unsigned suspsts:1; 1239 /** Enumerated Speed */ 1240 unsigned enumspd:2; 1241 #define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 1242 #define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 1243 #define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2 1244 #define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3 1245 /** Erratic Error */ 1246 unsigned errticerr:1; 1247 unsigned reserved4_7:4; 1248 /** Frame or Microframe Number of the received SOF */ 1249 unsigned soffn:14; 1250 unsigned reserved22_31:10; 1251 } b; 1252 } dsts_data_t; 1253 1254 /** 1255 * This union represents the bit fields in the Device IN EP Interrupt 1256 * Register and the Device IN EP Common Mask Register. 1257 * 1258 * - Read the register into the <i>d32</i> member then set/clear the 1259 * bits using the <i>b</i>it elements. 1260 */ 1261 typedef union diepint_data { 1262 /** raw register data */ 1263 uint32_t d32; 1264 /** register bits */ 1265 struct { 1266 /** Transfer complete mask */ 1267 unsigned xfercompl:1; 1268 /** Endpoint disable mask */ 1269 unsigned epdisabled:1; 1270 /** AHB Error mask */ 1271 unsigned ahberr:1; 1272 /** TimeOUT Handshake mask (non-ISOC EPs) */ 1273 unsigned timeout:1; 1274 /** IN Token received with TxF Empty mask */ 1275 unsigned intktxfemp:1; 1276 /** IN Token Received with EP mismatch mask */ 1277 unsigned intknepmis:1; 1278 /** IN Endpoint NAK Effective mask */ 1279 unsigned inepnakeff:1; 1280 /** Reserved */ 1281 unsigned emptyintr:1; 1282 1283 unsigned txfifoundrn:1; 1284 1285 /** BNA Interrupt mask */ 1286 unsigned bna:1; 1287 1288 unsigned reserved10_12:3; 1289 /** BNA Interrupt mask */ 1290 unsigned nak:1; 1291 1292 unsigned reserved14_31:18; 1293 } b; 1294 } diepint_data_t; 1295 1296 /** 1297 * This union represents the bit fields in the Device IN EP 1298 * Common/Dedicated Interrupt Mask Register. 1299 */ 1300 typedef union diepint_data diepmsk_data_t; 1301 1302 /** 1303 * This union represents the bit fields in the Device OUT EP Interrupt 1304 * Registerand Device OUT EP Common Interrupt Mask Register. 1305 * 1306 * - Read the register into the <i>d32</i> member then set/clear the 1307 * bits using the <i>b</i>it elements. 1308 */ 1309 typedef union doepint_data { 1310 /** raw register data */ 1311 uint32_t d32; 1312 /** register bits */ 1313 struct { 1314 /** Transfer complete */ 1315 unsigned xfercompl:1; 1316 /** Endpoint disable */ 1317 unsigned epdisabled:1; 1318 /** AHB Error */ 1319 unsigned ahberr:1; 1320 /** Setup Phase Done (contorl EPs) */ 1321 unsigned setup:1; 1322 /** OUT Token Received when Endpoint Disabled */ 1323 unsigned outtknepdis:1; 1324 1325 unsigned stsphsercvd:1; 1326 /** Back-to-Back SETUP Packets Received */ 1327 unsigned back2backsetup:1; 1328 1329 unsigned reserved7:1; 1330 /** OUT packet Error */ 1331 unsigned outpkterr:1; 1332 /** BNA Interrupt */ 1333 unsigned bna:1; 1334 1335 unsigned reserved10:1; 1336 /** Packet Drop Status */ 1337 unsigned pktdrpsts:1; 1338 /** Babble Interrupt */ 1339 unsigned babble:1; 1340 /** NAK Interrupt */ 1341 unsigned nak:1; 1342 /** NYET Interrupt */ 1343 unsigned nyet:1; 1344 /** Bit indicating setup packet received */ 1345 unsigned sr:1; 1346 1347 unsigned reserved16_31:16; 1348 } b; 1349 } doepint_data_t; 1350 1351 /** 1352 * This union represents the bit fields in the Device OUT EP 1353 * Common/Dedicated Interrupt Mask Register. 1354 */ 1355 typedef union doepint_data doepmsk_data_t; 1356 1357 /** 1358 * This union represents the bit fields in the Device All EP Interrupt 1359 * and Mask Registers. 1360 * - Read the register into the <i>d32</i> member then set/clear the 1361 * bits using the <i>b</i>it elements. 1362 */ 1363 typedef union daint_data { 1364 /** raw register data */ 1365 uint32_t d32; 1366 /** register bits */ 1367 struct { 1368 /** IN Endpoint bits */ 1369 unsigned in:16; 1370 /** OUT Endpoint bits */ 1371 unsigned out:16; 1372 } ep; 1373 struct { 1374 /** IN Endpoint bits */ 1375 unsigned inep0:1; 1376 unsigned inep1:1; 1377 unsigned inep2:1; 1378 unsigned inep3:1; 1379 unsigned inep4:1; 1380 unsigned inep5:1; 1381 unsigned inep6:1; 1382 unsigned inep7:1; 1383 unsigned inep8:1; 1384 unsigned inep9:1; 1385 unsigned inep10:1; 1386 unsigned inep11:1; 1387 unsigned inep12:1; 1388 unsigned inep13:1; 1389 unsigned inep14:1; 1390 unsigned inep15:1; 1391 /** OUT Endpoint bits */ 1392 unsigned outep0:1; 1393 unsigned outep1:1; 1394 unsigned outep2:1; 1395 unsigned outep3:1; 1396 unsigned outep4:1; 1397 unsigned outep5:1; 1398 unsigned outep6:1; 1399 unsigned outep7:1; 1400 unsigned outep8:1; 1401 unsigned outep9:1; 1402 unsigned outep10:1; 1403 unsigned outep11:1; 1404 unsigned outep12:1; 1405 unsigned outep13:1; 1406 unsigned outep14:1; 1407 unsigned outep15:1; 1408 } b; 1409 } daint_data_t; 1410 1411 /** 1412 * This union represents the bit fields in the Device IN Token Queue 1413 * Read Registers. 1414 * - Read the register into the <i>d32</i> member. 1415 * - READ-ONLY Register 1416 */ 1417 typedef union dtknq1_data { 1418 /** raw register data */ 1419 uint32_t d32; 1420 /** register bits */ 1421 struct { 1422 /** In Token Queue Write Pointer */ 1423 unsigned intknwptr:5; 1424 /** Reserved */ 1425 unsigned reserved05_06:2; 1426 /** write pointer has wrapped. */ 1427 unsigned wrap_bit:1; 1428 /** EP Numbers of IN Tokens 0 ... 4 */ 1429 unsigned epnums0_5:24; 1430 } b; 1431 } dtknq1_data_t; 1432 1433 /** 1434 * This union represents Threshold control Register 1435 * - Read and write the register into the <i>d32</i> member. 1436 * - READ-WRITABLE Register 1437 */ 1438 typedef union dthrctl_data { 1439 /** raw register data */ 1440 uint32_t d32; 1441 /** register bits */ 1442 struct { 1443 /** non ISO Tx Thr. Enable */ 1444 unsigned non_iso_thr_en:1; 1445 /** ISO Tx Thr. Enable */ 1446 unsigned iso_thr_en:1; 1447 /** Tx Thr. Length */ 1448 unsigned tx_thr_len:9; 1449 /** AHB Threshold ratio */ 1450 unsigned ahb_thr_ratio:2; 1451 /** Reserved */ 1452 unsigned reserved13_15:3; 1453 /** Rx Thr. Enable */ 1454 unsigned rx_thr_en:1; 1455 /** Rx Thr. Length */ 1456 unsigned rx_thr_len:9; 1457 unsigned reserved26:1; 1458 /** Arbiter Parking Enable*/ 1459 unsigned arbprken:1; 1460 /** Reserved */ 1461 unsigned reserved28_31:4; 1462 } b; 1463 } dthrctl_data_t; 1464 1465 /** 1466 * Device Logical IN Endpoint-Specific Registers. <i>Offsets 1467 * 900h-AFCh</i> 1468 * 1469 * There will be one set of endpoint registers per logical endpoint 1470 * implemented. 1471 * 1472 * <i>These registers are visible only in Device mode and must not be 1473 * accessed in Host mode, as the results are unknown.</i> 1474 */ 1475 typedef struct dwc_otg_dev_in_ep_regs { 1476 /** Device IN Endpoint Control Register. <i>Offset:900h + 1477 * (ep_num * 20h) + 00h</i> */ 1478 volatile uint32_t diepctl; 1479 /** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */ 1480 uint32_t reserved04; 1481 /** Device IN Endpoint Interrupt Register. <i>Offset:900h + 1482 * (ep_num * 20h) + 08h</i> */ 1483 volatile uint32_t diepint; 1484 /** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */ 1485 uint32_t reserved0C; 1486 /** Device IN Endpoint Transfer Size 1487 * Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */ 1488 volatile uint32_t dieptsiz; 1489 /** Device IN Endpoint DMA Address Register. <i>Offset:900h + 1490 * (ep_num * 20h) + 14h</i> */ 1491 volatile uint32_t diepdma; 1492 /** Device IN Endpoint Transmit FIFO Status Register. <i>Offset:900h + 1493 * (ep_num * 20h) + 18h</i> */ 1494 volatile uint32_t dtxfsts; 1495 /** Device IN Endpoint DMA Buffer Register. <i>Offset:900h + 1496 * (ep_num * 20h) + 1Ch</i> */ 1497 volatile uint32_t diepdmab; 1498 } dwc_otg_dev_in_ep_regs_t; 1499 1500 /** 1501 * Device Logical OUT Endpoint-Specific Registers. <i>Offsets: 1502 * B00h-CFCh</i> 1503 * 1504 * There will be one set of endpoint registers per logical endpoint 1505 * implemented. 1506 * 1507 * <i>These registers are visible only in Device mode and must not be 1508 * accessed in Host mode, as the results are unknown.</i> 1509 */ 1510 typedef struct dwc_otg_dev_out_ep_regs { 1511 /** Device OUT Endpoint Control Register. <i>Offset:B00h + 1512 * (ep_num * 20h) + 00h</i> */ 1513 volatile uint32_t doepctl; 1514 /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 04h</i> */ 1515 uint32_t reserved04; 1516 /** Device OUT Endpoint Interrupt Register. <i>Offset:B00h + 1517 * (ep_num * 20h) + 08h</i> */ 1518 volatile uint32_t doepint; 1519 /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */ 1520 uint32_t reserved0C; 1521 /** Device OUT Endpoint Transfer Size Register. <i>Offset: 1522 * B00h + (ep_num * 20h) + 10h</i> */ 1523 volatile uint32_t doeptsiz; 1524 /** Device OUT Endpoint DMA Address Register. <i>Offset:B00h 1525 * + (ep_num * 20h) + 14h</i> */ 1526 volatile uint32_t doepdma; 1527 /** Reserved. <i>Offset:B00h + * (ep_num * 20h) + 18h</i> */ 1528 uint32_t unused; 1529 /** Device OUT Endpoint DMA Buffer Register. <i>Offset:B00h 1530 * + (ep_num * 20h) + 1Ch</i> */ 1531 uint32_t doepdmab; 1532 } dwc_otg_dev_out_ep_regs_t; 1533 1534 /** 1535 * This union represents the bit fields in the Device EP Control 1536 * Register. Read the register into the <i>d32</i> member then 1537 * set/clear the bits using the <i>b</i>it elements. 1538 */ 1539 typedef union depctl_data { 1540 /** raw register data */ 1541 uint32_t d32; 1542 /** register bits */ 1543 struct { 1544 /** Maximum Packet Size 1545 * IN/OUT EPn 1546 * IN/OUT EP0 - 2 bits 1547 * 2'b00: 64 Bytes 1548 * 2'b01: 32 1549 * 2'b10: 16 1550 * 2'b11: 8 */ 1551 unsigned mps:11; 1552 #define DWC_DEP0CTL_MPS_64 0 1553 #define DWC_DEP0CTL_MPS_32 1 1554 #define DWC_DEP0CTL_MPS_16 2 1555 #define DWC_DEP0CTL_MPS_8 3 1556 1557 /** Next Endpoint 1558 * IN EPn/IN EP0 1559 * OUT EPn/OUT EP0 - reserved */ 1560 unsigned nextep:4; 1561 1562 /** USB Active Endpoint */ 1563 unsigned usbactep:1; 1564 1565 /** Endpoint DPID (INTR/Bulk IN and OUT endpoints) 1566 * This field contains the PID of the packet going to 1567 * be received or transmitted on this endpoint. The 1568 * application should program the PID of the first 1569 * packet going to be received or transmitted on this 1570 * endpoint , after the endpoint is 1571 * activated. Application use the SetD1PID and 1572 * SetD0PID fields of this register to program either 1573 * D0 or D1 PID. 1574 * 1575 * The encoding for this field is 1576 * - 0: D0 1577 * - 1: D1 1578 */ 1579 unsigned dpid:1; 1580 1581 /** NAK Status */ 1582 unsigned naksts:1; 1583 1584 /** Endpoint Type 1585 * 2'b00: Control 1586 * 2'b01: Isochronous 1587 * 2'b10: Bulk 1588 * 2'b11: Interrupt */ 1589 unsigned eptype:2; 1590 1591 /** Snoop Mode 1592 * OUT EPn/OUT EP0 1593 * IN EPn/IN EP0 - reserved */ 1594 unsigned snp:1; 1595 1596 /** Stall Handshake */ 1597 unsigned stall:1; 1598 1599 /** Tx Fifo Number 1600 * IN EPn/IN EP0 1601 * OUT EPn/OUT EP0 - reserved */ 1602 unsigned txfnum:4; 1603 1604 /** Clear NAK */ 1605 unsigned cnak:1; 1606 /** Set NAK */ 1607 unsigned snak:1; 1608 /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints) 1609 * Writing to this field sets the Endpoint DPID (DPID) 1610 * field in this register to DATA0. Set Even 1611 * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) 1612 * Writing to this field sets the Even/Odd 1613 * (micro)frame (EO_FrNum) field to even (micro) 1614 * frame. 1615 */ 1616 unsigned setd0pid:1; 1617 /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints) 1618 * Writing to this field sets the Endpoint DPID (DPID) 1619 * field in this register to DATA1 Set Odd 1620 * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) 1621 * Writing to this field sets the Even/Odd 1622 * (micro)frame (EO_FrNum) field to odd (micro) frame. 1623 */ 1624 unsigned setd1pid:1; 1625 1626 /** Endpoint Disable */ 1627 unsigned epdis:1; 1628 /** Endpoint Enable */ 1629 unsigned epena:1; 1630 } b; 1631 } depctl_data_t; 1632 1633 /** 1634 * This union represents the bit fields in the Device EP Transfer 1635 * Size Register. Read the register into the <i>d32</i> member then 1636 * set/clear the bits using the <i>b</i>it elements. 1637 */ 1638 typedef union deptsiz_data { 1639 /** raw register data */ 1640 uint32_t d32; 1641 /** register bits */ 1642 struct { 1643 /** Transfer size */ 1644 unsigned xfersize:19; 1645 /** Max packet count for EP (pow(2,10)-1) */ 1646 #define MAX_PKT_CNT 1023 1647 /** Packet Count */ 1648 unsigned pktcnt:10; 1649 /** Multi Count - Periodic IN endpoints */ 1650 unsigned mc:2; 1651 unsigned reserved:1; 1652 } b; 1653 } deptsiz_data_t; 1654 1655 /** 1656 * This union represents the bit fields in the Device EP 0 Transfer 1657 * Size Register. Read the register into the <i>d32</i> member then 1658 * set/clear the bits using the <i>b</i>it elements. 1659 */ 1660 typedef union deptsiz0_data { 1661 /** raw register data */ 1662 uint32_t d32; 1663 /** register bits */ 1664 struct { 1665 /** Transfer size */ 1666 unsigned xfersize:7; 1667 /** Reserved */ 1668 unsigned reserved7_18:12; 1669 /** Packet Count */ 1670 unsigned pktcnt:2; 1671 /** Reserved */ 1672 unsigned reserved21_28:8; 1673 /**Setup Packet Count (DOEPTSIZ0 Only) */ 1674 unsigned supcnt:2; 1675 unsigned reserved31; 1676 } b; 1677 } deptsiz0_data_t; 1678 1679 ///////////////////////////////////////////////// 1680 // DMA Descriptor Specific Structures 1681 // 1682 1683 /** Buffer status definitions */ 1684 1685 #define BS_HOST_READY 0x0 1686 #define BS_DMA_BUSY 0x1 1687 #define BS_DMA_DONE 0x2 1688 #define BS_HOST_BUSY 0x3 1689 1690 /** Receive/Transmit status definitions */ 1691 1692 #define RTS_SUCCESS 0x0 1693 #define RTS_BUFFLUSH 0x1 1694 #define RTS_RESERVED 0x2 1695 #define RTS_BUFERR 0x3 1696 1697 /** 1698 * This union represents the bit fields in the DMA Descriptor 1699 * status quadlet. Read the quadlet into the <i>d32</i> member then 1700 * set/clear the bits using the <i>b</i>it, <i>b_iso_out</i> and 1701 * <i>b_iso_in</i> elements. 1702 */ 1703 typedef union dev_dma_desc_sts { 1704 /** raw register data */ 1705 uint32_t d32; 1706 /** quadlet bits */ 1707 struct { 1708 /** Received number of bytes */ 1709 unsigned bytes:16; 1710 /** NAK bit - only for OUT EPs */ 1711 unsigned nak:1; 1712 unsigned reserved17_22:6; 1713 /** Multiple Transfer - only for OUT EPs */ 1714 unsigned mtrf:1; 1715 /** Setup Packet received - only for OUT EPs */ 1716 unsigned sr:1; 1717 /** Interrupt On Complete */ 1718 unsigned ioc:1; 1719 /** Short Packet */ 1720 unsigned sp:1; 1721 /** Last */ 1722 unsigned l:1; 1723 /** Receive Status */ 1724 unsigned sts:2; 1725 /** Buffer Status */ 1726 unsigned bs:2; 1727 } b; 1728 1729 //#ifdef DWC_EN_ISOC 1730 /** iso out quadlet bits */ 1731 struct { 1732 /** Received number of bytes */ 1733 unsigned rxbytes:11; 1734 1735 unsigned reserved11:1; 1736 /** Frame Number */ 1737 unsigned framenum:11; 1738 /** Received ISO Data PID */ 1739 unsigned pid:2; 1740 /** Interrupt On Complete */ 1741 unsigned ioc:1; 1742 /** Short Packet */ 1743 unsigned sp:1; 1744 /** Last */ 1745 unsigned l:1; 1746 /** Receive Status */ 1747 unsigned rxsts:2; 1748 /** Buffer Status */ 1749 unsigned bs:2; 1750 } b_iso_out; 1751 1752 /** iso in quadlet bits */ 1753 struct { 1754 /** Transmited number of bytes */ 1755 unsigned txbytes:12; 1756 /** Frame Number */ 1757 unsigned framenum:11; 1758 /** Transmited ISO Data PID */ 1759 unsigned pid:2; 1760 /** Interrupt On Complete */ 1761 unsigned ioc:1; 1762 /** Short Packet */ 1763 unsigned sp:1; 1764 /** Last */ 1765 unsigned l:1; 1766 /** Transmit Status */ 1767 unsigned txsts:2; 1768 /** Buffer Status */ 1769 unsigned bs:2; 1770 } b_iso_in; 1771 //#endif /* DWC_EN_ISOC */ 1772 } dev_dma_desc_sts_t; 1773 1774 /** 1775 * DMA Descriptor structure 1776 * 1777 * DMA Descriptor structure contains two quadlets: 1778 * Status quadlet and Data buffer pointer. 1779 */ 1780 typedef struct dwc_otg_dev_dma_desc { 1781 /** DMA Descriptor status quadlet */ 1782 dev_dma_desc_sts_t status; 1783 /** DMA Descriptor data buffer pointer */ 1784 uint32_t buf; 1785 } dwc_otg_dev_dma_desc_t; 1786 1787 /** 1788 * The dwc_otg_dev_if structure contains information needed to manage 1789 * the DWC_otg controller acting in device mode. It represents the 1790 * programming view of the device-specific aspects of the controller. 1791 */ 1792 typedef struct dwc_otg_dev_if { 1793 /** Pointer to device Global registers. 1794 * Device Global Registers starting at offset 800h 1795 */ 1796 dwc_otg_device_global_regs_t *dev_global_regs; 1797 #define DWC_DEV_GLOBAL_REG_OFFSET 0x800 1798 1799 /** 1800 * Device Logical IN Endpoint-Specific Registers 900h-AFCh 1801 */ 1802 dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS]; 1803 #define DWC_DEV_IN_EP_REG_OFFSET 0x900 1804 #define DWC_EP_REG_OFFSET 0x20 1805 1806 /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */ 1807 dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS]; 1808 #define DWC_DEV_OUT_EP_REG_OFFSET 0xB00 1809 1810 /* Device configuration information */ 1811 uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */ 1812 uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */ 1813 uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/ 1814 1815 /** Size of periodic FIFOs (Bytes) */ 1816 uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS]; 1817 1818 /** Size of Tx FIFOs (Bytes) */ 1819 uint16_t tx_fifo_size[MAX_TX_FIFOS]; 1820 1821 /** Thresholding enable flags and length varaiables **/ 1822 uint16_t rx_thr_en; 1823 uint16_t iso_tx_thr_en; 1824 uint16_t non_iso_tx_thr_en; 1825 1826 uint16_t rx_thr_length; 1827 uint16_t tx_thr_length; 1828 1829 /** 1830 * Pointers to the DMA Descriptors for EP0 Control 1831 * transfers (virtual and physical) 1832 */ 1833 1834 /** 2 descriptors for SETUP packets */ 1835 dwc_dma_t dma_setup_desc_addr[2]; 1836 dwc_otg_dev_dma_desc_t *setup_desc_addr[2]; 1837 1838 /** Pointer to Descriptor with latest SETUP packet */ 1839 dwc_otg_dev_dma_desc_t *psetup; 1840 1841 /** Index of current SETUP handler descriptor */ 1842 uint32_t setup_desc_index; 1843 1844 /** Descriptor for Data In or Status In phases */ 1845 dwc_dma_t dma_in_desc_addr; 1846 dwc_otg_dev_dma_desc_t *in_desc_addr; 1847 1848 /** Descriptor for Data Out or Status Out phases */ 1849 dwc_dma_t dma_out_desc_addr; 1850 dwc_otg_dev_dma_desc_t *out_desc_addr; 1851 1852 /** Setup Packet Detected - if set clear NAK when queueing */ 1853 uint32_t spd; 1854 /** Isoc ep pointer on which incomplete happens */ 1855 void *isoc_ep; 1856 1857 } dwc_otg_dev_if_t; 1858 1859 ///////////////////////////////////////////////// 1860 // Host Mode Register Structures 1861 // 1862 /** 1863 * The Host Global Registers structure defines the size and relative 1864 * field offsets for the Host Mode Global Registers. Host Global 1865 * Registers offsets 400h-7FFh. 1866 */ 1867 typedef struct dwc_otg_host_global_regs { 1868 /** Host Configuration Register. <i>Offset: 400h</i> */ 1869 volatile uint32_t hcfg; 1870 /** Host Frame Interval Register. <i>Offset: 404h</i> */ 1871 volatile uint32_t hfir; 1872 /** Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */ 1873 volatile uint32_t hfnum; 1874 /** Reserved. <i>Offset: 40Ch</i> */ 1875 uint32_t reserved40C; 1876 /** Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */ 1877 volatile uint32_t hptxsts; 1878 /** Host All Channels Interrupt Register. <i>Offset: 414h</i> */ 1879 volatile uint32_t haint; 1880 /** Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */ 1881 volatile uint32_t haintmsk; 1882 /** Host Frame List Base Address Register . <i>Offset: 41Ch</i> */ 1883 volatile uint32_t hflbaddr; 1884 } dwc_otg_host_global_regs_t; 1885 1886 /** 1887 * This union represents the bit fields in the Host Configuration Register. 1888 * Read the register into the <i>d32</i> member then set/clear the bits using 1889 * the <i>b</i>it elements. Write the <i>d32</i> member to the hcfg register. 1890 */ 1891 typedef union hcfg_data { 1892 /** raw register data */ 1893 uint32_t d32; 1894 1895 /** register bits */ 1896 struct { 1897 /** FS/LS Phy Clock Select */ 1898 unsigned fslspclksel:2; 1899 #define DWC_HCFG_30_60_MHZ 0 1900 #define DWC_HCFG_48_MHZ 1 1901 #define DWC_HCFG_6_MHZ 2 1902 1903 /** FS/LS Only Support */ 1904 unsigned fslssupp:1; 1905 unsigned reserved3_6:4; 1906 /** Enable 32-KHz Suspend Mode */ 1907 unsigned ena32khzs:1; 1908 /** Resume Validation Periiod */ 1909 unsigned resvalid:8; 1910 unsigned reserved16_22:7; 1911 /** Enable Scatter/gather DMA in Host mode */ 1912 unsigned descdma:1; 1913 /** Frame List Entries */ 1914 unsigned frlisten:2; 1915 /** Enable Periodic Scheduling */ 1916 unsigned perschedena:1; 1917 unsigned reserved27_30:4; 1918 unsigned modechtimen:1; 1919 } b; 1920 } hcfg_data_t; 1921 1922 /** 1923 * This union represents the bit fields in the Host Frame Remaing/Number 1924 * Register. 1925 */ 1926 typedef union hfir_data { 1927 /** raw register data */ 1928 uint32_t d32; 1929 1930 /** register bits */ 1931 struct { 1932 unsigned frint:16; 1933 unsigned hfirrldctrl:1; 1934 unsigned reserved:15; 1935 } b; 1936 } hfir_data_t; 1937 1938 /** 1939 * This union represents the bit fields in the Host Frame Remaing/Number 1940 * Register. 1941 */ 1942 typedef union hfnum_data { 1943 /** raw register data */ 1944 uint32_t d32; 1945 1946 /** register bits */ 1947 struct { 1948 unsigned frnum:16; 1949 #define DWC_HFNUM_MAX_FRNUM 0x3FFF 1950 unsigned frrem:16; 1951 } b; 1952 } hfnum_data_t; 1953 1954 typedef union hptxsts_data { 1955 /** raw register data */ 1956 uint32_t d32; 1957 1958 /** register bits */ 1959 struct { 1960 unsigned ptxfspcavail:16; 1961 unsigned ptxqspcavail:8; 1962 /** Top of the Periodic Transmit Request Queue 1963 * - bit 24 - Terminate (last entry for the selected channel) 1964 * - bits 26:25 - Token Type 1965 * - 2'b00 - Zero length 1966 * - 2'b01 - Ping 1967 * - 2'b10 - Disable 1968 * - bits 30:27 - Channel Number 1969 * - bit 31 - Odd/even microframe 1970 */ 1971 unsigned ptxqtop_terminate:1; 1972 unsigned ptxqtop_token:2; 1973 unsigned ptxqtop_chnum:4; 1974 unsigned ptxqtop_odd:1; 1975 } b; 1976 } hptxsts_data_t; 1977 1978 /** 1979 * This union represents the bit fields in the Host Port Control and Status 1980 * Register. Read the register into the <i>d32</i> member then set/clear the 1981 * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the 1982 * hprt0 register. 1983 */ 1984 typedef union hprt0_data { 1985 /** raw register data */ 1986 uint32_t d32; 1987 /** register bits */ 1988 struct { 1989 unsigned prtconnsts:1; 1990 unsigned prtconndet:1; 1991 unsigned prtena:1; 1992 unsigned prtenchng:1; 1993 unsigned prtovrcurract:1; 1994 unsigned prtovrcurrchng:1; 1995 unsigned prtres:1; 1996 unsigned prtsusp:1; 1997 unsigned prtrst:1; 1998 unsigned reserved9:1; 1999 unsigned prtlnsts:2; 2000 unsigned prtpwr:1; 2001 unsigned prttstctl:4; 2002 unsigned prtspd:2; 2003 #define DWC_HPRT0_PRTSPD_HIGH_SPEED 0 2004 #define DWC_HPRT0_PRTSPD_FULL_SPEED 1 2005 #define DWC_HPRT0_PRTSPD_LOW_SPEED 2 2006 unsigned reserved19_31:13; 2007 } b; 2008 } hprt0_data_t; 2009 2010 /** 2011 * This union represents the bit fields in the Host All Interrupt 2012 * Register. 2013 */ 2014 typedef union haint_data { 2015 /** raw register data */ 2016 uint32_t d32; 2017 /** register bits */ 2018 struct { 2019 unsigned ch0:1; 2020 unsigned ch1:1; 2021 unsigned ch2:1; 2022 unsigned ch3:1; 2023 unsigned ch4:1; 2024 unsigned ch5:1; 2025 unsigned ch6:1; 2026 unsigned ch7:1; 2027 unsigned ch8:1; 2028 unsigned ch9:1; 2029 unsigned ch10:1; 2030 unsigned ch11:1; 2031 unsigned ch12:1; 2032 unsigned ch13:1; 2033 unsigned ch14:1; 2034 unsigned ch15:1; 2035 unsigned reserved:16; 2036 } b; 2037 2038 struct { 2039 unsigned chint:16; 2040 unsigned reserved:16; 2041 } b2; 2042 } haint_data_t; 2043 2044 /** 2045 * This union represents the bit fields in the Host All Interrupt 2046 * Register. 2047 */ 2048 typedef union haintmsk_data { 2049 /** raw register data */ 2050 uint32_t d32; 2051 /** register bits */ 2052 struct { 2053 unsigned ch0:1; 2054 unsigned ch1:1; 2055 unsigned ch2:1; 2056 unsigned ch3:1; 2057 unsigned ch4:1; 2058 unsigned ch5:1; 2059 unsigned ch6:1; 2060 unsigned ch7:1; 2061 unsigned ch8:1; 2062 unsigned ch9:1; 2063 unsigned ch10:1; 2064 unsigned ch11:1; 2065 unsigned ch12:1; 2066 unsigned ch13:1; 2067 unsigned ch14:1; 2068 unsigned ch15:1; 2069 unsigned reserved:16; 2070 } b; 2071 2072 struct { 2073 unsigned chint:16; 2074 unsigned reserved:16; 2075 } b2; 2076 } haintmsk_data_t; 2077 2078 /** 2079 * Host Channel Specific Registers. <i>500h-5FCh</i> 2080 */ 2081 typedef struct dwc_otg_hc_regs { 2082 /** Host Channel 0 Characteristic Register. <i>Offset: 500h + (chan_num * 20h) + 00h</i> */ 2083 volatile uint32_t hcchar; 2084 /** Host Channel 0 Split Control Register. <i>Offset: 500h + (chan_num * 20h) + 04h</i> */ 2085 volatile uint32_t hcsplt; 2086 /** Host Channel 0 Interrupt Register. <i>Offset: 500h + (chan_num * 20h) + 08h</i> */ 2087 volatile uint32_t hcint; 2088 /** Host Channel 0 Interrupt Mask Register. <i>Offset: 500h + (chan_num * 20h) + 0Ch</i> */ 2089 volatile uint32_t hcintmsk; 2090 /** Host Channel 0 Transfer Size Register. <i>Offset: 500h + (chan_num * 20h) + 10h</i> */ 2091 volatile uint32_t hctsiz; 2092 /** Host Channel 0 DMA Address Register. <i>Offset: 500h + (chan_num * 20h) + 14h</i> */ 2093 volatile uint32_t hcdma; 2094 volatile uint32_t reserved; 2095 /** Host Channel 0 DMA Buffer Address Register. <i>Offset: 500h + (chan_num * 20h) + 1Ch</i> */ 2096 volatile uint32_t hcdmab; 2097 } dwc_otg_hc_regs_t; 2098 2099 /** 2100 * This union represents the bit fields in the Host Channel Characteristics 2101 * Register. Read the register into the <i>d32</i> member then set/clear the 2102 * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the 2103 * hcchar register. 2104 */ 2105 typedef union hcchar_data { 2106 /** raw register data */ 2107 uint32_t d32; 2108 2109 /** register bits */ 2110 struct { 2111 /** Maximum packet size in bytes */ 2112 unsigned mps:11; 2113 2114 /** Endpoint number */ 2115 unsigned epnum:4; 2116 2117 /** 0: OUT, 1: IN */ 2118 unsigned epdir:1; 2119 2120 unsigned reserved:1; 2121 2122 /** 0: Full/high speed device, 1: Low speed device */ 2123 unsigned lspddev:1; 2124 2125 /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */ 2126 unsigned eptype:2; 2127 2128 /** Packets per frame for periodic transfers. 0 is reserved. */ 2129 unsigned multicnt:2; 2130 2131 /** Device address */ 2132 unsigned devaddr:7; 2133 2134 /** 2135 * Frame to transmit periodic transaction. 2136 * 0: even, 1: odd 2137 */ 2138 unsigned oddfrm:1; 2139 2140 /** Channel disable */ 2141 unsigned chdis:1; 2142 2143 /** Channel enable */ 2144 unsigned chen:1; 2145 } b; 2146 } hcchar_data_t; 2147 2148 typedef union hcsplt_data { 2149 /** raw register data */ 2150 uint32_t d32; 2151 2152 /** register bits */ 2153 struct { 2154 /** Port Address */ 2155 unsigned prtaddr:7; 2156 2157 /** Hub Address */ 2158 unsigned hubaddr:7; 2159 2160 /** Transaction Position */ 2161 unsigned xactpos:2; 2162 #define DWC_HCSPLIT_XACTPOS_MID 0 2163 #define DWC_HCSPLIT_XACTPOS_END 1 2164 #define DWC_HCSPLIT_XACTPOS_BEGIN 2 2165 #define DWC_HCSPLIT_XACTPOS_ALL 3 2166 2167 /** Do Complete Split */ 2168 unsigned compsplt:1; 2169 2170 /** Reserved */ 2171 unsigned reserved:14; 2172 2173 /** Split Enble */ 2174 unsigned spltena:1; 2175 } b; 2176 } hcsplt_data_t; 2177 2178 /** 2179 * This union represents the bit fields in the Host All Interrupt 2180 * Register. 2181 */ 2182 typedef union hcint_data { 2183 /** raw register data */ 2184 uint32_t d32; 2185 /** register bits */ 2186 struct { 2187 /** Transfer Complete */ 2188 unsigned xfercomp:1; 2189 /** Channel Halted */ 2190 unsigned chhltd:1; 2191 /** AHB Error */ 2192 unsigned ahberr:1; 2193 /** STALL Response Received */ 2194 unsigned stall:1; 2195 /** NAK Response Received */ 2196 unsigned nak:1; 2197 /** ACK Response Received */ 2198 unsigned ack:1; 2199 /** NYET Response Received */ 2200 unsigned nyet:1; 2201 /** Transaction Err */ 2202 unsigned xacterr:1; 2203 /** Babble Error */ 2204 unsigned bblerr:1; 2205 /** Frame Overrun */ 2206 unsigned frmovrun:1; 2207 /** Data Toggle Error */ 2208 unsigned datatglerr:1; 2209 /** Buffer Not Available (only for DDMA mode) */ 2210 unsigned bna:1; 2211 /** Exessive transaction error (only for DDMA mode) */ 2212 unsigned xcs_xact:1; 2213 /** Frame List Rollover interrupt */ 2214 unsigned frm_list_roll:1; 2215 /** Reserved */ 2216 unsigned reserved14_31:18; 2217 } b; 2218 } hcint_data_t; 2219 2220 /** 2221 * This union represents the bit fields in the Host Channel Interrupt Mask 2222 * Register. Read the register into the <i>d32</i> member then set/clear the 2223 * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the 2224 * hcintmsk register. 2225 */ 2226 typedef union hcintmsk_data { 2227 /** raw register data */ 2228 uint32_t d32; 2229 2230 /** register bits */ 2231 struct { 2232 unsigned xfercompl:1; 2233 unsigned chhltd:1; 2234 unsigned ahberr:1; 2235 unsigned stall:1; 2236 unsigned nak:1; 2237 unsigned ack:1; 2238 unsigned nyet:1; 2239 unsigned xacterr:1; 2240 unsigned bblerr:1; 2241 unsigned frmovrun:1; 2242 unsigned datatglerr:1; 2243 unsigned bna:1; 2244 unsigned xcs_xact:1; 2245 unsigned frm_list_roll:1; 2246 unsigned reserved14_31:18; 2247 } b; 2248 } hcintmsk_data_t; 2249 2250 /** 2251 * This union represents the bit fields in the Host Channel Transfer Size 2252 * Register. Read the register into the <i>d32</i> member then set/clear the 2253 * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the 2254 * hcchar register. 2255 */ 2256 2257 typedef union hctsiz_data { 2258 /** raw register data */ 2259 uint32_t d32; 2260 2261 /** register bits */ 2262 struct { 2263 /** Total transfer size in bytes */ 2264 unsigned xfersize:19; 2265 2266 /** Data packets to transfer */ 2267 unsigned pktcnt:10; 2268 2269 /** 2270 * Packet ID for next data packet 2271 * 0: DATA0 2272 * 1: DATA2 2273 * 2: DATA1 2274 * 3: MDATA (non-Control), SETUP (Control) 2275 */ 2276 unsigned pid:2; 2277 #define DWC_HCTSIZ_DATA0 0 2278 #define DWC_HCTSIZ_DATA1 2 2279 #define DWC_HCTSIZ_DATA2 1 2280 #define DWC_HCTSIZ_MDATA 3 2281 #define DWC_HCTSIZ_SETUP 3 2282 2283 /** Do PING protocol when 1 */ 2284 unsigned dopng:1; 2285 } b; 2286 2287 /** register bits */ 2288 struct { 2289 /** Scheduling information */ 2290 unsigned schinfo:8; 2291 2292 /** Number of transfer descriptors. 2293 * Max value: 2294 * 64 in general, 2295 * 256 only for HS isochronous endpoint. 2296 */ 2297 unsigned ntd:8; 2298 2299 /** Data packets to transfer */ 2300 unsigned reserved16_28:13; 2301 2302 /** 2303 * Packet ID for next data packet 2304 * 0: DATA0 2305 * 1: DATA2 2306 * 2: DATA1 2307 * 3: MDATA (non-Control) 2308 */ 2309 unsigned pid:2; 2310 2311 /** Do PING protocol when 1 */ 2312 unsigned dopng:1; 2313 } b_ddma; 2314 } hctsiz_data_t; 2315 2316 /** 2317 * This union represents the bit fields in the Host DMA Address 2318 * Register used in Descriptor DMA mode. 2319 */ 2320 typedef union hcdma_data { 2321 /** raw register data */ 2322 uint32_t d32; 2323 /** register bits */ 2324 struct { 2325 unsigned reserved0_2:3; 2326 /** Current Transfer Descriptor. Not used for ISOC */ 2327 unsigned ctd:8; 2328 /** Start Address of Descriptor List */ 2329 unsigned dma_addr:21; 2330 } b; 2331 } hcdma_data_t; 2332 2333 /** 2334 * This union represents the bit fields in the DMA Descriptor 2335 * status quadlet for host mode. Read the quadlet into the <i>d32</i> member then 2336 * set/clear the bits using the <i>b</i>it elements. 2337 */ 2338 typedef union host_dma_desc_sts { 2339 /** raw register data */ 2340 uint32_t d32; 2341 /** quadlet bits */ 2342 2343 /* for non-isochronous */ 2344 struct { 2345 /** Number of bytes */ 2346 unsigned n_bytes:17; 2347 /** QTD offset to jump when Short Packet received - only for IN EPs */ 2348 unsigned qtd_offset:6; 2349 /** 2350 * Set to request the core to jump to alternate QTD if 2351 * Short Packet received - only for IN EPs 2352 */ 2353 unsigned a_qtd:1; 2354 /** 2355 * Setup Packet bit. When set indicates that buffer contains 2356 * setup packet. 2357 */ 2358 unsigned sup:1; 2359 /** Interrupt On Complete */ 2360 unsigned ioc:1; 2361 /** End of List */ 2362 unsigned eol:1; 2363 unsigned reserved27:1; 2364 /** Rx/Tx Status */ 2365 unsigned sts:2; 2366 #define DMA_DESC_STS_PKTERR 1 2367 unsigned reserved30:1; 2368 /** Active Bit */ 2369 unsigned a:1; 2370 } b; 2371 /* for isochronous */ 2372 struct { 2373 /** Number of bytes */ 2374 unsigned n_bytes:12; 2375 unsigned reserved12_24:13; 2376 /** Interrupt On Complete */ 2377 unsigned ioc:1; 2378 unsigned reserved26_27:2; 2379 /** Rx/Tx Status */ 2380 unsigned sts:2; 2381 unsigned reserved30:1; 2382 /** Active Bit */ 2383 unsigned a:1; 2384 } b_isoc; 2385 } host_dma_desc_sts_t; 2386 2387 #define MAX_DMA_DESC_SIZE 131071 2388 #define MAX_DMA_DESC_NUM_GENERIC 64 2389 #define MAX_DMA_DESC_NUM_HS_ISOC 256 2390 #define MAX_FRLIST_EN_NUM 64 2391 /** 2392 * Host-mode DMA Descriptor structure 2393 * 2394 * DMA Descriptor structure contains two quadlets: 2395 * Status quadlet and Data buffer pointer. 2396 */ 2397 typedef struct dwc_otg_host_dma_desc { 2398 /** DMA Descriptor status quadlet */ 2399 host_dma_desc_sts_t status; 2400 /** DMA Descriptor data buffer pointer */ 2401 uint32_t buf; 2402 } dwc_otg_host_dma_desc_t; 2403 2404 /** OTG Host Interface Structure. 2405 * 2406 * The OTG Host Interface Structure structure contains information 2407 * needed to manage the DWC_otg controller acting in host mode. It 2408 * represents the programming view of the host-specific aspects of the 2409 * controller. 2410 */ 2411 typedef struct dwc_otg_host_if { 2412 /** Host Global Registers starting at offset 400h.*/ 2413 dwc_otg_host_global_regs_t *host_global_regs; 2414 #define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400 2415 2416 /** Host Port 0 Control and Status Register */ 2417 volatile uint32_t *hprt0; 2418 #define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440 2419 2420 /** Host Channel Specific Registers at offsets 500h-5FCh. */ 2421 dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS]; 2422 #define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500 2423 #define DWC_OTG_CHAN_REGS_OFFSET 0x20 2424 2425 /* Host configuration information */ 2426 /** Number of Host Channels (range: 1-16) */ 2427 uint8_t num_host_channels; 2428 /** Periodic EPs supported (0: no, 1: yes) */ 2429 uint8_t perio_eps_supported; 2430 /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */ 2431 uint16_t perio_tx_fifo_size; 2432 2433 } dwc_otg_host_if_t; 2434 2435 /** 2436 * This union represents the bit fields in the Power and Clock Gating Control 2437 * Register. Read the register into the <i>d32</i> member then set/clear the 2438 * bits using the <i>b</i>it elements. 2439 */ 2440 typedef union pcgcctl_data { 2441 /** raw register data */ 2442 uint32_t d32; 2443 2444 /** register bits */ 2445 struct { 2446 /** Stop Pclk */ 2447 unsigned stoppclk:1; 2448 /** Gate Hclk */ 2449 unsigned gatehclk:1; 2450 /** Power Clamp */ 2451 unsigned pwrclmp:1; 2452 /** Reset Power Down Modules */ 2453 unsigned rstpdwnmodule:1; 2454 /** Reserved */ 2455 unsigned reserved:1; 2456 /** Enable Sleep Clock Gating (Enbl_L1Gating) */ 2457 unsigned enbl_sleep_gating:1; 2458 /** PHY In Sleep (PhySleep) */ 2459 unsigned phy_in_sleep:1; 2460 /** Deep Sleep*/ 2461 unsigned deep_sleep:1; 2462 unsigned resetaftsusp:1; 2463 unsigned restoremode:1; 2464 unsigned enbl_extnd_hiber:1; 2465 unsigned extnd_hiber_pwrclmp:1; 2466 unsigned extnd_hiber_switch:1; 2467 unsigned ess_reg_restored:1; 2468 unsigned prt_clk_sel:2; 2469 unsigned port_power:1; 2470 unsigned max_xcvrselect:2; 2471 unsigned max_termsel:1; 2472 unsigned mac_dev_addr:7; 2473 unsigned p2hd_dev_enum_spd:2; 2474 unsigned p2hd_prt_spd:2; 2475 unsigned if_dev_mode:1; 2476 } b; 2477 } pcgcctl_data_t; 2478 2479 /** 2480 * This union represents the bit fields in the Global Data FIFO Software 2481 * Configuration Register. Read the register into the <i>d32</i> member then 2482 * set/clear the bits using the <i>b</i>it elements. 2483 */ 2484 typedef union gdfifocfg_data { 2485 /* raw register data */ 2486 uint32_t d32; 2487 /** register bits */ 2488 struct { 2489 /** OTG Data FIFO depth */ 2490 unsigned gdfifocfg:16; 2491 /** Start address of EP info controller */ 2492 unsigned epinfobase:16; 2493 } b; 2494 } gdfifocfg_data_t; 2495 2496 /** 2497 * This union represents the bit fields in the Global Power Down Register 2498 * Register. Read the register into the <i>d32</i> member then set/clear the 2499 * bits using the <i>b</i>it elements. 2500 */ 2501 typedef union gpwrdn_data { 2502 /* raw register data */ 2503 uint32_t d32; 2504 2505 /** register bits */ 2506 struct { 2507 /** PMU Interrupt Select */ 2508 unsigned pmuintsel:1; 2509 /** PMU Active */ 2510 unsigned pmuactv:1; 2511 /** Restore */ 2512 unsigned restore:1; 2513 /** Power Down Clamp */ 2514 unsigned pwrdnclmp:1; 2515 /** Power Down Reset */ 2516 unsigned pwrdnrstn:1; 2517 /** Power Down Switch */ 2518 unsigned pwrdnswtch:1; 2519 /** Disable VBUS */ 2520 unsigned dis_vbus:1; 2521 /** Line State Change */ 2522 unsigned lnstschng:1; 2523 /** Line state change mask */ 2524 unsigned lnstchng_msk:1; 2525 /** Reset Detected */ 2526 unsigned rst_det:1; 2527 /** Reset Detect mask */ 2528 unsigned rst_det_msk:1; 2529 /** Disconnect Detected */ 2530 unsigned disconn_det:1; 2531 /** Disconnect Detect mask */ 2532 unsigned disconn_det_msk:1; 2533 /** Connect Detected*/ 2534 unsigned connect_det:1; 2535 /** Connect Detected Mask*/ 2536 unsigned connect_det_msk:1; 2537 /** SRP Detected */ 2538 unsigned srp_det:1; 2539 /** SRP Detect mask */ 2540 unsigned srp_det_msk:1; 2541 /** Status Change Interrupt */ 2542 unsigned sts_chngint:1; 2543 /** Status Change Interrupt Mask */ 2544 unsigned sts_chngint_msk:1; 2545 /** Line State */ 2546 unsigned linestate:2; 2547 /** Indicates current mode(status of IDDIG signal) */ 2548 unsigned idsts:1; 2549 /** B Session Valid signal status*/ 2550 unsigned bsessvld:1; 2551 /** ADP Event Detected */ 2552 unsigned adp_int:1; 2553 /** Multi Valued ID pin */ 2554 unsigned mult_val_id_bc:5; 2555 /** Reserved 24_31 */ 2556 unsigned reserved29_31:3; 2557 } b; 2558 } gpwrdn_data_t; 2559 2560 #endif 2561