1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25 /*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28
29 #include <linux/pci.h>
30
31 #include <drm/drm_atomic_helper.h>
32 #include <drm/drm_drv.h>
33 #include <drm/drm_gem.h>
34 #include <drm/drm_managed.h>
35
36 #include "ast_drv.h"
37
ast_set_index_reg_mask(struct ast_private * ast,uint32_t base,uint8_t index,uint8_t mask,uint8_t val)38 void ast_set_index_reg_mask(struct ast_private *ast,
39 uint32_t base, uint8_t index,
40 uint8_t mask, uint8_t val)
41 {
42 u8 tmp;
43 ast_io_write8(ast, base, index);
44 tmp = (ast_io_read8(ast, base + 1) & mask) | val;
45 ast_set_index_reg(ast, base, index, tmp);
46 }
47
ast_get_index_reg(struct ast_private * ast,uint32_t base,uint8_t index)48 uint8_t ast_get_index_reg(struct ast_private *ast,
49 uint32_t base, uint8_t index)
50 {
51 uint8_t ret;
52 ast_io_write8(ast, base, index);
53 ret = ast_io_read8(ast, base + 1);
54 return ret;
55 }
56
ast_get_index_reg_mask(struct ast_private * ast,uint32_t base,uint8_t index,uint8_t mask)57 uint8_t ast_get_index_reg_mask(struct ast_private *ast,
58 uint32_t base, uint8_t index, uint8_t mask)
59 {
60 uint8_t ret;
61 ast_io_write8(ast, base, index);
62 ret = ast_io_read8(ast, base + 1) & mask;
63 return ret;
64 }
65
ast_detect_config_mode(struct drm_device * dev,u32 * scu_rev)66 static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev)
67 {
68 struct device_node *np = dev->dev->of_node;
69 struct ast_private *ast = to_ast_private(dev);
70 struct pci_dev *pdev = to_pci_dev(dev->dev);
71 uint32_t data, jregd0, jregd1;
72
73 /* Defaults */
74 ast->config_mode = ast_use_defaults;
75 *scu_rev = 0xffffffff;
76
77 /* Check if we have device-tree properties */
78 if (np && !of_property_read_u32(np, "aspeed,scu-revision-id",
79 scu_rev)) {
80 /* We do, disable P2A access */
81 ast->config_mode = ast_use_dt;
82 drm_info(dev, "Using device-tree for configuration\n");
83 return;
84 }
85
86 /* Not all families have a P2A bridge */
87 if (pdev->device != PCI_CHIP_AST2000)
88 return;
89
90 /*
91 * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge
92 * is disabled. We force using P2A if VGA only mode bit
93 * is set D[7]
94 */
95 jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
96 jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
97 if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) {
98 /* Patch AST2500 */
99 if (((pdev->revision & 0xF0) == 0x40)
100 && ((jregd0 & AST_VRAM_INIT_STATUS_MASK) == 0))
101 ast_patch_ahb_2500(ast);
102
103 /* Double check it's actually working */
104 data = ast_read32(ast, 0xf004);
105 if ((data != 0xFFFFFFFF) && (data != 0x00)) {
106 /* P2A works, grab silicon revision */
107 ast->config_mode = ast_use_p2a;
108
109 drm_info(dev, "Using P2A bridge for configuration\n");
110
111 /* Read SCU7c (silicon revision register) */
112 ast_write32(ast, 0xf004, 0x1e6e0000);
113 ast_write32(ast, 0xf000, 0x1);
114 *scu_rev = ast_read32(ast, 0x1207c);
115 return;
116 }
117 }
118
119 /* We have a P2A bridge but it's disabled */
120 drm_info(dev, "P2A bridge disabled, using default configuration\n");
121 }
122
ast_detect_chip(struct drm_device * dev,bool * need_post)123 static int ast_detect_chip(struct drm_device *dev, bool *need_post)
124 {
125 struct ast_private *ast = to_ast_private(dev);
126 struct pci_dev *pdev = to_pci_dev(dev->dev);
127 uint32_t jreg, scu_rev;
128
129 /*
130 * If VGA isn't enabled, we need to enable now or subsequent
131 * access to the scratch registers will fail. We also inform
132 * our caller that it needs to POST the chip
133 * (Assumption: VGA not enabled -> need to POST)
134 */
135 if (!ast_is_vga_enabled(dev)) {
136 ast_enable_vga(dev);
137 drm_info(dev, "VGA not enabled on entry, requesting chip POST\n");
138 *need_post = true;
139 } else
140 *need_post = false;
141
142
143 /* Enable extended register access */
144 ast_open_key(ast);
145 ast_enable_mmio(dev);
146
147 /* Find out whether P2A works or whether to use device-tree */
148 ast_detect_config_mode(dev, &scu_rev);
149
150 /* Identify chipset */
151 if (pdev->revision >= 0x50) {
152 ast->chip = AST2600;
153 drm_info(dev, "AST 2600 detected\n");
154 } else if (pdev->revision >= 0x40) {
155 ast->chip = AST2500;
156 drm_info(dev, "AST 2500 detected\n");
157 } else if (pdev->revision >= 0x30) {
158 ast->chip = AST2400;
159 drm_info(dev, "AST 2400 detected\n");
160 } else if (pdev->revision >= 0x20) {
161 ast->chip = AST2300;
162 drm_info(dev, "AST 2300 detected\n");
163 } else if (pdev->revision >= 0x10) {
164 switch (scu_rev & 0x0300) {
165 case 0x0200:
166 ast->chip = AST1100;
167 drm_info(dev, "AST 1100 detected\n");
168 break;
169 case 0x0100:
170 ast->chip = AST2200;
171 drm_info(dev, "AST 2200 detected\n");
172 break;
173 case 0x0000:
174 ast->chip = AST2150;
175 drm_info(dev, "AST 2150 detected\n");
176 break;
177 default:
178 ast->chip = AST2100;
179 drm_info(dev, "AST 2100 detected\n");
180 break;
181 }
182 ast->vga2_clone = false;
183 } else {
184 ast->chip = AST2000;
185 drm_info(dev, "AST 2000 detected\n");
186 }
187
188 /* Check if we support wide screen */
189 switch (ast->chip) {
190 case AST2000:
191 ast->support_wide_screen = false;
192 break;
193 default:
194 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
195 if (!(jreg & 0x80))
196 ast->support_wide_screen = true;
197 else if (jreg & 0x01)
198 ast->support_wide_screen = true;
199 else {
200 ast->support_wide_screen = false;
201 if (ast->chip == AST2300 &&
202 (scu_rev & 0x300) == 0x0) /* ast1300 */
203 ast->support_wide_screen = true;
204 if (ast->chip == AST2400 &&
205 (scu_rev & 0x300) == 0x100) /* ast1400 */
206 ast->support_wide_screen = true;
207 if (ast->chip == AST2500 &&
208 scu_rev == 0x100) /* ast2510 */
209 ast->support_wide_screen = true;
210 if (ast->chip == AST2600) /* ast2600 */
211 ast->support_wide_screen = true;
212 }
213 break;
214 }
215
216 /* Check 3rd Tx option (digital output afaik) */
217 ast->tx_chip_types |= AST_TX_NONE_BIT;
218
219 /*
220 * VGACRA3 Enhanced Color Mode Register, check if DVO is already
221 * enabled, in that case, assume we have a SIL164 TMDS transmitter
222 *
223 * Don't make that assumption if we the chip wasn't enabled and
224 * is at power-on reset, otherwise we'll incorrectly "detect" a
225 * SIL164 when there is none.
226 */
227 if (!*need_post) {
228 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff);
229 if (jreg & 0x80)
230 ast->tx_chip_types = AST_TX_SIL164_BIT;
231 }
232
233 if ((ast->chip == AST2300) || (ast->chip == AST2400) || (ast->chip == AST2500)) {
234 /*
235 * On AST2300 and 2400, look the configuration set by the SoC in
236 * the SOC scratch register #1 bits 11:8 (interestingly marked
237 * as "reserved" in the spec)
238 */
239 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
240 switch (jreg) {
241 case 0x04:
242 ast->tx_chip_types = AST_TX_SIL164_BIT;
243 break;
244 case 0x08:
245 ast->dp501_fw_addr = drmm_kzalloc(dev, 32*1024, GFP_KERNEL);
246 if (ast->dp501_fw_addr) {
247 /* backup firmware */
248 if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) {
249 drmm_kfree(dev, ast->dp501_fw_addr);
250 ast->dp501_fw_addr = NULL;
251 }
252 }
253 fallthrough;
254 case 0x0c:
255 ast->tx_chip_types = AST_TX_DP501_BIT;
256 }
257 } else if (ast->chip == AST2600)
258 ast_dp_launch(&ast->base, 0);
259
260 /* Print stuff for diagnostic purposes */
261 if (ast->tx_chip_types & AST_TX_NONE_BIT)
262 drm_info(dev, "Using analog VGA\n");
263 if (ast->tx_chip_types & AST_TX_SIL164_BIT)
264 drm_info(dev, "Using Sil164 TMDS transmitter\n");
265 if (ast->tx_chip_types & AST_TX_DP501_BIT)
266 drm_info(dev, "Using DP501 DisplayPort transmitter\n");
267
268 return 0;
269 }
270
ast_get_dram_info(struct drm_device * dev)271 static int ast_get_dram_info(struct drm_device *dev)
272 {
273 struct device_node *np = dev->dev->of_node;
274 struct ast_private *ast = to_ast_private(dev);
275 uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
276 uint32_t denum, num, div, ref_pll, dsel;
277
278 switch (ast->config_mode) {
279 case ast_use_dt:
280 /*
281 * If some properties are missing, use reasonable
282 * defaults for AST2400
283 */
284 if (of_property_read_u32(np, "aspeed,mcr-configuration",
285 &mcr_cfg))
286 mcr_cfg = 0x00000577;
287 if (of_property_read_u32(np, "aspeed,mcr-scu-mpll",
288 &mcr_scu_mpll))
289 mcr_scu_mpll = 0x000050C0;
290 if (of_property_read_u32(np, "aspeed,mcr-scu-strap",
291 &mcr_scu_strap))
292 mcr_scu_strap = 0;
293 break;
294 case ast_use_p2a:
295 ast_write32(ast, 0xf004, 0x1e6e0000);
296 ast_write32(ast, 0xf000, 0x1);
297 mcr_cfg = ast_read32(ast, 0x10004);
298 mcr_scu_mpll = ast_read32(ast, 0x10120);
299 mcr_scu_strap = ast_read32(ast, 0x10170);
300 break;
301 case ast_use_defaults:
302 default:
303 ast->dram_bus_width = 16;
304 ast->dram_type = AST_DRAM_1Gx16;
305 if (ast->chip == AST2500)
306 ast->mclk = 800;
307 else
308 ast->mclk = 396;
309 return 0;
310 }
311
312 if (mcr_cfg & 0x40)
313 ast->dram_bus_width = 16;
314 else
315 ast->dram_bus_width = 32;
316
317 if (ast->chip == AST2500) {
318 switch (mcr_cfg & 0x03) {
319 case 0:
320 ast->dram_type = AST_DRAM_1Gx16;
321 break;
322 default:
323 case 1:
324 ast->dram_type = AST_DRAM_2Gx16;
325 break;
326 case 2:
327 ast->dram_type = AST_DRAM_4Gx16;
328 break;
329 case 3:
330 ast->dram_type = AST_DRAM_8Gx16;
331 break;
332 }
333 } else if (ast->chip == AST2300 || ast->chip == AST2400) {
334 switch (mcr_cfg & 0x03) {
335 case 0:
336 ast->dram_type = AST_DRAM_512Mx16;
337 break;
338 default:
339 case 1:
340 ast->dram_type = AST_DRAM_1Gx16;
341 break;
342 case 2:
343 ast->dram_type = AST_DRAM_2Gx16;
344 break;
345 case 3:
346 ast->dram_type = AST_DRAM_4Gx16;
347 break;
348 }
349 } else {
350 switch (mcr_cfg & 0x0c) {
351 case 0:
352 case 4:
353 ast->dram_type = AST_DRAM_512Mx16;
354 break;
355 case 8:
356 if (mcr_cfg & 0x40)
357 ast->dram_type = AST_DRAM_1Gx16;
358 else
359 ast->dram_type = AST_DRAM_512Mx32;
360 break;
361 case 0xc:
362 ast->dram_type = AST_DRAM_1Gx32;
363 break;
364 }
365 }
366
367 if (mcr_scu_strap & 0x2000)
368 ref_pll = 14318;
369 else
370 ref_pll = 12000;
371
372 denum = mcr_scu_mpll & 0x1f;
373 num = (mcr_scu_mpll & 0x3fe0) >> 5;
374 dsel = (mcr_scu_mpll & 0xc000) >> 14;
375 switch (dsel) {
376 case 3:
377 div = 0x4;
378 break;
379 case 2:
380 case 1:
381 div = 0x2;
382 break;
383 default:
384 div = 0x1;
385 break;
386 }
387 ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000));
388 return 0;
389 }
390
391 /*
392 * Run this function as part of the HW device cleanup; not
393 * when the DRM device gets released.
394 */
ast_device_release(void * data)395 static void ast_device_release(void *data)
396 {
397 struct ast_private *ast = data;
398
399 /* enable standard VGA decode */
400 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x04);
401 }
402
ast_device_create(const struct drm_driver * drv,struct pci_dev * pdev,unsigned long flags)403 struct ast_private *ast_device_create(const struct drm_driver *drv,
404 struct pci_dev *pdev,
405 unsigned long flags)
406 {
407 struct drm_device *dev;
408 struct ast_private *ast;
409 bool need_post;
410 int ret = 0;
411
412 ast = devm_drm_dev_alloc(&pdev->dev, drv, struct ast_private, base);
413 if (IS_ERR(ast))
414 return ast;
415 dev = &ast->base;
416
417 pci_set_drvdata(pdev, dev);
418
419 ret = drmm_mutex_init(dev, &ast->ioregs_lock);
420 if (ret)
421 return ERR_PTR(ret);
422
423 ast->regs = pcim_iomap(pdev, 1, 0);
424 if (!ast->regs)
425 return ERR_PTR(-EIO);
426
427 /*
428 * If we don't have IO space at all, use MMIO now and
429 * assume the chip has MMIO enabled by default (rev 0x20
430 * and higher).
431 */
432 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_IO)) {
433 drm_info(dev, "platform has no IO space, trying MMIO\n");
434 ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
435 }
436
437 /* "map" IO regs if the above hasn't done so already */
438 if (!ast->ioregs) {
439 ast->ioregs = pcim_iomap(pdev, 2, 0);
440 if (!ast->ioregs)
441 return ERR_PTR(-EIO);
442 }
443
444 ast_detect_chip(dev, &need_post);
445
446 ret = ast_get_dram_info(dev);
447 if (ret)
448 return ERR_PTR(ret);
449
450 drm_info(dev, "dram MCLK=%u Mhz type=%d bus_width=%d\n",
451 ast->mclk, ast->dram_type, ast->dram_bus_width);
452
453 if (need_post)
454 ast_post_gpu(dev);
455
456 ret = ast_mm_init(ast);
457 if (ret)
458 return ERR_PTR(ret);
459
460 /* map reserved buffer */
461 ast->dp501_fw_buf = NULL;
462 if (ast->vram_size < pci_resource_len(pdev, 0)) {
463 ast->dp501_fw_buf = pci_iomap_range(pdev, 0, ast->vram_size, 0);
464 if (!ast->dp501_fw_buf)
465 drm_info(dev, "failed to map reserved buffer!\n");
466 }
467
468 ret = ast_mode_config_init(ast);
469 if (ret)
470 return ERR_PTR(ret);
471
472 ret = devm_add_action_or_reset(dev->dev, ast_device_release, ast);
473 if (ret)
474 return ERR_PTR(ret);
475
476 return ast;
477 }
478