1 /*
2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <arch.h>
12 #include <arch_features.h>
13 #include <arch_helpers.h>
14 #include <bl1/bl1.h>
15 #include <common/bl_common.h>
16 #include <common/debug.h>
17 #include <drivers/auth/auth_mod.h>
18 #include <drivers/auth/crypto_mod.h>
19 #include <drivers/console.h>
20 #include <lib/cpus/errata_report.h>
21 #include <lib/utils.h>
22 #include <plat/common/platform.h>
23 #include <smccc_helpers.h>
24 #include <tools_share/uuid.h>
25
26 #include "bl1_private.h"
27
28 static void bl1_load_bl2(void);
29
30 #if ENABLE_PAUTH
31 uint64_t bl1_apiakey[2];
32 #endif
33
34 /*******************************************************************************
35 * Helper utility to calculate the BL2 memory layout taking into consideration
36 * the BL1 RW data assuming that it is at the top of the memory layout.
37 ******************************************************************************/
bl1_calc_bl2_mem_layout(const meminfo_t * bl1_mem_layout,meminfo_t * bl2_mem_layout)38 void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
39 meminfo_t *bl2_mem_layout)
40 {
41 assert(bl1_mem_layout != NULL);
42 assert(bl2_mem_layout != NULL);
43
44 /*
45 * Remove BL1 RW data from the scope of memory visible to BL2.
46 * This is assuming BL1 RW data is at the top of bl1_mem_layout.
47 */
48 assert(BL1_RW_BASE > bl1_mem_layout->total_base);
49 bl2_mem_layout->total_base = bl1_mem_layout->total_base;
50 bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base;
51
52 flush_dcache_range((uintptr_t)bl2_mem_layout, sizeof(meminfo_t));
53 }
54
55 /*******************************************************************************
56 * Setup function for BL1.
57 ******************************************************************************/
bl1_setup(void)58 void bl1_setup(void)
59 {
60 /* Perform early platform-specific setup */
61 bl1_early_platform_setup();
62
63 /* Perform late platform-specific setup */
64 bl1_plat_arch_setup();
65
66 #if CTX_INCLUDE_PAUTH_REGS
67 /*
68 * Assert that the ARMv8.3-PAuth registers are present or an access
69 * fault will be triggered when they are being saved or restored.
70 */
71 assert(is_armv8_3_pauth_present());
72 #endif /* CTX_INCLUDE_PAUTH_REGS */
73 }
74
75 /*******************************************************************************
76 * Function to perform late architectural and platform specific initialization.
77 * It also queries the platform to load and run next BL image. Only called
78 * by the primary cpu after a cold boot.
79 ******************************************************************************/
bl1_main(void)80 void bl1_main(void)
81 {
82 unsigned int image_id;
83
84 /* Announce our arrival */
85 NOTICE(FIRMWARE_WELCOME_STR);
86 NOTICE("BL1: %s\n", version_string);
87 NOTICE("BL1: %s\n", build_message);
88
89 INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, (void *)BL1_RAM_LIMIT);
90
91 print_errata_status();
92
93 #if ENABLE_ASSERTIONS
94 u_register_t val;
95 /*
96 * Ensure that MMU/Caches and coherency are turned on
97 */
98 #ifdef __aarch64__
99 val = read_sctlr_el3();
100 #else
101 val = read_sctlr();
102 #endif
103 assert((val & SCTLR_M_BIT) != 0);
104 assert((val & SCTLR_C_BIT) != 0);
105 assert((val & SCTLR_I_BIT) != 0);
106 /*
107 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the
108 * provided platform value
109 */
110 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
111 /*
112 * If CWG is zero, then no CWG information is available but we can
113 * at least check the platform value is less than the architectural
114 * maximum.
115 */
116 if (val != 0)
117 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
118 else
119 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
120 #endif /* ENABLE_ASSERTIONS */
121
122 /* Perform remaining generic architectural setup from EL3 */
123 bl1_arch_setup();
124
125 crypto_mod_init();
126
127 /* Initialize authentication module */
128 auth_mod_init();
129
130 /* Initialize the measured boot */
131 bl1_plat_mboot_init();
132
133 /* Perform platform setup in BL1. */
134 bl1_platform_setup();
135
136 #if ENABLE_PAUTH
137 /* Store APIAKey_EL1 key */
138 bl1_apiakey[0] = read_apiakeylo_el1();
139 bl1_apiakey[1] = read_apiakeyhi_el1();
140 #endif /* ENABLE_PAUTH */
141
142 /* Get the image id of next image to load and run. */
143 image_id = bl1_plat_get_next_image_id();
144
145 /*
146 * We currently interpret any image id other than
147 * BL2_IMAGE_ID as the start of firmware update.
148 */
149 if (image_id == BL2_IMAGE_ID)
150 bl1_load_bl2();
151 else
152 NOTICE("BL1-FWU: *******FWU Process Started*******\n");
153
154 /* Teardown the measured boot driver */
155 bl1_plat_mboot_finish();
156
157 bl1_prepare_next_image(image_id);
158
159 console_flush();
160 }
161
162 /*******************************************************************************
163 * This function locates and loads the BL2 raw binary image in the trusted SRAM.
164 * Called by the primary cpu after a cold boot.
165 * TODO: Add support for alternative image load mechanism e.g using virtio/elf
166 * loader etc.
167 ******************************************************************************/
bl1_load_bl2(void)168 static void bl1_load_bl2(void)
169 {
170 image_desc_t *desc;
171 image_info_t *info;
172 int err;
173
174 /* Get the image descriptor */
175 desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
176 assert(desc != NULL);
177
178 /* Get the image info */
179 info = &desc->image_info;
180 INFO("BL1: Loading BL2\n");
181
182 err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID);
183 if (err != 0) {
184 ERROR("Failure in pre image load handling of BL2 (%d)\n", err);
185 plat_error_handler(err);
186 }
187
188 err = load_auth_image(BL2_IMAGE_ID, info);
189 if (err != 0) {
190 ERROR("Failed to load BL2 firmware.\n");
191 plat_error_handler(err);
192 }
193
194 /* Allow platform to handle image information. */
195 err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID);
196 if (err != 0) {
197 ERROR("Failure in post image load handling of BL2 (%d)\n", err);
198 plat_error_handler(err);
199 }
200
201 NOTICE("BL1: Booting BL2\n");
202 }
203
204 /*******************************************************************************
205 * Function called just before handing over to the next BL to inform the user
206 * about the boot progress. In debug mode, also print details about the BL
207 * image's execution context.
208 ******************************************************************************/
bl1_print_next_bl_ep_info(const entry_point_info_t * bl_ep_info)209 void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info)
210 {
211 #ifdef __aarch64__
212 NOTICE("BL1: Booting BL31\n");
213 #else
214 NOTICE("BL1: Booting BL32\n");
215 #endif /* __aarch64__ */
216 print_entry_point_info(bl_ep_info);
217 }
218
219 #if SPIN_ON_BL1_EXIT
print_debug_loop_message(void)220 void print_debug_loop_message(void)
221 {
222 NOTICE("BL1: Debug loop, spinning forever\n");
223 NOTICE("BL1: Please connect the debugger to continue\n");
224 }
225 #endif
226
227 /*******************************************************************************
228 * Top level handler for servicing BL1 SMCs.
229 ******************************************************************************/
bl1_smc_handler(unsigned int smc_fid,u_register_t x1,u_register_t x2,u_register_t x3,u_register_t x4,void * cookie,void * handle,unsigned int flags)230 u_register_t bl1_smc_handler(unsigned int smc_fid,
231 u_register_t x1,
232 u_register_t x2,
233 u_register_t x3,
234 u_register_t x4,
235 void *cookie,
236 void *handle,
237 unsigned int flags)
238 {
239 /* BL1 Service UUID */
240 DEFINE_SVC_UUID2(bl1_svc_uid,
241 U(0xd46739fd), 0xcb72, 0x9a4d, 0xb5, 0x75,
242 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a);
243
244
245 #if TRUSTED_BOARD_BOOT
246 /*
247 * Dispatch FWU calls to FWU SMC handler and return its return
248 * value
249 */
250 if (is_fwu_fid(smc_fid)) {
251 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
252 handle, flags);
253 }
254 #endif
255
256 switch (smc_fid) {
257 case BL1_SMC_CALL_COUNT:
258 SMC_RET1(handle, BL1_NUM_SMC_CALLS);
259
260 case BL1_SMC_UID:
261 SMC_UUID_RET(handle, bl1_svc_uid);
262
263 case BL1_SMC_VERSION:
264 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER);
265
266 default:
267 WARN("Unimplemented BL1 SMC Call: 0x%x\n", smc_fid);
268 SMC_RET1(handle, SMC_UNK);
269 }
270 }
271
272 /*******************************************************************************
273 * BL1 SMC wrapper. This function is only used in AArch32 mode to ensure ABI
274 * compliance when invoking bl1_smc_handler.
275 ******************************************************************************/
bl1_smc_wrapper(uint32_t smc_fid,void * cookie,void * handle,unsigned int flags)276 u_register_t bl1_smc_wrapper(uint32_t smc_fid,
277 void *cookie,
278 void *handle,
279 unsigned int flags)
280 {
281 u_register_t x1, x2, x3, x4;
282
283 assert(handle != NULL);
284
285 get_smc_params_from_ctx(handle, x1, x2, x3, x4);
286 return bl1_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
287 }
288