1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2021 Broadcom Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9 #include <linux/kernel.h>
10 #include <linux/errno.h>
11 #include <linux/pci.h>
12 #include <linux/netdevice.h>
13 #include <linux/etherdevice.h>
14 #include <linux/net_tstamp.h>
15 #include <linux/timekeeping.h>
16 #include <linux/ptp_classify.h>
17 #include <linux/clocksource.h>
18 #include "bnxt_hsi.h"
19 #include "bnxt.h"
20 #include "bnxt_hwrm.h"
21 #include "bnxt_ptp.h"
22
bnxt_ptp_cfg_settime(struct bnxt * bp,u64 time)23 static int bnxt_ptp_cfg_settime(struct bnxt *bp, u64 time)
24 {
25 struct hwrm_func_ptp_cfg_input *req;
26 int rc;
27
28 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG);
29 if (rc)
30 return rc;
31
32 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME);
33 req->ptp_set_time = cpu_to_le64(time);
34 return hwrm_req_send(bp, req);
35 }
36
bnxt_ptp_parse(struct sk_buff * skb,u16 * seq_id,u16 * hdr_off)37 int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id, u16 *hdr_off)
38 {
39 unsigned int ptp_class;
40 struct ptp_header *hdr;
41
42 ptp_class = ptp_classify_raw(skb);
43
44 switch (ptp_class & PTP_CLASS_VMASK) {
45 case PTP_CLASS_V1:
46 case PTP_CLASS_V2:
47 hdr = ptp_parse_header(skb, ptp_class);
48 if (!hdr)
49 return -EINVAL;
50
51 *hdr_off = (u8 *)hdr - skb->data;
52 *seq_id = ntohs(hdr->sequence_id);
53 return 0;
54 default:
55 return -ERANGE;
56 }
57 }
58
bnxt_ptp_settime(struct ptp_clock_info * ptp_info,const struct timespec64 * ts)59 static int bnxt_ptp_settime(struct ptp_clock_info *ptp_info,
60 const struct timespec64 *ts)
61 {
62 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
63 ptp_info);
64 u64 ns = timespec64_to_ns(ts);
65
66 if (ptp->bp->fw_cap & BNXT_FW_CAP_PTP_RTC)
67 return bnxt_ptp_cfg_settime(ptp->bp, ns);
68
69 spin_lock_bh(&ptp->ptp_lock);
70 timecounter_init(&ptp->tc, &ptp->cc, ns);
71 spin_unlock_bh(&ptp->ptp_lock);
72 return 0;
73 }
74
75 /* Caller holds ptp_lock */
bnxt_refclk_read(struct bnxt * bp,struct ptp_system_timestamp * sts,u64 * ns)76 static int bnxt_refclk_read(struct bnxt *bp, struct ptp_system_timestamp *sts,
77 u64 *ns)
78 {
79 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
80 u32 high_before, high_now, low;
81
82 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
83 return -EIO;
84
85 high_before = readl(bp->bar0 + ptp->refclk_mapped_regs[1]);
86 ptp_read_system_prets(sts);
87 low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]);
88 ptp_read_system_postts(sts);
89 high_now = readl(bp->bar0 + ptp->refclk_mapped_regs[1]);
90 if (high_now != high_before) {
91 ptp_read_system_prets(sts);
92 low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]);
93 ptp_read_system_postts(sts);
94 }
95 *ns = ((u64)high_now << 32) | low;
96
97 return 0;
98 }
99
bnxt_ptp_get_current_time(struct bnxt * bp)100 static void bnxt_ptp_get_current_time(struct bnxt *bp)
101 {
102 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
103
104 if (!ptp)
105 return;
106 spin_lock_bh(&ptp->ptp_lock);
107 WRITE_ONCE(ptp->old_time, ptp->current_time);
108 bnxt_refclk_read(bp, NULL, &ptp->current_time);
109 spin_unlock_bh(&ptp->ptp_lock);
110 }
111
bnxt_hwrm_port_ts_query(struct bnxt * bp,u32 flags,u64 * ts)112 static int bnxt_hwrm_port_ts_query(struct bnxt *bp, u32 flags, u64 *ts)
113 {
114 struct hwrm_port_ts_query_output *resp;
115 struct hwrm_port_ts_query_input *req;
116 int rc;
117
118 rc = hwrm_req_init(bp, req, HWRM_PORT_TS_QUERY);
119 if (rc)
120 return rc;
121
122 req->flags = cpu_to_le32(flags);
123 if ((flags & PORT_TS_QUERY_REQ_FLAGS_PATH) ==
124 PORT_TS_QUERY_REQ_FLAGS_PATH_TX) {
125 req->enables = cpu_to_le16(BNXT_PTP_QTS_TX_ENABLES);
126 req->ptp_seq_id = cpu_to_le32(bp->ptp_cfg->tx_seqid);
127 req->ptp_hdr_offset = cpu_to_le16(bp->ptp_cfg->tx_hdr_off);
128 req->ts_req_timeout = cpu_to_le16(BNXT_PTP_QTS_TIMEOUT);
129 }
130 resp = hwrm_req_hold(bp, req);
131
132 rc = hwrm_req_send(bp, req);
133 if (!rc)
134 *ts = le64_to_cpu(resp->ptp_msg_ts);
135 hwrm_req_drop(bp, req);
136 return rc;
137 }
138
bnxt_ptp_gettimex(struct ptp_clock_info * ptp_info,struct timespec64 * ts,struct ptp_system_timestamp * sts)139 static int bnxt_ptp_gettimex(struct ptp_clock_info *ptp_info,
140 struct timespec64 *ts,
141 struct ptp_system_timestamp *sts)
142 {
143 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
144 ptp_info);
145 u64 ns, cycles;
146 int rc;
147
148 spin_lock_bh(&ptp->ptp_lock);
149 rc = bnxt_refclk_read(ptp->bp, sts, &cycles);
150 if (rc) {
151 spin_unlock_bh(&ptp->ptp_lock);
152 return rc;
153 }
154 ns = timecounter_cyc2time(&ptp->tc, cycles);
155 spin_unlock_bh(&ptp->ptp_lock);
156 *ts = ns_to_timespec64(ns);
157
158 return 0;
159 }
160
161 /* Caller holds ptp_lock */
bnxt_ptp_update_current_time(struct bnxt * bp)162 void bnxt_ptp_update_current_time(struct bnxt *bp)
163 {
164 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
165
166 bnxt_refclk_read(ptp->bp, NULL, &ptp->current_time);
167 WRITE_ONCE(ptp->old_time, ptp->current_time);
168 }
169
bnxt_ptp_adjphc(struct bnxt_ptp_cfg * ptp,s64 delta)170 static int bnxt_ptp_adjphc(struct bnxt_ptp_cfg *ptp, s64 delta)
171 {
172 struct hwrm_port_mac_cfg_input *req;
173 int rc;
174
175 rc = hwrm_req_init(ptp->bp, req, HWRM_PORT_MAC_CFG);
176 if (rc)
177 return rc;
178
179 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE);
180 req->ptp_adj_phase = cpu_to_le64(delta);
181
182 rc = hwrm_req_send(ptp->bp, req);
183 if (rc) {
184 netdev_err(ptp->bp->dev, "ptp adjphc failed. rc = %x\n", rc);
185 } else {
186 spin_lock_bh(&ptp->ptp_lock);
187 bnxt_ptp_update_current_time(ptp->bp);
188 spin_unlock_bh(&ptp->ptp_lock);
189 }
190
191 return rc;
192 }
193
bnxt_ptp_adjtime(struct ptp_clock_info * ptp_info,s64 delta)194 static int bnxt_ptp_adjtime(struct ptp_clock_info *ptp_info, s64 delta)
195 {
196 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
197 ptp_info);
198
199 if (ptp->bp->fw_cap & BNXT_FW_CAP_PTP_RTC)
200 return bnxt_ptp_adjphc(ptp, delta);
201
202 spin_lock_bh(&ptp->ptp_lock);
203 timecounter_adjtime(&ptp->tc, delta);
204 spin_unlock_bh(&ptp->ptp_lock);
205 return 0;
206 }
207
bnxt_ptp_adjfine(struct ptp_clock_info * ptp_info,long scaled_ppm)208 static int bnxt_ptp_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
209 {
210 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
211 ptp_info);
212 struct hwrm_port_mac_cfg_input *req;
213 struct bnxt *bp = ptp->bp;
214 int rc = 0;
215
216 if (!(ptp->bp->fw_cap & BNXT_FW_CAP_PTP_RTC)) {
217 spin_lock_bh(&ptp->ptp_lock);
218 timecounter_read(&ptp->tc);
219 ptp->cc.mult = adjust_by_scaled_ppm(ptp->cmult, scaled_ppm);
220 spin_unlock_bh(&ptp->ptp_lock);
221 } else {
222 s32 ppb = scaled_ppm_to_ppb(scaled_ppm);
223
224 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG);
225 if (rc)
226 return rc;
227
228 req->ptp_freq_adj_ppb = cpu_to_le32(ppb);
229 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB);
230 rc = hwrm_req_send(ptp->bp, req);
231 if (rc)
232 netdev_err(ptp->bp->dev,
233 "ptp adjfine failed. rc = %d\n", rc);
234 }
235 return rc;
236 }
237
bnxt_ptp_pps_event(struct bnxt * bp,u32 data1,u32 data2)238 void bnxt_ptp_pps_event(struct bnxt *bp, u32 data1, u32 data2)
239 {
240 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
241 struct ptp_clock_event event;
242 u64 ns, pps_ts;
243
244 pps_ts = EVENT_PPS_TS(data2, data1);
245 spin_lock_bh(&ptp->ptp_lock);
246 ns = timecounter_cyc2time(&ptp->tc, pps_ts);
247 spin_unlock_bh(&ptp->ptp_lock);
248
249 switch (EVENT_DATA2_PPS_EVENT_TYPE(data2)) {
250 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL:
251 event.pps_times.ts_real = ns_to_timespec64(ns);
252 event.type = PTP_CLOCK_PPSUSR;
253 event.index = EVENT_DATA2_PPS_PIN_NUM(data2);
254 break;
255 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL:
256 event.timestamp = ns;
257 event.type = PTP_CLOCK_EXTTS;
258 event.index = EVENT_DATA2_PPS_PIN_NUM(data2);
259 break;
260 }
261
262 ptp_clock_event(bp->ptp_cfg->ptp_clock, &event);
263 }
264
bnxt_ptp_cfg_pin(struct bnxt * bp,u8 pin,u8 usage)265 static int bnxt_ptp_cfg_pin(struct bnxt *bp, u8 pin, u8 usage)
266 {
267 struct hwrm_func_ptp_pin_cfg_input *req;
268 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
269 u8 state = usage != BNXT_PPS_PIN_NONE;
270 u8 *pin_state, *pin_usg;
271 u32 enables;
272 int rc;
273
274 if (!TSIO_PIN_VALID(pin)) {
275 netdev_err(ptp->bp->dev, "1PPS: Invalid pin. Check pin-function configuration\n");
276 return -EOPNOTSUPP;
277 }
278
279 rc = hwrm_req_init(ptp->bp, req, HWRM_FUNC_PTP_PIN_CFG);
280 if (rc)
281 return rc;
282
283 enables = (FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE |
284 FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE) << (pin * 2);
285 req->enables = cpu_to_le32(enables);
286
287 pin_state = &req->pin0_state;
288 pin_usg = &req->pin0_usage;
289
290 *(pin_state + (pin * 2)) = state;
291 *(pin_usg + (pin * 2)) = usage;
292
293 rc = hwrm_req_send(ptp->bp, req);
294 if (rc)
295 return rc;
296
297 ptp->pps_info.pins[pin].usage = usage;
298 ptp->pps_info.pins[pin].state = state;
299
300 return 0;
301 }
302
bnxt_ptp_cfg_event(struct bnxt * bp,u8 event)303 static int bnxt_ptp_cfg_event(struct bnxt *bp, u8 event)
304 {
305 struct hwrm_func_ptp_cfg_input *req;
306 int rc;
307
308 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG);
309 if (rc)
310 return rc;
311
312 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT);
313 req->ptp_pps_event = event;
314 return hwrm_req_send(bp, req);
315 }
316
bnxt_ptp_cfg_tstamp_filters(struct bnxt * bp)317 void bnxt_ptp_cfg_tstamp_filters(struct bnxt *bp)
318 {
319 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
320 struct hwrm_port_mac_cfg_input *req;
321
322 if (!ptp || !ptp->tstamp_filters)
323 return;
324
325 if (hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG))
326 goto out;
327
328 if (!(bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) && (ptp->tstamp_filters &
329 (PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE |
330 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE))) {
331 ptp->tstamp_filters &= ~(PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE |
332 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE);
333 netdev_warn(bp->dev, "Unsupported FW for all RX pkts timestamp filter\n");
334 }
335
336 req->flags = cpu_to_le32(ptp->tstamp_filters);
337 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
338 req->rx_ts_capture_ptp_msg_type = cpu_to_le16(ptp->rxctl);
339
340 if (!hwrm_req_send(bp, req)) {
341 bp->ptp_all_rx_tstamp = !!(ptp->tstamp_filters &
342 PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE);
343 return;
344 }
345 ptp->tstamp_filters = 0;
346 out:
347 bp->ptp_all_rx_tstamp = 0;
348 netdev_warn(bp->dev, "Failed to configure HW packet timestamp filters\n");
349 }
350
bnxt_ptp_reapply_pps(struct bnxt * bp)351 void bnxt_ptp_reapply_pps(struct bnxt *bp)
352 {
353 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
354 struct bnxt_pps *pps;
355 u32 pin = 0;
356 int rc;
357
358 if (!ptp || !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) ||
359 !(ptp->ptp_info.pin_config))
360 return;
361 pps = &ptp->pps_info;
362 for (pin = 0; pin < BNXT_MAX_TSIO_PINS; pin++) {
363 if (pps->pins[pin].state) {
364 rc = bnxt_ptp_cfg_pin(bp, pin, pps->pins[pin].usage);
365 if (!rc && pps->pins[pin].event)
366 rc = bnxt_ptp_cfg_event(bp,
367 pps->pins[pin].event);
368 if (rc)
369 netdev_err(bp->dev, "1PPS: Failed to configure pin%d\n",
370 pin);
371 }
372 }
373 }
374
bnxt_get_target_cycles(struct bnxt_ptp_cfg * ptp,u64 target_ns,u64 * cycles_delta)375 static int bnxt_get_target_cycles(struct bnxt_ptp_cfg *ptp, u64 target_ns,
376 u64 *cycles_delta)
377 {
378 u64 cycles_now;
379 u64 nsec_now, nsec_delta;
380 int rc;
381
382 spin_lock_bh(&ptp->ptp_lock);
383 rc = bnxt_refclk_read(ptp->bp, NULL, &cycles_now);
384 if (rc) {
385 spin_unlock_bh(&ptp->ptp_lock);
386 return rc;
387 }
388 nsec_now = timecounter_cyc2time(&ptp->tc, cycles_now);
389 spin_unlock_bh(&ptp->ptp_lock);
390
391 nsec_delta = target_ns - nsec_now;
392 *cycles_delta = div64_u64(nsec_delta << ptp->cc.shift, ptp->cc.mult);
393 return 0;
394 }
395
bnxt_ptp_perout_cfg(struct bnxt_ptp_cfg * ptp,struct ptp_clock_request * rq)396 static int bnxt_ptp_perout_cfg(struct bnxt_ptp_cfg *ptp,
397 struct ptp_clock_request *rq)
398 {
399 struct hwrm_func_ptp_cfg_input *req;
400 struct bnxt *bp = ptp->bp;
401 struct timespec64 ts;
402 u64 target_ns, delta;
403 u16 enables;
404 int rc;
405
406 ts.tv_sec = rq->perout.start.sec;
407 ts.tv_nsec = rq->perout.start.nsec;
408 target_ns = timespec64_to_ns(&ts);
409
410 rc = bnxt_get_target_cycles(ptp, target_ns, &delta);
411 if (rc)
412 return rc;
413
414 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG);
415 if (rc)
416 return rc;
417
418 enables = FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD |
419 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP |
420 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE;
421 req->enables = cpu_to_le16(enables);
422 req->ptp_pps_event = 0;
423 req->ptp_freq_adj_dll_source = 0;
424 req->ptp_freq_adj_dll_phase = 0;
425 req->ptp_freq_adj_ext_period = cpu_to_le32(NSEC_PER_SEC);
426 req->ptp_freq_adj_ext_up = 0;
427 req->ptp_freq_adj_ext_phase_lower = cpu_to_le32(delta);
428
429 return hwrm_req_send(bp, req);
430 }
431
bnxt_ptp_enable(struct ptp_clock_info * ptp_info,struct ptp_clock_request * rq,int on)432 static int bnxt_ptp_enable(struct ptp_clock_info *ptp_info,
433 struct ptp_clock_request *rq, int on)
434 {
435 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
436 ptp_info);
437 struct bnxt *bp = ptp->bp;
438 int pin_id;
439 int rc;
440
441 switch (rq->type) {
442 case PTP_CLK_REQ_EXTTS:
443 /* Configure an External PPS IN */
444 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_EXTTS,
445 rq->extts.index);
446 if (!TSIO_PIN_VALID(pin_id))
447 return -EOPNOTSUPP;
448 if (!on)
449 break;
450 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_IN);
451 if (rc)
452 return rc;
453 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_EXTERNAL);
454 if (!rc)
455 ptp->pps_info.pins[pin_id].event = BNXT_PPS_EVENT_EXTERNAL;
456 return rc;
457 case PTP_CLK_REQ_PEROUT:
458 /* Configure a Periodic PPS OUT */
459 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_PEROUT,
460 rq->perout.index);
461 if (!TSIO_PIN_VALID(pin_id))
462 return -EOPNOTSUPP;
463 if (!on)
464 break;
465
466 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_OUT);
467 if (!rc)
468 rc = bnxt_ptp_perout_cfg(ptp, rq);
469
470 return rc;
471 case PTP_CLK_REQ_PPS:
472 /* Configure PHC PPS IN */
473 rc = bnxt_ptp_cfg_pin(bp, 0, BNXT_PPS_PIN_PPS_IN);
474 if (rc)
475 return rc;
476 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_INTERNAL);
477 if (!rc)
478 ptp->pps_info.pins[0].event = BNXT_PPS_EVENT_INTERNAL;
479 return rc;
480 default:
481 netdev_err(ptp->bp->dev, "Unrecognized PIN function\n");
482 return -EOPNOTSUPP;
483 }
484
485 return bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_NONE);
486 }
487
bnxt_hwrm_ptp_cfg(struct bnxt * bp)488 static int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
489 {
490 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
491 u32 flags = 0;
492 int rc = 0;
493
494 switch (ptp->rx_filter) {
495 case HWTSTAMP_FILTER_ALL:
496 flags = PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE;
497 break;
498 case HWTSTAMP_FILTER_NONE:
499 flags = PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
500 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS)
501 flags |= PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE;
502 break;
503 case HWTSTAMP_FILTER_PTP_V2_EVENT:
504 case HWTSTAMP_FILTER_PTP_V2_SYNC:
505 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
506 flags = PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
507 break;
508 }
509
510 if (ptp->tx_tstamp_en)
511 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
512 else
513 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
514
515 ptp->tstamp_filters = flags;
516
517 if (netif_running(bp->dev)) {
518 if (ptp->rx_filter == HWTSTAMP_FILTER_ALL) {
519 rc = bnxt_close_nic(bp, false, false);
520 if (!rc)
521 rc = bnxt_open_nic(bp, false, false);
522 } else {
523 bnxt_ptp_cfg_tstamp_filters(bp);
524 }
525 if (!rc && !ptp->tstamp_filters)
526 rc = -EIO;
527 }
528
529 return rc;
530 }
531
bnxt_hwtstamp_set(struct net_device * dev,struct ifreq * ifr)532 int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
533 {
534 struct bnxt *bp = netdev_priv(dev);
535 struct hwtstamp_config stmpconf;
536 struct bnxt_ptp_cfg *ptp;
537 u16 old_rxctl;
538 int old_rx_filter, rc;
539 u8 old_tx_tstamp_en;
540
541 ptp = bp->ptp_cfg;
542 if (!ptp)
543 return -EOPNOTSUPP;
544
545 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
546 return -EFAULT;
547
548 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
549 stmpconf.tx_type != HWTSTAMP_TX_OFF)
550 return -ERANGE;
551
552 old_rx_filter = ptp->rx_filter;
553 old_rxctl = ptp->rxctl;
554 old_tx_tstamp_en = ptp->tx_tstamp_en;
555 switch (stmpconf.rx_filter) {
556 case HWTSTAMP_FILTER_NONE:
557 ptp->rxctl = 0;
558 ptp->rx_filter = HWTSTAMP_FILTER_NONE;
559 break;
560 case HWTSTAMP_FILTER_ALL:
561 if (bp->fw_cap & BNXT_FW_CAP_RX_ALL_PKT_TS) {
562 ptp->rx_filter = HWTSTAMP_FILTER_ALL;
563 break;
564 }
565 return -EOPNOTSUPP;
566 case HWTSTAMP_FILTER_PTP_V2_EVENT:
567 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
568 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
569 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
570 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
571 break;
572 case HWTSTAMP_FILTER_PTP_V2_SYNC:
573 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
574 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
575 ptp->rxctl = BNXT_PTP_MSG_SYNC;
576 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
577 break;
578 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
579 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
580 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
581 ptp->rxctl = BNXT_PTP_MSG_DELAY_REQ;
582 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
583 break;
584 default:
585 return -ERANGE;
586 }
587
588 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
589 ptp->tx_tstamp_en = 1;
590 else
591 ptp->tx_tstamp_en = 0;
592
593 rc = bnxt_hwrm_ptp_cfg(bp);
594 if (rc)
595 goto ts_set_err;
596
597 stmpconf.rx_filter = ptp->rx_filter;
598 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
599 -EFAULT : 0;
600
601 ts_set_err:
602 ptp->rx_filter = old_rx_filter;
603 ptp->rxctl = old_rxctl;
604 ptp->tx_tstamp_en = old_tx_tstamp_en;
605 return rc;
606 }
607
bnxt_hwtstamp_get(struct net_device * dev,struct ifreq * ifr)608 int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
609 {
610 struct bnxt *bp = netdev_priv(dev);
611 struct hwtstamp_config stmpconf;
612 struct bnxt_ptp_cfg *ptp;
613
614 ptp = bp->ptp_cfg;
615 if (!ptp)
616 return -EOPNOTSUPP;
617
618 stmpconf.flags = 0;
619 stmpconf.tx_type = ptp->tx_tstamp_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
620
621 stmpconf.rx_filter = ptp->rx_filter;
622 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
623 -EFAULT : 0;
624 }
625
bnxt_map_regs(struct bnxt * bp,u32 * reg_arr,int count,int reg_win)626 static int bnxt_map_regs(struct bnxt *bp, u32 *reg_arr, int count, int reg_win)
627 {
628 u32 reg_base = *reg_arr & BNXT_GRC_BASE_MASK;
629 u32 win_off;
630 int i;
631
632 for (i = 0; i < count; i++) {
633 if ((reg_arr[i] & BNXT_GRC_BASE_MASK) != reg_base)
634 return -ERANGE;
635 }
636 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
637 writel(reg_base, bp->bar0 + win_off);
638 return 0;
639 }
640
bnxt_map_ptp_regs(struct bnxt * bp)641 static int bnxt_map_ptp_regs(struct bnxt *bp)
642 {
643 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
644 u32 *reg_arr;
645 int rc, i;
646
647 reg_arr = ptp->refclk_regs;
648 if (bp->flags & BNXT_FLAG_CHIP_P5) {
649 rc = bnxt_map_regs(bp, reg_arr, 2, BNXT_PTP_GRC_WIN);
650 if (rc)
651 return rc;
652 for (i = 0; i < 2; i++)
653 ptp->refclk_mapped_regs[i] = BNXT_PTP_GRC_WIN_BASE +
654 (ptp->refclk_regs[i] & BNXT_GRC_OFFSET_MASK);
655 return 0;
656 }
657 return -ENODEV;
658 }
659
bnxt_unmap_ptp_regs(struct bnxt * bp)660 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
661 {
662 writel(0, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT +
663 (BNXT_PTP_GRC_WIN - 1) * 4);
664 }
665
bnxt_cc_read(const struct cyclecounter * cc)666 static u64 bnxt_cc_read(const struct cyclecounter *cc)
667 {
668 struct bnxt_ptp_cfg *ptp = container_of(cc, struct bnxt_ptp_cfg, cc);
669 u64 ns = 0;
670
671 bnxt_refclk_read(ptp->bp, NULL, &ns);
672 return ns;
673 }
674
bnxt_stamp_tx_skb(struct bnxt * bp,struct sk_buff * skb)675 static void bnxt_stamp_tx_skb(struct bnxt *bp, struct sk_buff *skb)
676 {
677 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
678 struct skb_shared_hwtstamps timestamp;
679 u64 ts = 0, ns = 0;
680 int rc;
681
682 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_PATH_TX, &ts);
683 if (!rc) {
684 memset(×tamp, 0, sizeof(timestamp));
685 spin_lock_bh(&ptp->ptp_lock);
686 ns = timecounter_cyc2time(&ptp->tc, ts);
687 spin_unlock_bh(&ptp->ptp_lock);
688 timestamp.hwtstamp = ns_to_ktime(ns);
689 skb_tstamp_tx(ptp->tx_skb, ×tamp);
690 } else {
691 netdev_err(bp->dev, "TS query for TX timer failed rc = %x\n",
692 rc);
693 }
694
695 dev_kfree_skb_any(ptp->tx_skb);
696 ptp->tx_skb = NULL;
697 atomic_inc(&ptp->tx_avail);
698 }
699
bnxt_ptp_ts_aux_work(struct ptp_clock_info * ptp_info)700 static long bnxt_ptp_ts_aux_work(struct ptp_clock_info *ptp_info)
701 {
702 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
703 ptp_info);
704 unsigned long now = jiffies;
705 struct bnxt *bp = ptp->bp;
706
707 if (ptp->tx_skb)
708 bnxt_stamp_tx_skb(bp, ptp->tx_skb);
709
710 if (!time_after_eq(now, ptp->next_period))
711 return ptp->next_period - now;
712
713 bnxt_ptp_get_current_time(bp);
714 ptp->next_period = now + HZ;
715 if (time_after_eq(now, ptp->next_overflow_check)) {
716 spin_lock_bh(&ptp->ptp_lock);
717 timecounter_read(&ptp->tc);
718 spin_unlock_bh(&ptp->ptp_lock);
719 ptp->next_overflow_check = now + BNXT_PHC_OVERFLOW_PERIOD;
720 }
721 return HZ;
722 }
723
bnxt_get_tx_ts_p5(struct bnxt * bp,struct sk_buff * skb)724 int bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb)
725 {
726 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
727
728 if (ptp->tx_skb) {
729 netdev_err(bp->dev, "deferring skb:one SKB is still outstanding\n");
730 return -EBUSY;
731 }
732 ptp->tx_skb = skb;
733 ptp_schedule_worker(ptp->ptp_clock, 0);
734 return 0;
735 }
736
bnxt_get_rx_ts_p5(struct bnxt * bp,u64 * ts,u32 pkt_ts)737 int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts)
738 {
739 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
740 u64 time;
741
742 if (!ptp)
743 return -ENODEV;
744
745 BNXT_READ_TIME64(ptp, time, ptp->old_time);
746 *ts = (time & BNXT_HI_TIMER_MASK) | pkt_ts;
747 if (pkt_ts < (time & BNXT_LO_TIMER_MASK))
748 *ts += BNXT_LO_TIMER_MASK + 1;
749
750 return 0;
751 }
752
753 static const struct ptp_clock_info bnxt_ptp_caps = {
754 .owner = THIS_MODULE,
755 .name = "bnxt clock",
756 .max_adj = BNXT_MAX_PHC_DRIFT,
757 .n_alarm = 0,
758 .n_ext_ts = 0,
759 .n_per_out = 0,
760 .n_pins = 0,
761 .pps = 0,
762 .adjfine = bnxt_ptp_adjfine,
763 .adjtime = bnxt_ptp_adjtime,
764 .do_aux_work = bnxt_ptp_ts_aux_work,
765 .gettimex64 = bnxt_ptp_gettimex,
766 .settime64 = bnxt_ptp_settime,
767 .enable = bnxt_ptp_enable,
768 };
769
bnxt_ptp_verify(struct ptp_clock_info * ptp_info,unsigned int pin,enum ptp_pin_function func,unsigned int chan)770 static int bnxt_ptp_verify(struct ptp_clock_info *ptp_info, unsigned int pin,
771 enum ptp_pin_function func, unsigned int chan)
772 {
773 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
774 ptp_info);
775 /* Allow only PPS pin function configuration */
776 if (ptp->pps_info.pins[pin].usage <= BNXT_PPS_PIN_PPS_OUT &&
777 func != PTP_PF_PHYSYNC)
778 return 0;
779 else
780 return -EOPNOTSUPP;
781 }
782
bnxt_ptp_pps_init(struct bnxt * bp)783 static int bnxt_ptp_pps_init(struct bnxt *bp)
784 {
785 struct hwrm_func_ptp_pin_qcfg_output *resp;
786 struct hwrm_func_ptp_pin_qcfg_input *req;
787 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
788 struct ptp_clock_info *ptp_info;
789 struct bnxt_pps *pps_info;
790 u8 *pin_usg;
791 u32 i, rc;
792
793 /* Query current/default PIN CFG */
794 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_PIN_QCFG);
795 if (rc)
796 return rc;
797
798 resp = hwrm_req_hold(bp, req);
799 rc = hwrm_req_send(bp, req);
800 if (rc || !resp->num_pins) {
801 hwrm_req_drop(bp, req);
802 return -EOPNOTSUPP;
803 }
804
805 ptp_info = &ptp->ptp_info;
806 pps_info = &ptp->pps_info;
807 pps_info->num_pins = resp->num_pins;
808 ptp_info->n_pins = pps_info->num_pins;
809 ptp_info->pin_config = kcalloc(ptp_info->n_pins,
810 sizeof(*ptp_info->pin_config),
811 GFP_KERNEL);
812 if (!ptp_info->pin_config) {
813 hwrm_req_drop(bp, req);
814 return -ENOMEM;
815 }
816
817 /* Report the TSIO capability to kernel */
818 pin_usg = &resp->pin0_usage;
819 for (i = 0; i < pps_info->num_pins; i++, pin_usg++) {
820 snprintf(ptp_info->pin_config[i].name,
821 sizeof(ptp_info->pin_config[i].name), "bnxt_pps%d", i);
822 ptp_info->pin_config[i].index = i;
823 ptp_info->pin_config[i].chan = i;
824 if (*pin_usg == BNXT_PPS_PIN_PPS_IN)
825 ptp_info->pin_config[i].func = PTP_PF_EXTTS;
826 else if (*pin_usg == BNXT_PPS_PIN_PPS_OUT)
827 ptp_info->pin_config[i].func = PTP_PF_PEROUT;
828 else
829 ptp_info->pin_config[i].func = PTP_PF_NONE;
830
831 pps_info->pins[i].usage = *pin_usg;
832 }
833 hwrm_req_drop(bp, req);
834
835 /* Only 1 each of ext_ts and per_out pins is available in HW */
836 ptp_info->n_ext_ts = 1;
837 ptp_info->n_per_out = 1;
838 ptp_info->pps = 1;
839 ptp_info->verify = bnxt_ptp_verify;
840
841 return 0;
842 }
843
bnxt_pps_config_ok(struct bnxt * bp)844 static bool bnxt_pps_config_ok(struct bnxt *bp)
845 {
846 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
847
848 return !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) == !ptp->ptp_info.pin_config;
849 }
850
bnxt_ptp_timecounter_init(struct bnxt * bp,bool init_tc)851 static void bnxt_ptp_timecounter_init(struct bnxt *bp, bool init_tc)
852 {
853 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
854
855 if (!ptp->ptp_clock) {
856 memset(&ptp->cc, 0, sizeof(ptp->cc));
857 ptp->cc.read = bnxt_cc_read;
858 ptp->cc.mask = CYCLECOUNTER_MASK(48);
859 ptp->cc.shift = BNXT_CYCLES_SHIFT;
860 ptp->cc.mult = clocksource_khz2mult(BNXT_DEVCLK_FREQ, ptp->cc.shift);
861 ptp->cmult = ptp->cc.mult;
862 ptp->next_overflow_check = jiffies + BNXT_PHC_OVERFLOW_PERIOD;
863 }
864 if (init_tc)
865 timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real()));
866 }
867
868 /* Caller holds ptp_lock */
bnxt_ptp_rtc_timecounter_init(struct bnxt_ptp_cfg * ptp,u64 ns)869 void bnxt_ptp_rtc_timecounter_init(struct bnxt_ptp_cfg *ptp, u64 ns)
870 {
871 timecounter_init(&ptp->tc, &ptp->cc, ns);
872 /* For RTC, cycle_last must be in sync with the timecounter value. */
873 ptp->tc.cycle_last = ns & ptp->cc.mask;
874 }
875
bnxt_ptp_init_rtc(struct bnxt * bp,bool phc_cfg)876 int bnxt_ptp_init_rtc(struct bnxt *bp, bool phc_cfg)
877 {
878 struct timespec64 tsp;
879 u64 ns;
880 int rc;
881
882 if (!bp->ptp_cfg || !(bp->fw_cap & BNXT_FW_CAP_PTP_RTC))
883 return -ENODEV;
884
885 if (!phc_cfg) {
886 ktime_get_real_ts64(&tsp);
887 ns = timespec64_to_ns(&tsp);
888 rc = bnxt_ptp_cfg_settime(bp, ns);
889 if (rc)
890 return rc;
891 } else {
892 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME, &ns);
893 if (rc)
894 return rc;
895 }
896 spin_lock_bh(&bp->ptp_cfg->ptp_lock);
897 bnxt_ptp_rtc_timecounter_init(bp->ptp_cfg, ns);
898 spin_unlock_bh(&bp->ptp_cfg->ptp_lock);
899
900 return 0;
901 }
902
bnxt_ptp_free(struct bnxt * bp)903 static void bnxt_ptp_free(struct bnxt *bp)
904 {
905 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
906
907 if (ptp->ptp_clock) {
908 ptp_clock_unregister(ptp->ptp_clock);
909 ptp->ptp_clock = NULL;
910 kfree(ptp->ptp_info.pin_config);
911 ptp->ptp_info.pin_config = NULL;
912 }
913 }
914
bnxt_ptp_init(struct bnxt * bp,bool phc_cfg)915 int bnxt_ptp_init(struct bnxt *bp, bool phc_cfg)
916 {
917 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
918 int rc;
919
920 if (!ptp)
921 return 0;
922
923 rc = bnxt_map_ptp_regs(bp);
924 if (rc)
925 return rc;
926
927 if (ptp->ptp_clock && bnxt_pps_config_ok(bp))
928 return 0;
929
930 bnxt_ptp_free(bp);
931
932 atomic_set(&ptp->tx_avail, BNXT_MAX_TX_TS);
933 spin_lock_init(&ptp->ptp_lock);
934
935 if (bp->fw_cap & BNXT_FW_CAP_PTP_RTC) {
936 bnxt_ptp_timecounter_init(bp, false);
937 rc = bnxt_ptp_init_rtc(bp, phc_cfg);
938 if (rc)
939 goto out;
940 } else {
941 bnxt_ptp_timecounter_init(bp, true);
942 }
943
944 ptp->ptp_info = bnxt_ptp_caps;
945 if ((bp->fw_cap & BNXT_FW_CAP_PTP_PPS)) {
946 if (bnxt_ptp_pps_init(bp))
947 netdev_err(bp->dev, "1pps not initialized, continuing without 1pps support\n");
948 }
949 ptp->ptp_clock = ptp_clock_register(&ptp->ptp_info, &bp->pdev->dev);
950 if (IS_ERR(ptp->ptp_clock)) {
951 int err = PTR_ERR(ptp->ptp_clock);
952
953 ptp->ptp_clock = NULL;
954 rc = err;
955 goto out;
956 }
957 if (bp->flags & BNXT_FLAG_CHIP_P5) {
958 spin_lock_bh(&ptp->ptp_lock);
959 bnxt_refclk_read(bp, NULL, &ptp->current_time);
960 WRITE_ONCE(ptp->old_time, ptp->current_time);
961 spin_unlock_bh(&ptp->ptp_lock);
962 ptp_schedule_worker(ptp->ptp_clock, 0);
963 }
964 return 0;
965
966 out:
967 bnxt_ptp_free(bp);
968 bnxt_unmap_ptp_regs(bp);
969 return rc;
970 }
971
bnxt_ptp_clear(struct bnxt * bp)972 void bnxt_ptp_clear(struct bnxt *bp)
973 {
974 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
975
976 if (!ptp)
977 return;
978
979 if (ptp->ptp_clock)
980 ptp_clock_unregister(ptp->ptp_clock);
981
982 ptp->ptp_clock = NULL;
983 kfree(ptp->ptp_info.pin_config);
984 ptp->ptp_info.pin_config = NULL;
985
986 if (ptp->tx_skb) {
987 dev_kfree_skb_any(ptp->tx_skb);
988 ptp->tx_skb = NULL;
989 }
990 bnxt_unmap_ptp_regs(bp);
991 }
992