1 /*
2 * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
4 * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include <common/debug.h>
10 #include <common/runtime_svc.h>
11 #include <drivers/generic_delay_timer.h>
12 #include <lib/mmio.h>
13 #include <lib/xlat_tables/xlat_tables_v2.h>
14 #include <plat/common/platform.h>
15 #include <plat_ipi.h>
16
17 #include <plat_private.h>
18 #include <versal_net_def.h>
19
20 uint32_t platform_id, platform_version;
21
22 /*
23 * Table of regions to map using the MMU.
24 * This doesn't include TZRAM as the 'mem_layout' argument passed to
25 * configure_mmu_elx() will give the available subset of that,
26 */
27 const mmap_region_t plat_versal_net_mmap[] = {
28 MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
29 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
30 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
31 MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
32 MAP_REGION_FLAT(IPI_BASE, IPI_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
33 { 0 }
34 };
35
plat_versal_net_get_mmap(void)36 const mmap_region_t *plat_versal_net_get_mmap(void)
37 {
38 return plat_versal_net_mmap;
39 }
40
41 /* For saving cpu clock for certain platform */
42 uint32_t cpu_clock;
43
board_name_decode(void)44 char *board_name_decode(void)
45 {
46 switch (platform_id) {
47 case VERSAL_NET_SPP:
48 return "IPP";
49 case VERSAL_NET_EMU:
50 return "EMU";
51 case VERSAL_NET_SILICON:
52 return "Silicon";
53 case VERSAL_NET_QEMU:
54 return "QEMU";
55 default:
56 return "Unknown";
57 }
58 }
59
board_detection(void)60 void board_detection(void)
61 {
62 uint32_t version;
63
64 version = mmio_read_32(PMC_TAP_VERSION);
65 platform_id = FIELD_GET(PLATFORM_MASK, version);
66 platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version);
67
68 if (platform_id == VERSAL_NET_QEMU_COSIM) {
69 platform_id = VERSAL_NET_QEMU;
70 }
71
72 if ((platform_id == VERSAL_NET_SPP) ||
73 (platform_id == VERSAL_NET_EMU) ||
74 (platform_id == VERSAL_NET_QEMU)) {
75 /*
76 * 9 is diff for
77 * 0 means 0.9 version
78 * 1 means 1.0 version
79 * 2 means 1.1 version
80 * etc,
81 */
82 platform_version += 9U;
83 }
84
85 /* Make sure that console is setup to see this message */
86 VERBOSE("Platform id: %d version: %d.%d\n", platform_id,
87 platform_version / 10U, platform_version % 10U);
88 }
89
versal_net_config_setup(void)90 void versal_net_config_setup(void)
91 {
92 uint32_t val;
93 uintptr_t crl_base, iou_scntrs_base, psx_base;
94
95 crl_base = VERSAL_NET_CRL;
96 iou_scntrs_base = VERSAL_NET_IOU_SCNTRS;
97 psx_base = PSX_CRF;
98
99 /* Reset for system timestamp generator in FPX */
100 mmio_write_32(psx_base + PSX_CRF_RST_TIMESTAMP_OFFSET, 0);
101
102 /* Global timer init - Program time stamp reference clk */
103 val = mmio_read_32(crl_base + VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET);
104 val |= VERSAL_NET_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
105 mmio_write_32(crl_base + VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET, val);
106
107 /* Clear reset of timestamp reg */
108 mmio_write_32(crl_base + VERSAL_NET_CRL_RST_TIMESTAMP_OFFSET, 0);
109
110 /* Program freq register in System counter and enable system counter. */
111 mmio_write_32(iou_scntrs_base + VERSAL_NET_IOU_SCNTRS_BASE_FREQ_OFFSET,
112 cpu_clock);
113 mmio_write_32(iou_scntrs_base + VERSAL_NET_IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET,
114 VERSAL_NET_IOU_SCNTRS_CONTROL_EN);
115
116 generic_delay_timer_init();
117
118 #if (TFA_NO_PM == 0)
119 /* Configure IPI data for versal_net */
120 versal_net_ipi_config_table_init();
121 #endif
122 }
123
plat_get_syscnt_freq2(void)124 uint32_t plat_get_syscnt_freq2(void)
125 {
126 return cpu_clock;
127 }
128