1 /* 2 * Copyright (c) 2015 Brian Swetland 3 * 4 * Use of this source code is governed by a MIT-style 5 * license that can be found in the LICENSE file or at 6 * https://opensource.org/licenses/MIT 7 */ 8 9 #pragma once 10 11 #define USB0_BASE 0x40006000 12 13 #define USB_CMD 0x140 14 #define USB_STS 0x144 15 #define USB_INTR 0x148 16 #define USB_FRINDEX 0x14C 17 #define USB_DEVICEADDR 0x154 18 #define USB_ENDPOINTLISTADDR 0x158 19 #define USB_BURSTSIZE 0x160 20 #define USB_ENDPTNAK 0x178 21 #define USB_ENDPTNAKEN 0x17C 22 #define USB_PORTSC1 0x184 23 #define USB_OTGSC 0x1A4 24 #define USB_MODE 0x1A8 25 #define USB_ENDPTSETUPSTAT 0x1AC 26 #define USB_ENDPTPRIME 0x1B0 27 #define USB_ENDPTFLUSH 0x1B4 28 #define USB_ENDPTSTAT 0x1B8 29 #define USB_ENDPTCOMPLETE 0x1BC 30 #define USB_ENDPTCTRL(n) (0x1C0 + (n) * 4) 31 32 33 #define CMD_RUN (1 << 0) // initiate attach 34 #define CMD_STOP (0 << 0) // detach 35 #define CMD_RST (1 << 1) // reset controller, raz when done 36 #define CMD_SUTW (1 << 13) // SetUp TripWire 37 #define CMD_ATDTW (1 << 14) // Add TD TripWire 38 #define CMD_ITC_0 (0 << 16) // IRQ Threshold Immediate 39 #define CMD_ITC_1 (1 << 16) // 1 microframe 40 #define CMD_ITC_2 (2 << 16) // 2 microframes 41 #define CMD_ITC_8 (8 << 16) // 8 microframes 42 #define CMD_ITC_16 (16 << 16) // 16 microframes 43 #define CMD_ITC_32 (32 << 16) // 32 microframes 44 #define CMD_ITC_64 (64 << 16) // 64 microframes 45 46 #define STS_UI (1 << 0) // USB Interrupt (WtC) 47 #define STS_UEI (1 << 1) // USB Error IRQ (WtC) 48 #define STS_PCI (1 << 2) // Port Change Detect (WtC) 49 #define STS_SEI (1 << 4) // System Error (fatal, reset) 50 #define STS_URI (1 << 6) // USB Reset (WtC) 51 #define STS_SRI (1 << 7) // SOF Received (WtC) 52 #define STS_SLI (1 << 8) // DC Suspend (WtC) 53 #define STS_NAKI (1 << 16) // 1 when EPT NAK bits set 54 55 #define INTR_UE (1 << 0) // USB Interrupt Enable 56 #define INTR_UEE (1 << 1) // USB Error IRQ Enable 57 #define INTR_PCE (1 << 2) // Port Change Detect IRQ Enable 58 #define INTR_SEE (1 << 4) // System Error IRQ Enable 59 #define INTR_URE (1 << 6) // USB Reset IRQ Enable 60 #define INTR_SRE (1 << 7) // SOF Received IRQ Enable 61 #define INTR_SLE (1 << 8) // DC Suspend IRQ Enable 62 #define INTR_NAKE (1 << 16) // NAK IRQ Enable 63 64 #define PORTSC1_CCS (1 << 0) // device is attached 65 #define PORTSC1_PE (1 << 2) // port enable (always 1) 66 #define PORTSC1_PEC (1 << 3) // always 0 67 #define PORTSC1_FPR (1 << 6) // force port resume 68 #define PORTSC1_SUSP (1 << 7) // ro: 1 = port suspended 69 #define PORTSC1_RC (1 << 8) // ro: 1 = port in reset 70 #define PORTSC1_HSP (1 << 9) // ro: 1 = port in high-speed 71 #define PORTSC1_PFSC (1 << 24) // 1 = force full-speed only 72 73 #define OTG_VD (1 << 0) // vbus discharge 74 #define OTG_VC (1 << 1) // vbus charge 75 #define OTG_HAAR (1 << 2) // hardware assist auto-reset 76 #define OTG_OT (1 << 3) // OTG termination 77 #define OTG_DP (1 << 4) // data pulsing 78 #define OTG_IDPU (1 << 5) // ID pull-up 79 #define OTG_HADP (1 << 6) // hardware assist data pulse 80 #define OTG_HABA (1 << 7) // hardware assist B-dis to A-con 81 #define OTG_ID (1 << 8) // 0 = A-device, 1 = B-device 82 #define OTG_AVV (1 << 9) // A-VBUS Valid 83 #define OTG_ASV (1 << 10) // A-Session Valid 84 #define OTG_BSV (1 << 11) // B-Session Valid 85 #define OTG_BSE (1 << 12) // B-Session End 86 #define OTG_MS1T (1 << 13) // 1ms Timer Toggle 87 #define OTG_DPS (1 << 14) // 1 = data pulsing detected 88 #define OTG_IDIS (1 << 16) // irq status bits (r/wc) 89 #define OTG_AVVIS (1 << 17) 90 #define OTG_ASVIS (1 << 18) 91 #define OTG_BSVIS (1 << 19) 92 #define OTG_BSEIS (1 << 20) 93 #define OTG_MS1S (1 << 21) 94 #define OTG_DPIS (1 << 22) 95 #define OTG_IDIE (1 << 24) // irq enable bits (rw) 96 #define OTG_AVVIE (1 << 25) 97 #define OTG_ASVIE (1 << 26) 98 #define OTG_BSVIE (1 << 27) 99 #define OTG_BSEIE (1 << 28) 100 #define OTG_MS1E (1 << 29) 101 #define OTG_DPIE (1 << 30) 102 103 //#define MODE_MASK 3 104 #define MODE_IDLE 0 // write once to enter device/host mode 105 #define MODE_DEVICE 2 // must reset to idle to change mode 106 #define MODE_HOST 3 // nust reset to idle to change mode 107 #define MODE_ES (1 << 2) // select big endian 108 #define MODE_SLOM (1 << 3) // enable setup lockout mode 109 #define MODE_SDIS (1 << 4) // enable stream disable mode 110 111 // bits for ENDPTCTRL(n) 112 #define EPCTRL_RXS (1 << 0) // rx ept stall 113 #define EPCTRL_RX_CTRL (0 << 2) 114 #define EPCTRL_RX_ISOC (1 << 2) 115 #define EPCTRL_RX_BULK (2 << 2) 116 #define EPCTRL_RX_INTR (3 << 2) 117 #define EPCTRL_RXR (1 << 6) // tx data toggle reset 118 #define EPCTRL_RXE (1 << 7) // rx ept enable 119 #define EPCTRL_TXS (1 << 16) // tx ept stall 120 #define EPCTRL_TX_CTRL (0 << 18) 121 #define EPCTRL_TX_ISOC (1 << 18) 122 #define EPCTRL_TX_BULK (2 << 18) 123 #define EPCTRL_TX_INTR (3 << 18) 124 #define EPCTRL_TXR (1 << 22) // tx data toggle reset 125 #define EPCTRL_TXE (1 << 23) // rx ept enable 126 // Do not leave unconfigured endpoints as CTRL when enabling 127 // their sibling, or data PID tracking will be undefined 128 129 // bits for all other ENDPT* registers 130 #define EP0_RX (1 << 0) 131 #define EP1_RX (1 << 1) 132 #define EP2_RX (1 << 2) 133 #define EP3_RX (1 << 3) 134 #define EP4_RX (1 << 4) 135 #define EP5_RX (1 << 5) 136 #define EP0_TX (1 << 16) 137 #define EP1_TX (1 << 17) 138 #define EP2_TX (1 << 18) 139 #define EP3_TX (1 << 19) 140 #define EP4_TX (1 << 20) 141 #define EP5_TX (1 << 21) 142 143 #define EPT_TX(n) (1 << ((n) + 16)) 144 #define EPT_RX(n) (1 << (n)) 145 146 #define DQH_MULT0 (0 << 30) // non-iscoh 147 #define DQH_MULT1 (1 << 30) // 1 txn per td 148 #define DQH_MULT2 (2 << 30) // 2 txn per td 149 #define DQH_MULT3 (3 << 30) // 3 txn per td 150 #define DQH_CFG_ZLT (1 << 29) // disable zero-length terminate 151 #define DQH_CFG_MAXPKT(n) ((n) << 16) // <= 1024 152 #define DQH_CFG_IOS (1 << 15) // IRQ on SETUP 153 154 #define DTD_LEN(n) ((n) << 16) 155 #define DTD_IOC (1 << 15) // interrupt on complete 156 #define DTD_MULT0 (0 << 10) 157 #define DTD_MULT1 (1 << 10) 158 #define DTD_MULT2 (2 << 10) 159 #define DTD_MULT3 (3 << 10) 160 #define DTD_STS_MASK 0xE8 161 #define DTD_ACTIVE 0x80 162 #define DTD_HALTED 0x40 163 #define DTD_BUF_ERR 0x20 164 #define DTD_TXN_ERR 0x08 165 166 typedef struct usb_dtd { 167 u32 next_dtd; 168 u32 config; 169 u32 bptr0; 170 u32 bptr1; 171 u32 bptr2; 172 u32 bptr3; 173 u32 bptr4; 174 struct usb_dtd *next; 175 } usb_dtd_t; 176 177 typedef struct usb_dqh { 178 u32 config; 179 u32 current_dtd; 180 u32 next_dtd; 181 u32 dtd_config; 182 u32 dtd_bptr0; 183 u32 dtd_bptr1; 184 u32 dtd_bptr2; 185 u32 dtd_bptr3; 186 u32 dtd_bptr4; 187 u32 dtd_rsvd0; 188 u32 setup0; 189 u32 setup1; 190 u32 rsvd1; 191 u32 rsvd2; 192 u32 rsvd3; 193 u32 rsvd4; 194 } usb_dqh_t; 195