1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef INTERNAL_CCN512_H 9 #define INTERNAL_CCN512_H 10 11 #include <fwk_macros.h> 12 13 #include <stdint.h> 14 15 /* 16 * CCN5xx miscellaneous node (MN) registers 17 */ 18 typedef struct { 19 FWK_RW uint64_t SECURE_ACCESS; 20 FWK_RW uint64_t ERRINT_STATUS; 21 uint8_t RESERVED0[0x170]; 22 FWK_R uint64_t OLY_RNF_NODEID_LIST; 23 uint8_t RESERVED1[0x8]; 24 FWK_R uint64_t OLY_RNI_NODEID_LIST; 25 uint8_t RESERVED2[0x8]; 26 FWK_R uint64_t OLY_RNIDVM_NODEID_LIST; 27 uint8_t RESERVED3[0x8]; 28 FWK_R uint64_t OLY_HNF_NODEID_LIST; 29 uint8_t RESERVED4[0x8]; 30 FWK_R uint64_t OLY_HNI_NODEID_LIST; 31 uint8_t RESERVED5[0x8]; 32 FWK_R uint64_t OLY_SN_NODEID_LIST; 33 uint8_t RESERVED6[0x8]; 34 FWK_R uint64_t OLY_COMP_LIST_63_0; 35 FWK_R uint64_t OLY_COMP_LIST_127_64; 36 FWK_R uint64_t OLY_COMP_LIST_191_128; 37 FWK_R uint64_t OLY_COMP_LIST_255_192; 38 FWK_R uint64_t DVM_DOMAIN_CTL; 39 uint8_t RESERVED7[0x8]; 40 FWK_W uint64_t DVM_DOMAIN_CTL_SET; 41 uint8_t RESERVED8[0x8]; 42 FWK_W uint64_t DVM_DOMAIN_CTL_CLR; 43 uint8_t RESERVED9[0xD8]; 44 FWK_R uint64_t ERR_SIG_VAL_63_0; 45 FWK_R uint64_t ERR_SIG_VAL_127_64; 46 FWK_R uint64_t ERR_SIG_VAL_191_128; 47 uint8_t RESERVED10[0x8]; 48 FWK_R uint64_t ERR_TYPE_31_0; 49 FWK_R uint64_t ERR_TYPE_63_32; 50 FWK_R uint64_t ERR_TYPE_95_64; 51 uint8_t RESERVED11[0x8]; 52 FWK_R uint64_t ERR_TYPE_159_128; 53 uint8_t RESERVED12[0xC88]; 54 FWK_R uint64_t PERIPH_ID_4_PERIPH_ID_5; 55 FWK_R uint64_t PERIPH_ID_6_PERIPH_ID_7; 56 FWK_R uint64_t PERIPH_ID_0_PERIPH_ID_1; 57 FWK_R uint64_t PERIPH_ID_2_PERIPH_ID_3; 58 FWK_R uint64_t COMPONENT_ID_0_COMPONENT_ID_1; 59 FWK_R uint64_t COMPONENT_ID_2_COMPONENT_ID_3; 60 uint8_t RESERVED13[0xEF00]; 61 FWK_R uint64_t OLY_MN_OLY_ID; 62 uint8_t RESERVED14[0xF8]; 63 } ccn5xx_mn_reg_t; 64 65 /* 66 * CCN5xx crosspoint (XP) registers 67 */ 68 typedef struct { 69 FWK_RW uint64_t XP_ROUTING_CONTROL; 70 FWK_RW uint64_t DEV0_NSM_ROUTING_VECTOR; 71 FWK_RW uint64_t DEV1_NSM_ROUTING_VECTOR; 72 uint8_t RESERVED0[0xF8]; 73 FWK_RW uint64_t DEV0_QOS_CONTROL; 74 FWK_RW uint64_t DEV0_QOS_LAT_TGT; 75 FWK_RW uint64_t DEV0_QOS_LAT_SCALE; 76 FWK_RW uint64_t DEV0_QOS_LAT_RANGE; 77 uint8_t RESERVED1[0xE0]; 78 FWK_RW uint64_t DEV1_QOS_CONTROL; 79 FWK_RW uint64_t DEV1_QOS_LAT_TGT; 80 FWK_RW uint64_t DEV1_QOS_LAT_SCALE; 81 FWK_RW uint64_t DEV1_QOS_LAT_RANGE; 82 uint8_t RESERVED2[0xD0]; 83 FWK_RW uint64_t DT_CONFIG; 84 FWK_RW uint64_t DT_INTERFACE_SEL; 85 FWK_RW uint64_t DT_CMP_VAL0_L; 86 FWK_RW uint64_t DT_CMP_VAL0_H; 87 FWK_RW uint64_t DT_CMP_MASK0_L; 88 FWK_RW uint64_t DT_CMP_MASK0_H; 89 uint8_t RESERVED3[0x20]; 90 FWK_RW uint64_t DT_CMP_VAL1_L; 91 FWK_RW uint64_t DT_CMP_VAL1_H; 92 FWK_RW uint64_t DT_CMP_MASK1_L; 93 FWK_RW uint64_t DT_CMP_MASK1_H; 94 FWK_RW uint64_t DT_CONTROL; 95 FWK_RW uint64_t DT_STATUS; 96 FWK_W uint64_t DT_STATUS_CLR; 97 uint8_t RESERVED4[0x78]; 98 FWK_R uint64_t ERR_SYNDROME_REG0; 99 uint8_t RESERVED5[0x78]; 100 FWK_W uint64_t ERR_SYNDROME_CLR; 101 uint8_t RESERVED6[0x78]; 102 FWK_RW uint64_t AUX_CTL; 103 uint8_t RESERVED7[0xF8]; 104 FWK_RW uint64_t PMU_EVENT_SEL; 105 uint8_t RESERVED8[0xF8F8]; 106 FWK_R uint64_t OLY_XP_OLY_ID; 107 uint8_t RESERVED9[0xF8]; 108 } ccn5xx_xp_reg_t; 109 110 /* 111 * CCN5xx fully coherent home node (HN-F) registers 112 */ 113 typedef struct { 114 FWK_RW uint64_t HNF_CFG_CTRL; 115 FWK_RW uint64_t HNF_SAM_CONTROL; 116 FWK_W uint64_t HN_CFG_PSTATE_REQ; 117 FWK_R uint64_t HN_CFG_PSTATE_STATUS; 118 FWK_R uint64_t QOS_BAND; 119 FWK_RW uint64_t QOS_RESERVATION; 120 FWK_RW uint64_t RN_STARVATION; 121 FWK_RW uint64_t HNF_ERR_INJ; 122 FWK_RW uint64_t HNF_L3_LOCK_WAYS; 123 FWK_RW uint64_t HNF_L3_LOCK_BASE0; 124 FWK_RW uint64_t HNF_L3_LOCK_BASE1; 125 FWK_RW uint64_t HNF_L3_LOCK_BASE2; 126 FWK_RW uint64_t HNF_L3_LOCK_BASE3; 127 uint8_t RESERVED0[0xA0]; 128 FWK_RW uint64_t HN_CFG_RNI_VEC; 129 uint8_t RESERVED1[0xF0]; 130 FWK_R uint64_t SNOOP_DOMAIN_CTL; 131 uint8_t RESERVED2[0x8]; 132 FWK_W uint64_t SNOOP_DOMAIN_CTL_SET; 133 uint8_t RESERVED3[0x8]; 134 FWK_W uint64_t SNOOP_DOMAIN_CTL_CLR; 135 uint8_t RESERVED4[0xD8]; 136 FWK_W uint64_t HN_CFG_L3SF_DBGRD; 137 FWK_R uint64_t L3_CACHE_ACCESS_L3_TAG; 138 FWK_R uint64_t L3_CACHE_ACCESS_L3_DATA; 139 FWK_R uint64_t L3_CACHE_ACCESS_SF_TAG; 140 uint8_t RESERVED5[0xE0]; 141 FWK_R uint64_t ERR_SYNDROME_REG0; 142 FWK_R uint64_t ERR_SYNDROME_REG1; 143 uint8_t RESERVED6[0x70]; 144 FWK_W uint64_t ERR_SYNDROME_CLR; 145 uint8_t RESERVED7[0x78]; 146 FWK_RW uint64_t HNF_AUX_CTL; 147 uint8_t RESERVED8[0xF8]; 148 FWK_RW uint64_t PMU_EVENT_SEL; 149 uint8_t RESERVED9[0xF8F8]; 150 FWK_R uint64_t OLY_HNF_MISC_OLY_ID; 151 uint8_t RESERVED10[0xF8]; 152 } ccn5xx_hnf_reg_t; 153 154 /* 155 * CCN5xx I/O home node (HN-I) registers 156 */ 157 typedef struct { 158 FWK_RW uint64_t POS_CONTROL; 159 FWK_RW uint64_t PCIERC_RNI_NODEID_LIST; 160 uint8_t RESERVED0[0x3F0]; 161 FWK_R uint64_t ERR_SYNDROME_REG0; 162 FWK_R uint64_t ERR_SYNDROME_REG1; 163 uint8_t RESERVED1[0x70]; 164 FWK_W uint64_t ERR_SYNDROME_CLR; 165 uint8_t RESERVED2[0x78]; 166 FWK_RW uint64_t SA_AUX_CTL; 167 uint8_t RESERVED3[0xF9F8]; 168 FWK_R uint64_t OLY_HNI_OLY_ID; 169 uint8_t RESERVED4[0xF8]; 170 } ccn5xx_hni_reg_t; 171 172 /* 173 * CCN5xx debug event module registers 174 */ 175 typedef struct { 176 FWK_RW uint64_t ACTIVE_DSM; 177 FWK_RW uint64_t TRIGGER_CTL; 178 FWK_RW uint64_t TRIGGER_STATUS; 179 FWK_W uint64_t TRIGGER_STATUS_CLR; 180 FWK_RW uint64_t TIMER_VAL; 181 FWK_RW int64_t DT_CTL; 182 uint8_t RESERVED0[0x50]; 183 FWK_RW uint64_t DBG_ID; 184 uint8_t RESERVED1[0x78]; 185 FWK_RW uint64_t PMEVCNT0; 186 FWK_RW uint64_t PMEVCNT1; 187 FWK_RW uint64_t PMEVCNT2; 188 FWK_RW uint64_t PMEVCNT3; 189 FWK_RW uint64_t PMEVCNT4; 190 FWK_RW uint64_t PMEVCNT5; 191 FWK_RW uint64_t PMEVCNT6; 192 FWK_RW uint64_t PMEVCNT7; 193 FWK_RW uint64_t PMCCNTR; 194 uint8_t RESERVED2[0x8]; 195 FWK_RW uint64_t PMEVCNTSR0; 196 FWK_RW uint64_t PMEVCNTSR1; 197 FWK_RW uint64_t PMEVCNTSR2; 198 FWK_RW uint64_t PMEVCNTSR3; 199 FWK_RW uint64_t PMEVCNTSR4; 200 FWK_RW uint64_t PMEVCNTSR5; 201 FWK_RW uint64_t PMEVCNTSR6; 202 FWK_RW uint64_t PMEVCNTSR7; 203 FWK_RW uint64_t PMCCNTRSR; 204 FWK_R uint64_t PMOVSR; 205 FWK_RW uint64_t PMOVSR_CLR; 206 FWK_RW uint64_t PMCR; 207 FWK_R uint64_t PMSR; 208 FWK_W uint64_t PMSR_REQ; 209 FWK_W uint64_t PMSR_CLR; 210 uint8_t RESERVED3[0xFD38]; 211 FWK_R uint64_t OLY_MN_DT_OLY_ID; 212 uint8_t RESERVED4[0xF8]; 213 } ccn5xx_dbg_reg_t; 214 215 /* 216 * CCN5xx I/O coherent requesting node bridge (RN-I) registers 217 */ 218 typedef struct { 219 uint8_t RESERVED0[0x8]; 220 FWK_RW uint64_t S0_PORT_CONTROL; 221 FWK_RW uint64_t S0_QOS_CONTROL; 222 FWK_RW uint64_t S0_QOS_LAT_TGT; 223 FWK_RW uint64_t S0_QOS_LAT_SCALE; 224 FWK_RW uint64_t S0_QOS_LAT_RANGE; 225 uint8_t RESERVED1[0xD8]; 226 FWK_RW uint64_t S1_PORT_CONTROL; 227 FWK_RW uint64_t S1_QOS_CONTROL; 228 FWK_RW uint64_t S1_QOS_LAT_TGT; 229 FWK_RW uint64_t S1_QOS_LAT_SCALE; 230 FWK_RW uint64_t S1_QOS_LAT_RANGE; 231 uint8_t RESERVED2[0xD8]; 232 FWK_RW uint64_t S2_PORT_CONTROL; 233 FWK_RW uint64_t S2_QOS_CONTROL; 234 FWK_RW uint64_t S2_QOS_LAT_TGT; 235 FWK_RW uint64_t S2_QOS_LAT_SCALE; 236 FWK_RW uint64_t S2_QOS_LAT_RANGE; 237 uint8_t RESERVED3[0x2D0]; 238 FWK_RW uint64_t AUX_CTL; 239 uint8_t RESERVED4[0xF8]; 240 FWK_RW uint64_t PMU_EVENT_SEL; 241 uint8_t RESERVED5[0xF8F8]; 242 FWK_R uint64_t OLY_RNI_OLY_ID; 243 uint8_t RESERVED6[0xF8]; 244 } ccn5xx_rni_reg_t; 245 246 /* 247 * CCN5xx CHI to AXI bridge (SBSX) registers 248 */ 249 typedef struct { 250 uint8_t RESERVED0[0x500]; 251 FWK_RW uint64_t SA_AUX_CTL; 252 uint8_t RESERVED1[0xF9F8]; 253 FWK_R uint64_t OLY_SBSX_OLY_ID; 254 uint8_t RESERVED2[0xF8]; 255 } ccn5xx_sbsx_reg_t; 256 257 /* 258 * CCN5xx unused region structure, used as a placeholder 259 */ 260 typedef struct { 261 uint8_t RESERVED0[0xFF00]; 262 FWK_R uint64_t OLY_REGION_OLY_ID; 263 uint8_t RESERVED1[0xF8]; 264 } ccn5xx_region_t; 265 266 #endif /* INTERNAL_CCN512_H */ 267