1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell.
5 *
6 */
7
8 #ifndef RVU_H
9 #define RVU_H
10
11 #include <linux/pci.h>
12 #include <net/devlink.h>
13
14 #include "rvu_struct.h"
15 #include "rvu_devlink.h"
16 #include "common.h"
17 #include "mbox.h"
18 #include "npc.h"
19 #include "rvu_reg.h"
20
21 /* PCI device IDs */
22 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065
23 #define PCI_DEVID_OCTEONTX2_LBK 0xA061
24
25 /* Subsystem Device ID */
26 #define PCI_SUBSYS_DEVID_96XX 0xB200
27 #define PCI_SUBSYS_DEVID_CN10K_A 0xB900
28 #define PCI_SUBSYS_DEVID_CNF10K_B 0xBC00
29 #define PCI_SUBSYS_DEVID_CN10K_B 0xBD00
30
31 /* PCI BAR nos */
32 #define PCI_AF_REG_BAR_NUM 0
33 #define PCI_PF_REG_BAR_NUM 2
34 #define PCI_MBOX_BAR_NUM 4
35
36 #define NAME_SIZE 32
37 #define MAX_NIX_BLKS 2
38 #define MAX_CPT_BLKS 2
39
40 /* PF_FUNC */
41 #define RVU_PFVF_PF_SHIFT 10
42 #define RVU_PFVF_PF_MASK 0x3F
43 #define RVU_PFVF_FUNC_SHIFT 0
44 #define RVU_PFVF_FUNC_MASK 0x3FF
45
46 #ifdef CONFIG_DEBUG_FS
47 struct dump_ctx {
48 int lf;
49 int id;
50 bool all;
51 };
52
53 struct cpt_ctx {
54 int blkaddr;
55 struct rvu *rvu;
56 };
57
58 struct rvu_debugfs {
59 struct dentry *root;
60 struct dentry *cgx_root;
61 struct dentry *cgx;
62 struct dentry *lmac;
63 struct dentry *npa;
64 struct dentry *nix;
65 struct dentry *npc;
66 struct dentry *cpt;
67 struct dentry *mcs_root;
68 struct dentry *mcs;
69 struct dentry *mcs_rx;
70 struct dentry *mcs_tx;
71 struct dump_ctx npa_aura_ctx;
72 struct dump_ctx npa_pool_ctx;
73 struct dump_ctx nix_cq_ctx;
74 struct dump_ctx nix_rq_ctx;
75 struct dump_ctx nix_sq_ctx;
76 struct cpt_ctx cpt_ctx[MAX_CPT_BLKS];
77 int npa_qsize_id;
78 int nix_qsize_id;
79 };
80 #endif
81
82 struct rvu_work {
83 struct work_struct work;
84 struct rvu *rvu;
85 int num_msgs;
86 int up_num_msgs;
87 };
88
89 struct rsrc_bmap {
90 unsigned long *bmap; /* Pointer to resource bitmap */
91 u16 max; /* Max resource id or count */
92 };
93
94 struct rvu_block {
95 struct rsrc_bmap lf;
96 struct admin_queue *aq; /* NIX/NPA AQ */
97 u16 *fn_map; /* LF to pcifunc mapping */
98 bool multislot;
99 bool implemented;
100 u8 addr; /* RVU_BLOCK_ADDR_E */
101 u8 type; /* RVU_BLOCK_TYPE_E */
102 u8 lfshift;
103 u64 lookup_reg;
104 u64 pf_lfcnt_reg;
105 u64 vf_lfcnt_reg;
106 u64 lfcfg_reg;
107 u64 msixcfg_reg;
108 u64 lfreset_reg;
109 unsigned char name[NAME_SIZE];
110 struct rvu *rvu;
111 u64 cpt_flt_eng_map[3];
112 u64 cpt_rcvrd_eng_map[3];
113 };
114
115 struct nix_mcast {
116 struct qmem *mce_ctx;
117 struct qmem *mcast_buf;
118 int replay_pkind;
119 int next_free_mce;
120 struct mutex mce_lock; /* Serialize MCE updates */
121 };
122
123 struct nix_mce_list {
124 struct hlist_head head;
125 int count;
126 int max;
127 };
128
129 /* layer metadata to uniquely identify a packet header field */
130 struct npc_layer_mdata {
131 u8 lid;
132 u8 ltype;
133 u8 hdr;
134 u8 key;
135 u8 len;
136 };
137
138 /* Structure to represent a field present in the
139 * generated key. A key field may present anywhere and can
140 * be of any size in the generated key. Once this structure
141 * is populated for fields of interest then field's presence
142 * and location (if present) can be known.
143 */
144 struct npc_key_field {
145 /* Masks where all set bits indicate position
146 * of a field in the key
147 */
148 u64 kw_mask[NPC_MAX_KWS_IN_KEY];
149 /* Number of words in the key a field spans. If a field is
150 * of 16 bytes and key offset is 4 then the field will use
151 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and
152 * nr_kws will be 3(KW0, KW1 and KW2).
153 */
154 int nr_kws;
155 /* used by packet header fields */
156 struct npc_layer_mdata layer_mdata;
157 };
158
159 struct npc_mcam {
160 struct rsrc_bmap counters;
161 struct mutex lock; /* MCAM entries and counters update lock */
162 unsigned long *bmap; /* bitmap, 0 => bmap_entries */
163 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */
164 u16 bmap_entries; /* Number of unreserved MCAM entries */
165 u16 bmap_fcnt; /* MCAM entries free count */
166 u16 *entry2pfvf_map;
167 u16 *entry2cntr_map;
168 u16 *cntr2pfvf_map;
169 u16 *cntr_refcnt;
170 u16 *entry2target_pffunc;
171 u8 keysize; /* MCAM keysize 112/224/448 bits */
172 u8 banks; /* Number of MCAM banks */
173 u8 banks_per_entry;/* Number of keywords in key */
174 u16 banksize; /* Number of MCAM entries in each bank */
175 u16 total_entries; /* Total number of MCAM entries */
176 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */
177 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */
178 u16 lprio_count;
179 u16 lprio_start;
180 u16 hprio_count;
181 u16 hprio_end;
182 u16 rx_miss_act_cntr; /* Counter for RX MISS action */
183 /* fields present in the generated key */
184 struct npc_key_field tx_key_fields[NPC_KEY_FIELDS_MAX];
185 struct npc_key_field rx_key_fields[NPC_KEY_FIELDS_MAX];
186 u64 tx_features;
187 u64 rx_features;
188 struct list_head mcam_rules;
189 };
190
191 /* Structure for per RVU func info ie PF/VF */
192 struct rvu_pfvf {
193 bool npalf; /* Only one NPALF per RVU_FUNC */
194 bool nixlf; /* Only one NIXLF per RVU_FUNC */
195 u16 sso;
196 u16 ssow;
197 u16 cptlfs;
198 u16 timlfs;
199 u16 cpt1_lfs;
200 u8 cgx_lmac;
201
202 /* Block LF's MSIX vector info */
203 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */
204 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF))
205 u16 *msix_lfmap; /* Vector to block LF mapping */
206
207 /* NPA contexts */
208 struct qmem *aura_ctx;
209 struct qmem *pool_ctx;
210 struct qmem *npa_qints_ctx;
211 unsigned long *aura_bmap;
212 unsigned long *pool_bmap;
213
214 /* NIX contexts */
215 struct qmem *rq_ctx;
216 struct qmem *sq_ctx;
217 struct qmem *cq_ctx;
218 struct qmem *rss_ctx;
219 struct qmem *cq_ints_ctx;
220 struct qmem *nix_qints_ctx;
221 unsigned long *sq_bmap;
222 unsigned long *rq_bmap;
223 unsigned long *cq_bmap;
224
225 u16 rx_chan_base;
226 u16 tx_chan_base;
227 u8 rx_chan_cnt; /* total number of RX channels */
228 u8 tx_chan_cnt; /* total number of TX channels */
229 u16 maxlen;
230 u16 minlen;
231
232 bool hw_rx_tstamp_en; /* Is rx_tstamp enabled */
233 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */
234 u8 default_mac[ETH_ALEN]; /* MAC address from FWdata */
235
236 /* Broadcast/Multicast/Promisc pkt replication info */
237 u16 bcast_mce_idx;
238 u16 mcast_mce_idx;
239 u16 promisc_mce_idx;
240 struct nix_mce_list bcast_mce_list;
241 struct nix_mce_list mcast_mce_list;
242 struct nix_mce_list promisc_mce_list;
243 bool use_mce_list;
244
245 struct rvu_npc_mcam_rule *def_ucast_rule;
246
247 bool cgx_in_use; /* this PF/VF using CGX? */
248 int cgx_users; /* number of cgx users - used only by PFs */
249
250 int intf_mode;
251 u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */
252 u8 nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */
253 u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */
254 u8 lbkid; /* NIX0/1 lbk link ID */
255 u64 lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/
256 u64 lmt_map_ent_w1; /* Preseving the word1 of lmtst map table entry*/
257 unsigned long flags;
258 struct sdp_node_info *sdp_info;
259 };
260
261 enum rvu_pfvf_flags {
262 NIXLF_INITIALIZED = 0,
263 PF_SET_VF_MAC,
264 PF_SET_VF_CFG,
265 PF_SET_VF_TRUSTED,
266 };
267
268 #define RVU_CLEAR_VF_PERM ~GENMASK(PF_SET_VF_TRUSTED, PF_SET_VF_MAC)
269
270 struct nix_txsch {
271 struct rsrc_bmap schq;
272 u8 lvl;
273 #define NIX_TXSCHQ_FREE BIT_ULL(1)
274 #define NIX_TXSCHQ_CFG_DONE BIT_ULL(0)
275 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF)
276 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16)
277 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16))
278 #define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16))
279 u32 *pfvf_map;
280 };
281
282 struct nix_mark_format {
283 u8 total;
284 u8 in_use;
285 u32 *cfg;
286 };
287
288 struct npc_pkind {
289 struct rsrc_bmap rsrc;
290 u32 *pfchan_map;
291 };
292
293 struct nix_flowkey {
294 #define NIX_FLOW_KEY_ALG_MAX 32
295 u32 flowkey[NIX_FLOW_KEY_ALG_MAX];
296 int in_use;
297 };
298
299 struct nix_lso {
300 u8 total;
301 u8 in_use;
302 };
303
304 struct nix_txvlan {
305 #define NIX_TX_VTAG_DEF_MAX 0x400
306 struct rsrc_bmap rsrc;
307 u16 *entry2pfvf_map;
308 struct mutex rsrc_lock; /* Serialize resource alloc/free */
309 };
310
311 struct nix_ipolicer {
312 struct rsrc_bmap band_prof;
313 u16 *pfvf_map;
314 u16 *match_id;
315 u16 *ref_count;
316 };
317
318 struct nix_hw {
319 int blkaddr;
320 struct rvu *rvu;
321 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */
322 struct nix_mcast mcast;
323 struct nix_flowkey flowkey;
324 struct nix_mark_format mark_format;
325 struct nix_lso lso;
326 struct nix_txvlan txvlan;
327 struct nix_ipolicer *ipolicer;
328 u64 *tx_credits;
329 };
330
331 /* RVU block's capabilities or functionality,
332 * which vary by silicon version/skew.
333 */
334 struct hw_cap {
335 /* Transmit side supported functionality */
336 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */
337 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */
338 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */
339 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */
340 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
341 bool nix_shaping; /* Is shaping and coloring supported */
342 bool nix_shaper_toggle_wait; /* Shaping toggle needs poll/wait */
343 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */
344 bool nix_rx_multicast; /* Rx packet replication support */
345 bool nix_common_dwrr_mtu; /* Common DWRR MTU for quantum config */
346 bool per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */
347 bool programmable_chans; /* Channels programmable ? */
348 bool ipolicer;
349 bool npc_hash_extract; /* Hash extract enabled ? */
350 bool npc_exact_match_enabled; /* Exact match supported ? */
351 };
352
353 struct rvu_hwinfo {
354 u8 total_pfs; /* MAX RVU PFs HW supports */
355 u16 total_vfs; /* Max RVU VFs HW supports */
356 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */
357 u8 cgx;
358 u8 lmac_per_cgx;
359 u16 cgx_chan_base; /* CGX base channel number */
360 u16 lbk_chan_base; /* LBK base channel number */
361 u16 sdp_chan_base; /* SDP base channel number */
362 u16 cpt_chan_base; /* CPT base channel number */
363 u8 cgx_links;
364 u8 lbk_links;
365 u8 sdp_links;
366 u8 cpt_links; /* Number of CPT links */
367 u8 npc_kpus; /* No of parser units */
368 u8 npc_pkinds; /* No of port kinds */
369 u8 npc_intfs; /* No of interfaces */
370 u8 npc_kpu_entries; /* No of KPU entries */
371 u16 npc_counters; /* No of match stats counters */
372 u32 lbk_bufsize; /* FIFO size supported by LBK */
373 bool npc_ext_set; /* Extended register set */
374 u64 npc_stat_ena; /* Match stats enable bit */
375
376 struct hw_cap cap;
377 struct rvu_block block[BLK_COUNT]; /* Block info */
378 struct nix_hw *nix;
379 struct rvu *rvu;
380 struct npc_pkind pkind;
381 struct npc_mcam mcam;
382 struct npc_exact_table *table;
383 };
384
385 struct mbox_wq_info {
386 struct otx2_mbox mbox;
387 struct rvu_work *mbox_wrk;
388
389 struct otx2_mbox mbox_up;
390 struct rvu_work *mbox_wrk_up;
391
392 struct workqueue_struct *mbox_wq;
393 };
394
395 struct rvu_fwdata {
396 #define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/
397 #define RVU_FWDATA_VERSION 0x0001
398 u32 header_magic;
399 u32 version; /* version id */
400
401 /* MAC address */
402 #define PF_MACNUM_MAX 32
403 #define VF_MACNUM_MAX 256
404 u64 pf_macs[PF_MACNUM_MAX];
405 u64 vf_macs[VF_MACNUM_MAX];
406 u64 sclk;
407 u64 rclk;
408 u64 mcam_addr;
409 u64 mcam_sz;
410 u64 msixtr_base;
411 u32 ptp_ext_clk_rate;
412 u32 ptp_ext_tstamp;
413 #define FWDATA_RESERVED_MEM 1022
414 u64 reserved[FWDATA_RESERVED_MEM];
415 #define CGX_MAX 9
416 #define CGX_LMACS_MAX 4
417 #define CGX_LMACS_USX 8
418 union {
419 struct cgx_lmac_fwdata_s
420 cgx_fw_data[CGX_MAX][CGX_LMACS_MAX];
421 struct cgx_lmac_fwdata_s
422 cgx_fw_data_usx[CGX_MAX][CGX_LMACS_USX];
423 };
424 /* Do not add new fields below this line */
425 };
426
427 struct ptp;
428
429 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the
430 * source where it came from.
431 */
432 struct npc_kpu_profile_adapter {
433 const char *name;
434 u64 version;
435 const struct npc_lt_def_cfg *lt_def;
436 const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */
437 const struct npc_kpu_profile *kpu; /* array[kpus] */
438 struct npc_mcam_kex *mkex;
439 struct npc_mcam_kex_hash *mkex_hash;
440 bool custom;
441 size_t pkinds;
442 size_t kpus;
443 };
444
445 #define RVU_SWITCH_LBK_CHAN 63
446
447 struct rvu_switch {
448 struct mutex switch_lock; /* Serialize flow installation */
449 u32 used_entries;
450 u16 *entry2pcifunc;
451 u16 mode;
452 u16 start_entry;
453 };
454
455 struct rvu {
456 void __iomem *afreg_base;
457 void __iomem *pfreg_base;
458 struct pci_dev *pdev;
459 struct device *dev;
460 struct rvu_hwinfo *hw;
461 struct rvu_pfvf *pf;
462 struct rvu_pfvf *hwvf;
463 struct mutex rsrc_lock; /* Serialize resource alloc/free */
464 struct mutex alias_lock; /* Serialize bar2 alias access */
465 int vfs; /* Number of VFs attached to RVU */
466 int nix_blkaddr[MAX_NIX_BLKS];
467
468 /* Mbox */
469 struct mbox_wq_info afpf_wq_info;
470 struct mbox_wq_info afvf_wq_info;
471
472 /* PF FLR */
473 struct rvu_work *flr_wrk;
474 struct workqueue_struct *flr_wq;
475 struct mutex flr_lock; /* Serialize FLRs */
476
477 /* MSI-X */
478 u16 num_vec;
479 char *irq_name;
480 bool *irq_allocated;
481 dma_addr_t msix_base_iova;
482 u64 msixtr_base_phy; /* Register reset value */
483
484 /* CGX */
485 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */
486 u16 cgx_mapped_vfs; /* maximum CGX mapped VFs */
487 u8 cgx_mapped_pfs;
488 u8 cgx_cnt_max; /* CGX port count max */
489 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */
490 u64 *cgxlmac2pf_map; /* bitmap of mapped pfs for
491 * every cgx lmac port
492 */
493 unsigned long pf_notify_bmap; /* Flags for PF notification */
494 void **cgx_idmap; /* cgx id to cgx data map table */
495 struct work_struct cgx_evh_work;
496 struct workqueue_struct *cgx_evh_wq;
497 spinlock_t cgx_evq_lock; /* cgx event queue lock */
498 struct list_head cgx_evq_head; /* cgx event queue head */
499 struct mutex cgx_cfg_lock; /* serialize cgx configuration */
500
501 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */
502 char kpu_pfl_name[KPU_NAME_LEN]; /* Configured KPU profile name */
503
504 /* Firmware data */
505 struct rvu_fwdata *fwdata;
506 void *kpu_fwdata;
507 size_t kpu_fwdata_sz;
508 void __iomem *kpu_prfl_addr;
509
510 /* NPC KPU data */
511 struct npc_kpu_profile_adapter kpu;
512
513 struct ptp *ptp;
514
515 int mcs_blk_cnt;
516 int cpt_pf_num;
517
518 #ifdef CONFIG_DEBUG_FS
519 struct rvu_debugfs rvu_dbg;
520 #endif
521 struct rvu_devlink *rvu_dl;
522
523 /* RVU switch implementation over NPC with DMAC rules */
524 struct rvu_switch rswitch;
525
526 struct work_struct mcs_intr_work;
527 struct workqueue_struct *mcs_intr_wq;
528 struct list_head mcs_intrq_head;
529 /* mcs interrupt queue lock */
530 spinlock_t mcs_intrq_lock;
531 /* CPT interrupt lock */
532 spinlock_t cpt_intr_lock;
533 };
534
rvu_write64(struct rvu * rvu,u64 block,u64 offset,u64 val)535 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
536 {
537 writeq(val, rvu->afreg_base + ((block << 28) | offset));
538 }
539
rvu_read64(struct rvu * rvu,u64 block,u64 offset)540 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset)
541 {
542 return readq(rvu->afreg_base + ((block << 28) | offset));
543 }
544
rvupf_write64(struct rvu * rvu,u64 offset,u64 val)545 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val)
546 {
547 writeq(val, rvu->pfreg_base + offset);
548 }
549
rvupf_read64(struct rvu * rvu,u64 offset)550 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset)
551 {
552 return readq(rvu->pfreg_base + offset);
553 }
554
rvu_bar2_sel_write64(struct rvu * rvu,u64 block,u64 offset,u64 val)555 static inline void rvu_bar2_sel_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
556 {
557 /* HW requires read back of RVU_AF_BAR2_SEL register to make sure completion of
558 * write operation.
559 */
560 rvu_write64(rvu, block, offset, val);
561 rvu_read64(rvu, block, offset);
562 /* Barrier to ensure read completes before accessing LF registers */
563 mb();
564 }
565
566 /* Silicon revisions */
is_rvu_pre_96xx_C0(struct rvu * rvu)567 static inline bool is_rvu_pre_96xx_C0(struct rvu *rvu)
568 {
569 struct pci_dev *pdev = rvu->pdev;
570 /* 96XX A0/B0, 95XX A0/A1/B0 chips */
571 return ((pdev->revision == 0x00) || (pdev->revision == 0x01) ||
572 (pdev->revision == 0x10) || (pdev->revision == 0x11) ||
573 (pdev->revision == 0x14));
574 }
575
is_rvu_96xx_A0(struct rvu * rvu)576 static inline bool is_rvu_96xx_A0(struct rvu *rvu)
577 {
578 struct pci_dev *pdev = rvu->pdev;
579
580 return (pdev->revision == 0x00);
581 }
582
is_rvu_96xx_B0(struct rvu * rvu)583 static inline bool is_rvu_96xx_B0(struct rvu *rvu)
584 {
585 struct pci_dev *pdev = rvu->pdev;
586
587 return (pdev->revision == 0x00) || (pdev->revision == 0x01);
588 }
589
is_rvu_95xx_A0(struct rvu * rvu)590 static inline bool is_rvu_95xx_A0(struct rvu *rvu)
591 {
592 struct pci_dev *pdev = rvu->pdev;
593
594 return (pdev->revision == 0x10) || (pdev->revision == 0x11);
595 }
596
597 /* REVID for PCIe devices.
598 * Bits 0..1: minor pass, bit 3..2: major pass
599 * bits 7..4: midr id
600 */
601 #define PCI_REVISION_ID_96XX 0x00
602 #define PCI_REVISION_ID_95XX 0x10
603 #define PCI_REVISION_ID_95XXN 0x20
604 #define PCI_REVISION_ID_98XX 0x30
605 #define PCI_REVISION_ID_95XXMM 0x40
606 #define PCI_REVISION_ID_95XXO 0xE0
607
is_rvu_otx2(struct rvu * rvu)608 static inline bool is_rvu_otx2(struct rvu *rvu)
609 {
610 struct pci_dev *pdev = rvu->pdev;
611
612 u8 midr = pdev->revision & 0xF0;
613
614 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX ||
615 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX ||
616 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO);
617 }
618
is_rvu_npc_hash_extract_en(struct rvu * rvu)619 static inline bool is_rvu_npc_hash_extract_en(struct rvu *rvu)
620 {
621 u64 npc_const3;
622
623 npc_const3 = rvu_read64(rvu, BLKADDR_NPC, NPC_AF_CONST3);
624 if (!(npc_const3 & BIT_ULL(62)))
625 return false;
626
627 return true;
628 }
629
rvu_nix_chan_cgx(struct rvu * rvu,u8 cgxid,u8 lmacid,u8 chan)630 static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid,
631 u8 lmacid, u8 chan)
632 {
633 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST);
634 u16 cgx_chans = nix_const & 0xFFULL;
635 struct rvu_hwinfo *hw = rvu->hw;
636
637 if (!hw->cap.programmable_chans)
638 return NIX_CHAN_CGX_LMAC_CHX(cgxid, lmacid, chan);
639
640 return rvu->hw->cgx_chan_base +
641 (cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan;
642 }
643
rvu_nix_chan_lbk(struct rvu * rvu,u8 lbkid,u8 chan)644 static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid,
645 u8 chan)
646 {
647 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST);
648 u16 lbk_chans = (nix_const >> 16) & 0xFFULL;
649 struct rvu_hwinfo *hw = rvu->hw;
650
651 if (!hw->cap.programmable_chans)
652 return NIX_CHAN_LBK_CHX(lbkid, chan);
653
654 return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan;
655 }
656
rvu_nix_chan_sdp(struct rvu * rvu,u8 chan)657 static inline u16 rvu_nix_chan_sdp(struct rvu *rvu, u8 chan)
658 {
659 struct rvu_hwinfo *hw = rvu->hw;
660
661 if (!hw->cap.programmable_chans)
662 return NIX_CHAN_SDP_CHX(chan);
663
664 return hw->sdp_chan_base + chan;
665 }
666
rvu_nix_chan_cpt(struct rvu * rvu,u8 chan)667 static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan)
668 {
669 return rvu->hw->cpt_chan_base + chan;
670 }
671
672 /* Function Prototypes
673 * RVU
674 */
is_afvf(u16 pcifunc)675 static inline bool is_afvf(u16 pcifunc)
676 {
677 return !(pcifunc & ~RVU_PFVF_FUNC_MASK);
678 }
679
is_vf(u16 pcifunc)680 static inline bool is_vf(u16 pcifunc)
681 {
682 return !!(pcifunc & RVU_PFVF_FUNC_MASK);
683 }
684
685 /* check if PF_FUNC is AF */
is_pffunc_af(u16 pcifunc)686 static inline bool is_pffunc_af(u16 pcifunc)
687 {
688 return !pcifunc;
689 }
690
is_rvu_fwdata_valid(struct rvu * rvu)691 static inline bool is_rvu_fwdata_valid(struct rvu *rvu)
692 {
693 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) &&
694 (rvu->fwdata->version == RVU_FWDATA_VERSION);
695 }
696
697 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc);
698 void rvu_free_bitmap(struct rsrc_bmap *rsrc);
699 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc);
700 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id);
701 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id);
702 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc);
703 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc);
704 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc);
705 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr);
706 int rvu_get_pf(u16 pcifunc);
707 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc);
708 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf);
709 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr);
710 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype);
711 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot);
712 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf);
713 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc);
714 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero);
715 int rvu_get_num_lbk_chans(void);
716 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc,
717 u16 global_slot, u16 *slot_in_block);
718
719 /* RVU HW reg validation */
720 enum regmap_block {
721 TXSCHQ_HWREGMAP = 0,
722 MAX_HWREGMAP,
723 };
724
725 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg);
726
727 /* NPA/NIX AQ APIs */
728 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
729 int qsize, int inst_size, int res_size);
730 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq);
731
732 /* SDP APIs */
733 int rvu_sdp_init(struct rvu *rvu);
734 bool is_sdp_pfvf(u16 pcifunc);
735 bool is_sdp_pf(u16 pcifunc);
736 bool is_sdp_vf(u16 pcifunc);
737
738 /* CGX APIs */
is_pf_cgxmapped(struct rvu * rvu,u8 pf)739 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf)
740 {
741 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs) &&
742 !is_sdp_pf(pf << RVU_PFVF_PF_SHIFT);
743 }
744
rvu_get_cgx_lmac_id(u8 map,u8 * cgx_id,u8 * lmac_id)745 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id)
746 {
747 *cgx_id = (map >> 4) & 0xF;
748 *lmac_id = (map & 0xF);
749 }
750
is_cgx_vf(struct rvu * rvu,u16 pcifunc)751 static inline bool is_cgx_vf(struct rvu *rvu, u16 pcifunc)
752 {
753 return ((pcifunc & RVU_PFVF_FUNC_MASK) &&
754 is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc)));
755 }
756
757 #define M(_name, _id, fn_name, req, rsp) \
758 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *);
759 MBOX_MESSAGES
760 #undef M
761
762 int rvu_cgx_init(struct rvu *rvu);
763 int rvu_cgx_exit(struct rvu *rvu);
764 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu);
765 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start);
766 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable);
767 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start);
768 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index,
769 int rxtxflag, u64 *stat);
770 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc);
771
772 /* NPA APIs */
773 int rvu_npa_init(struct rvu *rvu);
774 void rvu_npa_freemem(struct rvu *rvu);
775 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf);
776 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req,
777 struct npa_aq_enq_rsp *rsp);
778
779 /* NIX APIs */
780 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc);
781 int rvu_nix_init(struct rvu *rvu);
782 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw,
783 int blkaddr, u32 cfg);
784 void rvu_nix_freemem(struct rvu *rvu);
785 int rvu_get_nixlf_count(struct rvu *rvu);
786 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf);
787 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr);
788 int nix_update_mce_list(struct rvu *rvu, u16 pcifunc,
789 struct nix_mce_list *mce_list,
790 int mce_idx, int mcam_index, bool add);
791 void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type,
792 struct nix_mce_list **mce_list, int *mce_idx);
793 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr);
794 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr);
795 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc);
796 int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc,
797 struct nix_hw **nix_hw, int *blkaddr);
798 int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc,
799 u16 rq_idx, u16 match_id);
800 int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw,
801 struct nix_cn10k_aq_enq_req *aq_req,
802 struct nix_cn10k_aq_enq_rsp *aq_rsp,
803 u16 pcifunc, u8 ctype, u32 qidx);
804 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc);
805 u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu);
806 u32 convert_bytes_to_dwrr_mtu(u32 bytes);
807
808 /* NPC APIs */
809 void rvu_npc_freemem(struct rvu *rvu);
810 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf);
811 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf);
812 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en);
813 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
814 int nixlf, u64 chan, u8 *mac_addr);
815 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
816 int nixlf, u64 chan, u8 chan_cnt);
817 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
818 bool enable);
819 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
820 int nixlf, u64 chan);
821 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
822 bool enable);
823 void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
824 u64 chan);
825 void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
826 bool enable);
827
828 void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc,
829 int nixlf, int type, bool enable);
830 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
831 bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable);
832 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
833 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
834 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
835 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
836 int group, int alg_idx, int mcam_index);
837
838 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc,
839 int blkaddr, int *alloc_cnt,
840 int *enable_cnt);
841 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc,
842 int blkaddr, int *alloc_cnt,
843 int *enable_cnt);
844 bool is_npc_intf_tx(u8 intf);
845 bool is_npc_intf_rx(u8 intf);
846 bool is_npc_interface_valid(struct rvu *rvu, u8 intf);
847 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena);
848 int npc_flow_steering_init(struct rvu *rvu, int blkaddr);
849 const char *npc_get_field_name(u8 hdr);
850 int npc_get_bank(struct npc_mcam *mcam, int index);
851 void npc_mcam_enable_flows(struct rvu *rvu, u16 target);
852 void npc_mcam_disable_flows(struct rvu *rvu, u16 target);
853 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
854 int blkaddr, int index, bool enable);
855 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
856 int blkaddr, u16 src, struct mcam_entry *entry,
857 u8 *intf, u8 *ena);
858 bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc);
859 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature);
860 u32 rvu_cgx_get_fifolen(struct rvu *rvu);
861 void *rvu_first_cgx_pdata(struct rvu *rvu);
862 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id);
863 int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable);
864 int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause,
865 u16 pfc_en);
866 int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause);
867 u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac);
868 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, u16 pcifunc, int nixlf,
869 int type);
870 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr,
871 int index);
872 int rvu_npc_init(struct rvu *rvu);
873 int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx,
874 u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask,
875 u64 bcast_mcast_val, u64 bcast_mcast_mask);
876 void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx);
877 bool npc_is_feature_supported(struct rvu *rvu, u64 features, u8 intf);
878
879 /* CPT APIs */
880 int rvu_cpt_register_interrupts(struct rvu *rvu);
881 void rvu_cpt_unregister_interrupts(struct rvu *rvu);
882 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf,
883 int slot);
884 int rvu_cpt_ctx_flush(struct rvu *rvu, u16 pcifunc);
885 int rvu_cpt_init(struct rvu *rvu);
886
887 #define NDC_AF_BANK_MASK GENMASK_ULL(7, 0)
888 #define NDC_AF_BANK_LINE_MASK GENMASK_ULL(31, 16)
889
890 /* CN10K RVU */
891 int rvu_set_channels_base(struct rvu *rvu);
892 void rvu_program_channels(struct rvu *rvu);
893
894 /* CN10K NIX */
895 void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw);
896
897 /* CN10K RVU - LMT*/
898 void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc);
899
900 #ifdef CONFIG_DEBUG_FS
901 void rvu_dbg_init(struct rvu *rvu);
902 void rvu_dbg_exit(struct rvu *rvu);
903 #else
rvu_dbg_init(struct rvu * rvu)904 static inline void rvu_dbg_init(struct rvu *rvu) {}
rvu_dbg_exit(struct rvu * rvu)905 static inline void rvu_dbg_exit(struct rvu *rvu) {}
906 #endif
907
908 int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr);
909
910 /* RVU Switch */
911 void rvu_switch_enable(struct rvu *rvu);
912 void rvu_switch_disable(struct rvu *rvu);
913 void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc);
914
915 int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir,
916 u64 pkind, u8 var_len_off, u8 var_len_off_mask,
917 u8 shift_dir);
918 int rvu_get_hwvf(struct rvu *rvu, int pcifunc);
919
920 /* CN10K MCS */
921 int rvu_mcs_init(struct rvu *rvu);
922 int rvu_mcs_flr_handler(struct rvu *rvu, u16 pcifunc);
923 void rvu_mcs_exit(struct rvu *rvu);
924
925 #endif /* RVU_H */
926