1 /*
2 * AMD Family 10h mmconfig enablement (taken from Linux 2.6.36)
3 */
4
5 #include <xen/lib.h>
6 #include <xen/acpi.h>
7 #include <xen/pci.h>
8 #include <xen/pci_regs.h>
9 #include <xen/pci_ids.h>
10 #include <xen/init.h>
11 #include <xen/dmi.h>
12 #include <asm/amd.h>
13 #include <asm/e820.h>
14 #include <asm/msr.h>
15 #include <asm/processor.h>
16
17 #include "mmconfig.h"
18
19 struct pci_hostbridge_probe {
20 u32 bus;
21 u32 slot;
22 u32 vendor;
23 u32 device;
24 };
25
26 static u64 fam10h_pci_mmconf_base;
27
28 static struct pci_hostbridge_probe pci_probes[] = {
29 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
30 { 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
31 };
32
33 #define UNIT (1ULL << FAM10H_MMIO_CONF_BASE_SHIFT)
34 #define MASK (~(UNIT - 1))
35 #define SIZE (UNIT << 8)
36 /* need to avoid (0xfd<<32) and (0xfe<<32), ht used space */
37 #define FAM10H_PCI_MMCONF_BASE (0xfcULL<<32)
38 #define BASE_VALID(b) ((b) + SIZE <= (0xfdULL<<32) || (b) >= (1ULL<<40))
get_fam10h_pci_mmconf_base(void)39 static void __init get_fam10h_pci_mmconf_base(void)
40 {
41 unsigned int i, j, bus, slot, hi_mmio_num;
42 u32 address;
43 u64 val, tom2, start, end;
44 struct range {
45 u64 start, end;
46 } range[8];
47
48 for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
49 u32 id;
50 u16 device;
51 u16 vendor;
52
53 bus = pci_probes[i].bus;
54 slot = pci_probes[i].slot;
55 id = pci_conf_read32(0, bus, slot, 0, PCI_VENDOR_ID);
56
57 vendor = id & 0xffff;
58 device = (id>>16) & 0xffff;
59 if (pci_probes[i].vendor == vendor &&
60 pci_probes[i].device == device)
61 break;
62 }
63
64 if (i >= ARRAY_SIZE(pci_probes))
65 return;
66
67 /* SYS_CFG */
68 address = MSR_K8_SYSCFG;
69 rdmsrl(address, val);
70
71 /* TOP_MEM2 is not enabled? */
72 if (!(val & (1<<21))) {
73 tom2 = 1ULL << 32;
74 } else {
75 /* TOP_MEM2 */
76 address = MSR_K8_TOP_MEM2;
77 rdmsrl(address, val);
78 tom2 = max(val & 0xffffff800000ULL, 1ULL << 32);
79 }
80
81 /*
82 * need to check if the range is in the high mmio range that is
83 * above 4G
84 */
85 for (hi_mmio_num = i = 0; i < 8; i++) {
86 val = pci_conf_read32(0, bus, slot, 1, 0x80 + (i << 3));
87 if (!(val & 3))
88 continue;
89
90 start = (val & 0xffffff00) << 8; /* 39:16 on 31:8*/
91 val = pci_conf_read32(0, bus, slot, 1, 0x84 + (i << 3));
92 end = ((val & 0xffffff00) << 8) | 0xffff; /* 39:16 on 31:8*/
93
94 if (end < tom2)
95 continue;
96
97 for (j = hi_mmio_num; j; --j) {
98 if (range[j - 1].start < start)
99 break;
100 range[j] = range[j - 1];
101 }
102 range[j].start = start;
103 range[j].end = end;
104 hi_mmio_num++;
105 }
106
107 start = FAM10H_PCI_MMCONF_BASE;
108 if (start <= tom2)
109 start = (tom2 + 2 * UNIT - 1) & MASK;
110
111 if (!hi_mmio_num)
112 goto out;
113
114 if (range[hi_mmio_num - 1].end < start)
115 goto out;
116 if (range[0].start > start + SIZE)
117 goto out;
118
119 /* need to find one window */
120 start = (range[0].start & MASK) - UNIT;
121 if (start > tom2 && BASE_VALID(start))
122 goto out;
123 start = (range[hi_mmio_num - 1].end + UNIT) & MASK;
124 if (BASE_VALID(start))
125 goto out;
126 /* need to find window between ranges */
127 for (i = 1; i < hi_mmio_num; i++) {
128 start = (range[i - 1].end + UNIT) & MASK;
129 end = range[i].start & MASK;
130 if (end >= start + SIZE && BASE_VALID(start))
131 goto out;
132 }
133 return;
134
135 out:
136 if (e820_add_range(&e820, start, start + SIZE, E820_RESERVED))
137 fam10h_pci_mmconf_base = start;
138 }
139
fam10h_check_enable_mmcfg(void)140 void fam10h_check_enable_mmcfg(void)
141 {
142 u64 val;
143 bool_t print = opt_cpu_info;
144
145 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
146 return;
147
148 rdmsrl(MSR_FAM10H_MMIO_CONF_BASE, val);
149
150 /* try to make sure that AP's setting is identical to BSP setting */
151 if (val & FAM10H_MMIO_CONF_ENABLE) {
152 u64 base = val & MASK;
153
154 if (!fam10h_pci_mmconf_base) {
155 fam10h_pci_mmconf_base = base;
156 return;
157 }
158 if (fam10h_pci_mmconf_base == base)
159 return;
160 }
161
162 /*
163 * if it is not enabled, try to enable it and assume only one segment
164 * with 256 buses
165 */
166 /* only try to get setting from BSP */
167 if (!fam10h_pci_mmconf_base) {
168 get_fam10h_pci_mmconf_base();
169 print = 1;
170 }
171 if (!fam10h_pci_mmconf_base) {
172 pci_probe &= ~PCI_CHECK_ENABLE_AMD_MMCONF;
173 return;
174 }
175
176 if (print)
177 printk(KERN_INFO "Enable MMCONFIG on AMD Fam10h at %"PRIx64"\n",
178 fam10h_pci_mmconf_base);
179 val &= ~((FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT) |
180 (FAM10H_MMIO_CONF_BUSRANGE_MASK<<FAM10H_MMIO_CONF_BUSRANGE_SHIFT));
181 val |= fam10h_pci_mmconf_base | (8 << FAM10H_MMIO_CONF_BUSRANGE_SHIFT) |
182 FAM10H_MMIO_CONF_ENABLE;
183 wrmsrl(MSR_FAM10H_MMIO_CONF_BASE, val);
184 }
185
set_check_enable_amd_mmconf(struct dmi_system_id * d)186 static int __init set_check_enable_amd_mmconf(struct dmi_system_id *d)
187 {
188 pci_probe |= PCI_CHECK_ENABLE_AMD_MMCONF;
189 return 0;
190 }
191
192 static struct dmi_system_id __initdata mmconf_dmi_table[] = {
193 {
194 .callback = set_check_enable_amd_mmconf,
195 .ident = "Sun Microsystems Machine",
196 .matches = {
197 DMI_MATCH(DMI_SYS_VENDOR, "Sun Microsystems"),
198 },
199 },
200 {}
201 };
202
check_enable_amd_mmconf_dmi(void)203 void __init check_enable_amd_mmconf_dmi(void)
204 {
205 dmi_check_system(mmconf_dmi_table);
206 }
207