1 #include <asm/cpufeature.h>
2 #include <asm/cpuerrata.h>
3
4 #define MIDR_RANGE(model, min, max) \
5 .matches = is_affected_midr_range, \
6 .midr_model = model, \
7 .midr_range_min = min, \
8 .midr_range_max = max
9
10 static bool __maybe_unused
is_affected_midr_range(const struct arm_cpu_capabilities * entry)11 is_affected_midr_range(const struct arm_cpu_capabilities *entry)
12 {
13 return MIDR_IS_CPU_MODEL_RANGE(boot_cpu_data.midr.bits, entry->midr_model,
14 entry->midr_range_min,
15 entry->midr_range_max);
16 }
17
18 static const struct arm_cpu_capabilities arm_errata[] = {
19 {
20 /* Cortex-A15 r0p4 */
21 .desc = "ARM erratum 766422",
22 .capability = ARM32_WORKAROUND_766422,
23 MIDR_RANGE(MIDR_CORTEX_A15, 0x04, 0x04),
24 },
25 #if defined(CONFIG_ARM64_ERRATUM_827319) || \
26 defined(CONFIG_ARM64_ERRATUM_824069)
27 {
28 /* Cortex-A53 r0p[012] */
29 .desc = "ARM errata 827319, 824069",
30 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
31 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02),
32 },
33 #endif
34 #ifdef CONFIG_ARM64_ERRATUM_819472
35 {
36 /* Cortex-A53 r0[01] */
37 .desc = "ARM erratum 819472",
38 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
39 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01),
40 },
41 #endif
42 #ifdef CONFIG_ARM64_ERRATUM_832075
43 {
44 /* Cortex-A57 r0p0 - r1p2 */
45 .desc = "ARM erratum 832075",
46 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
47 MIDR_RANGE(MIDR_CORTEX_A57, 0x00,
48 (1 << MIDR_VARIANT_SHIFT) | 2),
49 },
50 #endif
51 #ifdef CONFIG_ARM64_ERRATUM_834220
52 {
53 /* Cortex-A57 r0p0 - r1p2 */
54 .desc = "ARM erratum 834220",
55 .capability = ARM64_WORKAROUND_834220,
56 MIDR_RANGE(MIDR_CORTEX_A57, 0x00,
57 (1 << MIDR_VARIANT_SHIFT) | 2),
58 },
59 #endif
60 {},
61 };
62
check_local_cpu_errata(void)63 void check_local_cpu_errata(void)
64 {
65 update_cpu_capabilities(arm_errata, "enabled workaround for");
66 }
67 /*
68 * Local variables:
69 * mode: C
70 * c-file-style: "BSD"
71 * c-basic-offset: 4
72 * indent-tabs-mode: nil
73 * End:
74 */
75