1 /*
2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <assert.h>
9 #include <stdbool.h>
10 #include <string.h>
11
12 #include <platform_def.h>
13
14 #include <arch.h>
15 #include <arch_helpers.h>
16 #include <arch_features.h>
17 #include <bl31/interrupt_mgmt.h>
18 #include <common/bl_common.h>
19 #include <common/debug.h>
20 #include <context.h>
21 #include <drivers/arm/gicv3.h>
22 #include <lib/el3_runtime/context_mgmt.h>
23 #include <lib/el3_runtime/pubsub_events.h>
24 #include <lib/extensions/amu.h>
25 #include <lib/extensions/brbe.h>
26 #include <lib/extensions/mpam.h>
27 #include <lib/extensions/sme.h>
28 #include <lib/extensions/spe.h>
29 #include <lib/extensions/sve.h>
30 #include <lib/extensions/sys_reg_trace.h>
31 #include <lib/extensions/trbe.h>
32 #include <lib/extensions/trf.h>
33 #include <lib/utils.h>
34
35 #if ENABLE_FEAT_TWED
36 /* Make sure delay value fits within the range(0-15) */
37 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check);
38 #endif /* ENABLE_FEAT_TWED */
39
40 static void manage_extensions_secure(cpu_context_t *ctx);
41
setup_el1_context(cpu_context_t * ctx,const struct entry_point_info * ep)42 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep)
43 {
44 u_register_t sctlr_elx, actlr_elx;
45
46 /*
47 * Initialise SCTLR_EL1 to the reset value corresponding to the target
48 * execution state setting all fields rather than relying on the hw.
49 * Some fields have architecturally UNKNOWN reset values and these are
50 * set to zero.
51 *
52 * SCTLR.EE: Endianness is taken from the entrypoint attributes.
53 *
54 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as
55 * required by PSCI specification)
56 */
57 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL;
58 if (GET_RW(ep->spsr) == MODE_RW_64) {
59 sctlr_elx |= SCTLR_EL1_RES1;
60 } else {
61 /*
62 * If the target execution state is AArch32 then the following
63 * fields need to be set.
64 *
65 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE
66 * instructions are not trapped to EL1.
67 *
68 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI
69 * instructions are not trapped to EL1.
70 *
71 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the
72 * CP15DMB, CP15DSB, and CP15ISB instructions.
73 */
74 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT
75 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT;
76 }
77
78 #if ERRATA_A75_764081
79 /*
80 * If workaround of errata 764081 for Cortex-A75 is used then set
81 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier.
82 */
83 sctlr_elx |= SCTLR_IESB_BIT;
84 #endif
85 /* Store the initialised SCTLR_EL1 value in the cpu_context */
86 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx);
87
88 /*
89 * Base the context ACTLR_EL1 on the current value, as it is
90 * implementation defined. The context restore process will write
91 * the value from the context to the actual register and can cause
92 * problems for processor cores that don't expect certain bits to
93 * be zero.
94 */
95 actlr_elx = read_actlr_el1();
96 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx));
97 }
98
99 /******************************************************************************
100 * This function performs initializations that are specific to SECURE state
101 * and updates the cpu context specified by 'ctx'.
102 *****************************************************************************/
setup_secure_context(cpu_context_t * ctx,const struct entry_point_info * ep)103 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep)
104 {
105 u_register_t scr_el3;
106 el3_state_t *state;
107
108 state = get_el3state_ctx(ctx);
109 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
110
111 #if defined(IMAGE_BL31) && !defined(SPD_spmd)
112 /*
113 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
114 * indicated by the interrupt routing model for BL31.
115 */
116 scr_el3 |= get_scr_el3_from_routing_model(SECURE);
117 #endif
118
119 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS
120 /* Get Memory Tagging Extension support level */
121 unsigned int mte = get_armv8_5_mte_support();
122 #endif
123 /*
124 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS
125 * is set, or when MTE is only implemented at EL0.
126 */
127 #if CTX_INCLUDE_MTE_REGS
128 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY));
129 scr_el3 |= SCR_ATA_BIT;
130 #else
131 if (mte == MTE_IMPLEMENTED_EL0) {
132 scr_el3 |= SCR_ATA_BIT;
133 }
134 #endif /* CTX_INCLUDE_MTE_REGS */
135
136 /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */
137 if ((GET_EL(ep->spsr) == MODE_EL2) && is_armv8_4_sel2_present()) {
138 if (GET_RW(ep->spsr) != MODE_RW_64) {
139 ERROR("S-EL2 can not be used in AArch32\n.");
140 panic();
141 }
142
143 scr_el3 |= SCR_EEL2_BIT;
144 }
145
146 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
147
148 /*
149 * Initialize EL1 context registers unless SPMC is running
150 * at S-EL2.
151 */
152 #if !SPMD_SPM_AT_SEL2
153 setup_el1_context(ctx, ep);
154 #endif
155
156 manage_extensions_secure(ctx);
157 }
158
159 #if ENABLE_RME
160 /******************************************************************************
161 * This function performs initializations that are specific to REALM state
162 * and updates the cpu context specified by 'ctx'.
163 *****************************************************************************/
setup_realm_context(cpu_context_t * ctx,const struct entry_point_info * ep)164 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep)
165 {
166 u_register_t scr_el3;
167 el3_state_t *state;
168
169 state = get_el3state_ctx(ctx);
170 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
171
172 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT | SCR_EnSCXT_BIT;
173
174 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
175 }
176 #endif /* ENABLE_RME */
177
178 /******************************************************************************
179 * This function performs initializations that are specific to NON-SECURE state
180 * and updates the cpu context specified by 'ctx'.
181 *****************************************************************************/
setup_ns_context(cpu_context_t * ctx,const struct entry_point_info * ep)182 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep)
183 {
184 u_register_t scr_el3;
185 el3_state_t *state;
186
187 state = get_el3state_ctx(ctx);
188 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
189
190 /* SCR_NS: Set the NS bit */
191 scr_el3 |= SCR_NS_BIT;
192
193 #if !CTX_INCLUDE_PAUTH_REGS
194 /*
195 * If the pointer authentication registers aren't saved during world
196 * switches the value of the registers can be leaked from the Secure to
197 * the Non-secure world. To prevent this, rather than enabling pointer
198 * authentication everywhere, we only enable it in the Non-secure world.
199 *
200 * If the Secure world wants to use pointer authentication,
201 * CTX_INCLUDE_PAUTH_REGS must be set to 1.
202 */
203 scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
204 #endif /* !CTX_INCLUDE_PAUTH_REGS */
205
206 /* Allow access to Allocation Tags when MTE is implemented. */
207 scr_el3 |= SCR_ATA_BIT;
208
209 #if HANDLE_EA_EL3_FIRST_NS
210 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */
211 scr_el3 |= SCR_EA_BIT;
212 #endif
213
214 #if RAS_TRAP_NS_ERR_REC_ACCESS
215 /*
216 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR
217 * and RAS ERX registers from EL1 and EL2(from any security state)
218 * are trapped to EL3.
219 * Set here to trap only for NS EL1/EL2
220 *
221 */
222 scr_el3 |= SCR_TERR_BIT;
223 #endif
224
225 #ifdef IMAGE_BL31
226 /*
227 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
228 * indicated by the interrupt routing model for BL31.
229 */
230 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE);
231 #endif
232 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
233
234 /* Initialize EL1 context registers */
235 setup_el1_context(ctx, ep);
236
237 /* Initialize EL2 context registers */
238 #if CTX_INCLUDE_EL2_REGS
239
240 /*
241 * Initialize SCTLR_EL2 context register using Endianness value
242 * taken from the entrypoint attribute.
243 */
244 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL;
245 sctlr_el2 |= SCTLR_EL2_RES1;
246 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2,
247 sctlr_el2);
248
249 /*
250 * Program the ICC_SRE_EL2 to make sure the correct bits are set
251 * when restoring NS context.
252 */
253 u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT |
254 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT;
255 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2,
256 icc_sre_el2);
257
258 /*
259 * Initialize MDCR_EL2.HPMN to its hardware reset value so we don't
260 * throw anyone off who expects this to be sensible.
261 * TODO: A similar thing happens in cm_prepare_el3_exit. They should be
262 * unified with the proper PMU implementation
263 */
264 u_register_t mdcr_el2 = ((read_pmcr_el0() >> PMCR_EL0_N_SHIFT) &
265 PMCR_EL0_N_MASK);
266 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_MDCR_EL2, mdcr_el2);
267 #endif /* CTX_INCLUDE_EL2_REGS */
268 }
269
270 /*******************************************************************************
271 * The following function performs initialization of the cpu_context 'ctx'
272 * for first use that is common to all security states, and sets the
273 * initial entrypoint state as specified by the entry_point_info structure.
274 *
275 * The EE and ST attributes are used to configure the endianness and secure
276 * timer availability for the new execution context.
277 ******************************************************************************/
setup_context_common(cpu_context_t * ctx,const entry_point_info_t * ep)278 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep)
279 {
280 u_register_t scr_el3;
281 el3_state_t *state;
282 gp_regs_t *gp_regs;
283
284 /* Clear any residual register values from the context */
285 zeromem(ctx, sizeof(*ctx));
286
287 /*
288 * SCR_EL3 was initialised during reset sequence in macro
289 * el3_arch_init_common. This code modifies the SCR_EL3 fields that
290 * affect the next EL.
291 *
292 * The following fields are initially set to zero and then updated to
293 * the required value depending on the state of the SPSR_EL3 and the
294 * Security state and entrypoint attributes of the next EL.
295 */
296 scr_el3 = read_scr();
297 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_EA_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT |
298 SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT);
299
300 /*
301 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next
302 * Exception level as specified by SPSR.
303 */
304 if (GET_RW(ep->spsr) == MODE_RW_64) {
305 scr_el3 |= SCR_RW_BIT;
306 }
307
308 /*
309 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical
310 * Secure timer registers to EL3, from AArch64 state only, if specified
311 * by the entrypoint attributes. If SEL2 is present and enabled, the ST
312 * bit always behaves as 1 (i.e. secure physical timer register access
313 * is not trapped)
314 */
315 if (EP_GET_ST(ep->h.attr) != 0U) {
316 scr_el3 |= SCR_ST_BIT;
317 }
318
319 /*
320 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting
321 * SCR_EL3.HXEn.
322 */
323 #if ENABLE_FEAT_HCX
324 scr_el3 |= SCR_HXEn_BIT;
325 #endif
326
327 /*
328 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS
329 * registers are trapped to EL3.
330 */
331 #if ENABLE_FEAT_RNG_TRAP
332 scr_el3 |= SCR_TRNDR_BIT;
333 #endif
334
335 #if FAULT_INJECTION_SUPPORT
336 /* Enable fault injection from lower ELs */
337 scr_el3 |= SCR_FIEN_BIT;
338 #endif
339
340 /*
341 * CPTR_EL3 was initialized out of reset, copy that value to the
342 * context register.
343 */
344 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3());
345
346 /*
347 * SCR_EL3.HCE: Enable HVC instructions if next execution state is
348 * AArch64 and next EL is EL2, or if next execution state is AArch32 and
349 * next mode is Hyp.
350 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the
351 * same conditions as HVC instructions and when the processor supports
352 * ARMv8.6-FGT.
353 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV)
354 * CNTPOFF_EL2 register under the same conditions as HVC instructions
355 * and when the processor supports ECV.
356 */
357 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2))
358 || ((GET_RW(ep->spsr) != MODE_RW_64)
359 && (GET_M32(ep->spsr) == MODE32_hyp))) {
360 scr_el3 |= SCR_HCE_BIT;
361
362 if (is_armv8_6_fgt_present()) {
363 scr_el3 |= SCR_FGTEN_BIT;
364 }
365
366 if (get_armv8_6_ecv_support()
367 == ID_AA64MMFR0_EL1_ECV_SELF_SYNCH) {
368 scr_el3 |= SCR_ECVEN_BIT;
369 }
370 }
371
372 #if ENABLE_FEAT_TWED
373 /* Enable WFE trap delay in SCR_EL3 if supported and configured */
374 /* Set delay in SCR_EL3 */
375 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT);
376 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK)
377 << SCR_TWEDEL_SHIFT);
378
379 /* Enable WFE delay */
380 scr_el3 |= SCR_TWEDEn_BIT;
381 #endif /* ENABLE_FEAT_TWED */
382
383 /*
384 * Populate EL3 state so that we've the right context
385 * before doing ERET
386 */
387 state = get_el3state_ctx(ctx);
388 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
389 write_ctx_reg(state, CTX_ELR_EL3, ep->pc);
390 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr);
391
392 /*
393 * Store the X0-X7 value from the entrypoint into the context
394 * Use memcpy as we are in control of the layout of the structures
395 */
396 gp_regs = get_gpregs_ctx(ctx);
397 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t));
398 }
399
400 /*******************************************************************************
401 * Context management library initialization routine. This library is used by
402 * runtime services to share pointers to 'cpu_context' structures for secure
403 * non-secure and realm states. Management of the structures and their associated
404 * memory is not done by the context management library e.g. the PSCI service
405 * manages the cpu context used for entry from and exit to the non-secure state.
406 * The Secure payload dispatcher service manages the context(s) corresponding to
407 * the secure state. It also uses this library to get access to the non-secure
408 * state cpu context pointers.
409 * Lastly, this library provides the API to make SP_EL3 point to the cpu context
410 * which will be used for programming an entry into a lower EL. The same context
411 * will be used to save state upon exception entry from that EL.
412 ******************************************************************************/
cm_init(void)413 void __init cm_init(void)
414 {
415 /*
416 * The context management library has only global data to intialize, but
417 * that will be done when the BSS is zeroed out.
418 */
419 }
420
421 /*******************************************************************************
422 * This is the high-level function used to initialize the cpu_context 'ctx' for
423 * first use. It performs initializations that are common to all security states
424 * and initializations specific to the security state specified in 'ep'
425 ******************************************************************************/
cm_setup_context(cpu_context_t * ctx,const entry_point_info_t * ep)426 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
427 {
428 unsigned int security_state;
429
430 assert(ctx != NULL);
431
432 /*
433 * Perform initializations that are common
434 * to all security states
435 */
436 setup_context_common(ctx, ep);
437
438 security_state = GET_SECURITY_STATE(ep->h.attr);
439
440 /* Perform security state specific initializations */
441 switch (security_state) {
442 case SECURE:
443 setup_secure_context(ctx, ep);
444 break;
445 #if ENABLE_RME
446 case REALM:
447 setup_realm_context(ctx, ep);
448 break;
449 #endif
450 case NON_SECURE:
451 setup_ns_context(ctx, ep);
452 break;
453 default:
454 ERROR("Invalid security state\n");
455 panic();
456 break;
457 }
458 }
459
460 /*******************************************************************************
461 * Enable architecture extensions on first entry to Non-secure world.
462 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise
463 * it is zero.
464 ******************************************************************************/
manage_extensions_nonsecure(bool el2_unused,cpu_context_t * ctx)465 static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx)
466 {
467 #if IMAGE_BL31
468 #if ENABLE_SPE_FOR_LOWER_ELS
469 spe_enable(el2_unused);
470 #endif
471
472 #if ENABLE_AMU
473 amu_enable(el2_unused, ctx);
474 #endif
475
476 #if ENABLE_SME_FOR_NS
477 /* Enable SME, SVE, and FPU/SIMD for non-secure world. */
478 sme_enable(ctx);
479 #elif ENABLE_SVE_FOR_NS
480 /* Enable SVE and FPU/SIMD for non-secure world. */
481 sve_enable(ctx);
482 #endif
483
484 #if ENABLE_MPAM_FOR_LOWER_ELS
485 mpam_enable(el2_unused);
486 #endif
487
488 #if ENABLE_TRBE_FOR_NS
489 trbe_enable();
490 #endif /* ENABLE_TRBE_FOR_NS */
491
492 #if ENABLE_BRBE_FOR_NS
493 brbe_enable();
494 #endif /* ENABLE_BRBE_FOR_NS */
495
496 #if ENABLE_SYS_REG_TRACE_FOR_NS
497 sys_reg_trace_enable(ctx);
498 #endif /* ENABLE_SYS_REG_TRACE_FOR_NS */
499
500 #if ENABLE_TRF_FOR_NS
501 trf_enable();
502 #endif /* ENABLE_TRF_FOR_NS */
503 #endif
504 }
505
506 /*******************************************************************************
507 * Enable architecture extensions on first entry to Secure world.
508 ******************************************************************************/
manage_extensions_secure(cpu_context_t * ctx)509 static void manage_extensions_secure(cpu_context_t *ctx)
510 {
511 #if IMAGE_BL31
512 #if ENABLE_SME_FOR_NS
513 #if ENABLE_SME_FOR_SWD
514 /*
515 * Enable SME, SVE, FPU/SIMD in secure context, secure manager must
516 * ensure SME, SVE, and FPU/SIMD context properly managed.
517 */
518 sme_enable(ctx);
519 #else /* ENABLE_SME_FOR_SWD */
520 /*
521 * Disable SME, SVE, FPU/SIMD in secure context so non-secure world can
522 * safely use the associated registers.
523 */
524 sme_disable(ctx);
525 #endif /* ENABLE_SME_FOR_SWD */
526 #elif ENABLE_SVE_FOR_NS
527 #if ENABLE_SVE_FOR_SWD
528 /*
529 * Enable SVE and FPU in secure context, secure manager must ensure that
530 * the SVE and FPU register contexts are properly managed.
531 */
532 sve_enable(ctx);
533 #else /* ENABLE_SVE_FOR_SWD */
534 /*
535 * Disable SVE and FPU in secure context so non-secure world can safely
536 * use them.
537 */
538 sve_disable(ctx);
539 #endif /* ENABLE_SVE_FOR_SWD */
540 #endif /* ENABLE_SVE_FOR_NS */
541 #endif /* IMAGE_BL31 */
542 }
543
544 /*******************************************************************************
545 * The following function initializes the cpu_context for a CPU specified by
546 * its `cpu_idx` for first use, and sets the initial entrypoint state as
547 * specified by the entry_point_info structure.
548 ******************************************************************************/
cm_init_context_by_index(unsigned int cpu_idx,const entry_point_info_t * ep)549 void cm_init_context_by_index(unsigned int cpu_idx,
550 const entry_point_info_t *ep)
551 {
552 cpu_context_t *ctx;
553 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr));
554 cm_setup_context(ctx, ep);
555 }
556
557 /*******************************************************************************
558 * The following function initializes the cpu_context for the current CPU
559 * for first use, and sets the initial entrypoint state as specified by the
560 * entry_point_info structure.
561 ******************************************************************************/
cm_init_my_context(const entry_point_info_t * ep)562 void cm_init_my_context(const entry_point_info_t *ep)
563 {
564 cpu_context_t *ctx;
565 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr));
566 cm_setup_context(ctx, ep);
567 }
568
569 /*******************************************************************************
570 * Prepare the CPU system registers for first entry into realm, secure, or
571 * normal world.
572 *
573 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized
574 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports
575 * EL2 then EL2 is disabled by configuring all necessary EL2 registers.
576 * For all entries, the EL1 registers are initialized from the cpu_context
577 ******************************************************************************/
cm_prepare_el3_exit(uint32_t security_state)578 void cm_prepare_el3_exit(uint32_t security_state)
579 {
580 u_register_t sctlr_elx, scr_el3, mdcr_el2;
581 cpu_context_t *ctx = cm_get_context(security_state);
582 bool el2_unused = false;
583 uint64_t hcr_el2 = 0U;
584
585 assert(ctx != NULL);
586
587 if (security_state == NON_SECURE) {
588 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx),
589 CTX_SCR_EL3);
590 if ((scr_el3 & SCR_HCE_BIT) != 0U) {
591 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
592 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx),
593 CTX_SCTLR_EL1);
594 sctlr_elx &= SCTLR_EE_BIT;
595 sctlr_elx |= SCTLR_EL2_RES1;
596 #if ERRATA_A75_764081
597 /*
598 * If workaround of errata 764081 for Cortex-A75 is used
599 * then set SCTLR_EL2.IESB to enable Implicit Error
600 * Synchronization Barrier.
601 */
602 sctlr_elx |= SCTLR_IESB_BIT;
603 #endif
604 write_sctlr_el2(sctlr_elx);
605 } else if (el_implemented(2) != EL_IMPL_NONE) {
606 el2_unused = true;
607
608 /*
609 * EL2 present but unused, need to disable safely.
610 * SCTLR_EL2 can be ignored in this case.
611 *
612 * Set EL2 register width appropriately: Set HCR_EL2
613 * field to match SCR_EL3.RW.
614 */
615 if ((scr_el3 & SCR_RW_BIT) != 0U)
616 hcr_el2 |= HCR_RW_BIT;
617
618 /*
619 * For Armv8.3 pointer authentication feature, disable
620 * traps to EL2 when accessing key registers or using
621 * pointer authentication instructions from lower ELs.
622 */
623 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT);
624
625 write_hcr_el2(hcr_el2);
626
627 /*
628 * Initialise CPTR_EL2 setting all fields rather than
629 * relying on the hw. All fields have architecturally
630 * UNKNOWN reset values.
631 *
632 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1
633 * accesses to the CPACR_EL1 or CPACR from both
634 * Execution states do not trap to EL2.
635 *
636 * CPTR_EL2.TTA: Set to zero so that Non-secure System
637 * register accesses to the trace registers from both
638 * Execution states do not trap to EL2.
639 * If PE trace unit System registers are not implemented
640 * then this bit is reserved, and must be set to zero.
641 *
642 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses
643 * to SIMD and floating-point functionality from both
644 * Execution states do not trap to EL2.
645 */
646 write_cptr_el2(CPTR_EL2_RESET_VAL &
647 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT
648 | CPTR_EL2_TFP_BIT));
649
650 /*
651 * Initialise CNTHCTL_EL2. All fields are
652 * architecturally UNKNOWN on reset and are set to zero
653 * except for field(s) listed below.
654 *
655 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to
656 * Hyp mode of Non-secure EL0 and EL1 accesses to the
657 * physical timer registers.
658 *
659 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to
660 * Hyp mode of Non-secure EL0 and EL1 accesses to the
661 * physical counter registers.
662 */
663 write_cnthctl_el2(CNTHCTL_RESET_VAL |
664 EL1PCEN_BIT | EL1PCTEN_BIT);
665
666 /*
667 * Initialise CNTVOFF_EL2 to zero as it resets to an
668 * architecturally UNKNOWN value.
669 */
670 write_cntvoff_el2(0);
671
672 /*
673 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and
674 * MPIDR_EL1 respectively.
675 */
676 write_vpidr_el2(read_midr_el1());
677 write_vmpidr_el2(read_mpidr_el1());
678
679 /*
680 * Initialise VTTBR_EL2. All fields are architecturally
681 * UNKNOWN on reset.
682 *
683 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage
684 * 2 address translation is disabled, cache maintenance
685 * operations depend on the VMID.
686 *
687 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address
688 * translation is disabled.
689 */
690 write_vttbr_el2(VTTBR_RESET_VAL &
691 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT)
692 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT)));
693
694 /*
695 * Initialise MDCR_EL2, setting all fields rather than
696 * relying on hw. Some fields are architecturally
697 * UNKNOWN on reset.
698 *
699 * MDCR_EL2.HLP: Set to one so that event counter
700 * overflow, that is recorded in PMOVSCLR_EL0[0-30],
701 * occurs on the increment that changes
702 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is
703 * implemented. This bit is RES0 in versions of the
704 * architecture earlier than ARMv8.5, setting it to 1
705 * doesn't have any effect on them.
706 *
707 * MDCR_EL2.TTRF: Set to zero so that access to Trace
708 * Filter Control register TRFCR_EL1 at EL1 is not
709 * trapped to EL2. This bit is RES0 in versions of
710 * the architecture earlier than ARMv8.4.
711 *
712 * MDCR_EL2.HPMD: Set to one so that event counting is
713 * prohibited at EL2. This bit is RES0 in versions of
714 * the architecture earlier than ARMv8.1, setting it
715 * to 1 doesn't have any effect on them.
716 *
717 * MDCR_EL2.TPMS: Set to zero so that accesses to
718 * Statistical Profiling control registers from EL1
719 * do not trap to EL2. This bit is RES0 when SPE is
720 * not implemented.
721 *
722 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and
723 * EL1 System register accesses to the Debug ROM
724 * registers are not trapped to EL2.
725 *
726 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1
727 * System register accesses to the powerdown debug
728 * registers are not trapped to EL2.
729 *
730 * MDCR_EL2.TDA: Set to zero so that System register
731 * accesses to the debug registers do not trap to EL2.
732 *
733 * MDCR_EL2.TDE: Set to zero so that debug exceptions
734 * are not routed to EL2.
735 *
736 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance
737 * Monitors.
738 *
739 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and
740 * EL1 accesses to all Performance Monitors registers
741 * are not trapped to EL2.
742 *
743 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0
744 * and EL1 accesses to the PMCR_EL0 or PMCR are not
745 * trapped to EL2.
746 *
747 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the
748 * architecturally-defined reset value.
749 *
750 * MDCR_EL2.E2TB: Set to zero so that the trace Buffer
751 * owning exception level is NS-EL1 and, tracing is
752 * prohibited at NS-EL2. These bits are RES0 when
753 * FEAT_TRBE is not implemented.
754 */
755 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP |
756 MDCR_EL2_HPMD) |
757 ((read_pmcr_el0() & PMCR_EL0_N_BITS)
758 >> PMCR_EL0_N_SHIFT)) &
759 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS |
760 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT |
761 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT |
762 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT |
763 MDCR_EL2_TPMCR_BIT |
764 MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1));
765
766 write_mdcr_el2(mdcr_el2);
767
768 /*
769 * Initialise HSTR_EL2. All fields are architecturally
770 * UNKNOWN on reset.
771 *
772 * HSTR_EL2.T<n>: Set all these fields to zero so that
773 * Non-secure EL0 or EL1 accesses to System registers
774 * do not trap to EL2.
775 */
776 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK));
777 /*
778 * Initialise CNTHP_CTL_EL2. All fields are
779 * architecturally UNKNOWN on reset.
780 *
781 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2
782 * physical timer and prevent timer interrupts.
783 */
784 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL &
785 ~(CNTHP_CTL_ENABLE_BIT));
786 }
787 manage_extensions_nonsecure(el2_unused, ctx);
788 }
789
790 cm_el1_sysregs_context_restore(security_state);
791 cm_set_next_eret_context(security_state);
792 }
793
794 #if CTX_INCLUDE_EL2_REGS
795 /*******************************************************************************
796 * Save EL2 sysreg context
797 ******************************************************************************/
cm_el2_sysregs_context_save(uint32_t security_state)798 void cm_el2_sysregs_context_save(uint32_t security_state)
799 {
800 u_register_t scr_el3 = read_scr();
801
802 /*
803 * Always save the non-secure and realm EL2 context, only save the
804 * S-EL2 context if S-EL2 is enabled.
805 */
806 if ((security_state != SECURE) ||
807 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) {
808 cpu_context_t *ctx;
809 el2_sysregs_t *el2_sysregs_ctx;
810
811 ctx = cm_get_context(security_state);
812 assert(ctx != NULL);
813
814 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx);
815
816 el2_sysregs_context_save_common(el2_sysregs_ctx);
817 #if ENABLE_SPE_FOR_LOWER_ELS
818 el2_sysregs_context_save_spe(el2_sysregs_ctx);
819 #endif
820 #if CTX_INCLUDE_MTE_REGS
821 el2_sysregs_context_save_mte(el2_sysregs_ctx);
822 #endif
823 #if ENABLE_MPAM_FOR_LOWER_ELS
824 el2_sysregs_context_save_mpam(el2_sysregs_ctx);
825 #endif
826 #if ENABLE_FEAT_FGT
827 el2_sysregs_context_save_fgt(el2_sysregs_ctx);
828 #endif
829 #if ENABLE_FEAT_ECV
830 el2_sysregs_context_save_ecv(el2_sysregs_ctx);
831 #endif
832 #if ENABLE_FEAT_VHE
833 el2_sysregs_context_save_vhe(el2_sysregs_ctx);
834 #endif
835 #if RAS_EXTENSION
836 el2_sysregs_context_save_ras(el2_sysregs_ctx);
837 #endif
838 #if CTX_INCLUDE_NEVE_REGS
839 el2_sysregs_context_save_nv2(el2_sysregs_ctx);
840 #endif
841 #if ENABLE_TRF_FOR_NS
842 el2_sysregs_context_save_trf(el2_sysregs_ctx);
843 #endif
844 #if ENABLE_FEAT_CSV2_2
845 el2_sysregs_context_save_csv2(el2_sysregs_ctx);
846 #endif
847 #if ENABLE_FEAT_HCX
848 el2_sysregs_context_save_hcx(el2_sysregs_ctx);
849 #endif
850 }
851 }
852
853 /*******************************************************************************
854 * Restore EL2 sysreg context
855 ******************************************************************************/
cm_el2_sysregs_context_restore(uint32_t security_state)856 void cm_el2_sysregs_context_restore(uint32_t security_state)
857 {
858 u_register_t scr_el3 = read_scr();
859
860 /*
861 * Always restore the non-secure and realm EL2 context, only restore the
862 * S-EL2 context if S-EL2 is enabled.
863 */
864 if ((security_state != SECURE) ||
865 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) {
866 cpu_context_t *ctx;
867 el2_sysregs_t *el2_sysregs_ctx;
868
869 ctx = cm_get_context(security_state);
870 assert(ctx != NULL);
871
872 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx);
873
874 el2_sysregs_context_restore_common(el2_sysregs_ctx);
875 #if ENABLE_SPE_FOR_LOWER_ELS
876 el2_sysregs_context_restore_spe(el2_sysregs_ctx);
877 #endif
878 #if CTX_INCLUDE_MTE_REGS
879 el2_sysregs_context_restore_mte(el2_sysregs_ctx);
880 #endif
881 #if ENABLE_MPAM_FOR_LOWER_ELS
882 el2_sysregs_context_restore_mpam(el2_sysregs_ctx);
883 #endif
884 #if ENABLE_FEAT_FGT
885 el2_sysregs_context_restore_fgt(el2_sysregs_ctx);
886 #endif
887 #if ENABLE_FEAT_ECV
888 el2_sysregs_context_restore_ecv(el2_sysregs_ctx);
889 #endif
890 #if ENABLE_FEAT_VHE
891 el2_sysregs_context_restore_vhe(el2_sysregs_ctx);
892 #endif
893 #if RAS_EXTENSION
894 el2_sysregs_context_restore_ras(el2_sysregs_ctx);
895 #endif
896 #if CTX_INCLUDE_NEVE_REGS
897 el2_sysregs_context_restore_nv2(el2_sysregs_ctx);
898 #endif
899 #if ENABLE_TRF_FOR_NS
900 el2_sysregs_context_restore_trf(el2_sysregs_ctx);
901 #endif
902 #if ENABLE_FEAT_CSV2_2
903 el2_sysregs_context_restore_csv2(el2_sysregs_ctx);
904 #endif
905 #if ENABLE_FEAT_HCX
906 el2_sysregs_context_restore_hcx(el2_sysregs_ctx);
907 #endif
908 }
909 }
910 #endif /* CTX_INCLUDE_EL2_REGS */
911
912 /*******************************************************************************
913 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS
914 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly
915 * updating EL1 and EL2 registers. Otherwise, it calls the generic
916 * cm_prepare_el3_exit function.
917 ******************************************************************************/
cm_prepare_el3_exit_ns(void)918 void cm_prepare_el3_exit_ns(void)
919 {
920 #if CTX_INCLUDE_EL2_REGS
921 cpu_context_t *ctx = cm_get_context(NON_SECURE);
922 assert(ctx != NULL);
923
924 /* Assert that EL2 is used. */
925 #if ENABLE_ASSERTIONS
926 el3_state_t *state = get_el3state_ctx(ctx);
927 u_register_t scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
928 #endif
929 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) &&
930 (el_implemented(2U) != EL_IMPL_NONE));
931
932 /*
933 * Currently some extensions are configured using
934 * direct register updates. Therefore, do this here
935 * instead of when setting up context.
936 */
937 manage_extensions_nonsecure(0, ctx);
938
939 /*
940 * Set the NS bit to be able to access the ICC_SRE_EL2
941 * register when restoring context.
942 */
943 write_scr_el3(read_scr_el3() | SCR_NS_BIT);
944
945 /*
946 * Ensure the NS bit change is committed before the EL2/EL1
947 * state restoration.
948 */
949 isb();
950
951 /* Restore EL2 and EL1 sysreg contexts */
952 cm_el2_sysregs_context_restore(NON_SECURE);
953 cm_el1_sysregs_context_restore(NON_SECURE);
954 cm_set_next_eret_context(NON_SECURE);
955 #else
956 cm_prepare_el3_exit(NON_SECURE);
957 #endif /* CTX_INCLUDE_EL2_REGS */
958 }
959
960 /*******************************************************************************
961 * The next four functions are used by runtime services to save and restore
962 * EL1 context on the 'cpu_context' structure for the specified security
963 * state.
964 ******************************************************************************/
cm_el1_sysregs_context_save(uint32_t security_state)965 void cm_el1_sysregs_context_save(uint32_t security_state)
966 {
967 cpu_context_t *ctx;
968
969 ctx = cm_get_context(security_state);
970 assert(ctx != NULL);
971
972 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx));
973
974 #if IMAGE_BL31
975 if (security_state == SECURE)
976 PUBLISH_EVENT(cm_exited_secure_world);
977 else
978 PUBLISH_EVENT(cm_exited_normal_world);
979 #endif
980 }
981
cm_el1_sysregs_context_restore(uint32_t security_state)982 void cm_el1_sysregs_context_restore(uint32_t security_state)
983 {
984 cpu_context_t *ctx;
985
986 ctx = cm_get_context(security_state);
987 assert(ctx != NULL);
988
989 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx));
990
991 #if IMAGE_BL31
992 if (security_state == SECURE)
993 PUBLISH_EVENT(cm_entering_secure_world);
994 else
995 PUBLISH_EVENT(cm_entering_normal_world);
996 #endif
997 }
998
999 /*******************************************************************************
1000 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the
1001 * given security state with the given entrypoint
1002 ******************************************************************************/
cm_set_elr_el3(uint32_t security_state,uintptr_t entrypoint)1003 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint)
1004 {
1005 cpu_context_t *ctx;
1006 el3_state_t *state;
1007
1008 ctx = cm_get_context(security_state);
1009 assert(ctx != NULL);
1010
1011 /* Populate EL3 state so that ERET jumps to the correct entry */
1012 state = get_el3state_ctx(ctx);
1013 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
1014 }
1015
1016 /*******************************************************************************
1017 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context'
1018 * pertaining to the given security state
1019 ******************************************************************************/
cm_set_elr_spsr_el3(uint32_t security_state,uintptr_t entrypoint,uint32_t spsr)1020 void cm_set_elr_spsr_el3(uint32_t security_state,
1021 uintptr_t entrypoint, uint32_t spsr)
1022 {
1023 cpu_context_t *ctx;
1024 el3_state_t *state;
1025
1026 ctx = cm_get_context(security_state);
1027 assert(ctx != NULL);
1028
1029 /* Populate EL3 state so that ERET jumps to the correct entry */
1030 state = get_el3state_ctx(ctx);
1031 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
1032 write_ctx_reg(state, CTX_SPSR_EL3, spsr);
1033 }
1034
1035 /*******************************************************************************
1036 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context'
1037 * pertaining to the given security state using the value and bit position
1038 * specified in the parameters. It preserves all other bits.
1039 ******************************************************************************/
cm_write_scr_el3_bit(uint32_t security_state,uint32_t bit_pos,uint32_t value)1040 void cm_write_scr_el3_bit(uint32_t security_state,
1041 uint32_t bit_pos,
1042 uint32_t value)
1043 {
1044 cpu_context_t *ctx;
1045 el3_state_t *state;
1046 u_register_t scr_el3;
1047
1048 ctx = cm_get_context(security_state);
1049 assert(ctx != NULL);
1050
1051 /* Ensure that the bit position is a valid one */
1052 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U);
1053
1054 /* Ensure that the 'value' is only a bit wide */
1055 assert(value <= 1U);
1056
1057 /*
1058 * Get the SCR_EL3 value from the cpu context, clear the desired bit
1059 * and set it to its new value.
1060 */
1061 state = get_el3state_ctx(ctx);
1062 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
1063 scr_el3 &= ~(1UL << bit_pos);
1064 scr_el3 |= (u_register_t)value << bit_pos;
1065 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
1066 }
1067
1068 /*******************************************************************************
1069 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the
1070 * given security state.
1071 ******************************************************************************/
cm_get_scr_el3(uint32_t security_state)1072 u_register_t cm_get_scr_el3(uint32_t security_state)
1073 {
1074 cpu_context_t *ctx;
1075 el3_state_t *state;
1076
1077 ctx = cm_get_context(security_state);
1078 assert(ctx != NULL);
1079
1080 /* Populate EL3 state so that ERET jumps to the correct entry */
1081 state = get_el3state_ctx(ctx);
1082 return read_ctx_reg(state, CTX_SCR_EL3);
1083 }
1084
1085 /*******************************************************************************
1086 * This function is used to program the context that's used for exception
1087 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for
1088 * the required security state
1089 ******************************************************************************/
cm_set_next_eret_context(uint32_t security_state)1090 void cm_set_next_eret_context(uint32_t security_state)
1091 {
1092 cpu_context_t *ctx;
1093
1094 ctx = cm_get_context(security_state);
1095 assert(ctx != NULL);
1096
1097 cm_set_next_context(ctx);
1098 }
1099