1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2// 3// Device Tree Include file for Layerscape-LX2160A family SoC. 4// 5// Copyright 2018-2020 NXP 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10/memreserve/ 0x80000000 0x00010000; 11 12/ { 13 compatible = "fsl,lx2160a"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 rtc1 = &ftm_alarm0; 20 }; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 // 8 clusters having 2 Cortex-A72 cores each 27 cpu0: cpu@0 { 28 device_type = "cpu"; 29 compatible = "arm,cortex-a72"; 30 enable-method = "psci"; 31 reg = <0x0>; 32 clocks = <&clockgen 1 0>; 33 d-cache-size = <0x8000>; 34 d-cache-line-size = <64>; 35 d-cache-sets = <128>; 36 i-cache-size = <0xC000>; 37 i-cache-line-size = <64>; 38 i-cache-sets = <192>; 39 next-level-cache = <&cluster0_l2>; 40 cpu-idle-states = <&cpu_pw15>; 41 #cooling-cells = <2>; 42 }; 43 44 cpu1: cpu@1 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a72"; 47 enable-method = "psci"; 48 reg = <0x1>; 49 clocks = <&clockgen 1 0>; 50 d-cache-size = <0x8000>; 51 d-cache-line-size = <64>; 52 d-cache-sets = <128>; 53 i-cache-size = <0xC000>; 54 i-cache-line-size = <64>; 55 i-cache-sets = <192>; 56 next-level-cache = <&cluster0_l2>; 57 cpu-idle-states = <&cpu_pw15>; 58 #cooling-cells = <2>; 59 }; 60 61 cpu100: cpu@100 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a72"; 64 enable-method = "psci"; 65 reg = <0x100>; 66 clocks = <&clockgen 1 1>; 67 d-cache-size = <0x8000>; 68 d-cache-line-size = <64>; 69 d-cache-sets = <128>; 70 i-cache-size = <0xC000>; 71 i-cache-line-size = <64>; 72 i-cache-sets = <192>; 73 next-level-cache = <&cluster1_l2>; 74 cpu-idle-states = <&cpu_pw15>; 75 #cooling-cells = <2>; 76 }; 77 78 cpu101: cpu@101 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a72"; 81 enable-method = "psci"; 82 reg = <0x101>; 83 clocks = <&clockgen 1 1>; 84 d-cache-size = <0x8000>; 85 d-cache-line-size = <64>; 86 d-cache-sets = <128>; 87 i-cache-size = <0xC000>; 88 i-cache-line-size = <64>; 89 i-cache-sets = <192>; 90 next-level-cache = <&cluster1_l2>; 91 cpu-idle-states = <&cpu_pw15>; 92 #cooling-cells = <2>; 93 }; 94 95 cpu200: cpu@200 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a72"; 98 enable-method = "psci"; 99 reg = <0x200>; 100 clocks = <&clockgen 1 2>; 101 d-cache-size = <0x8000>; 102 d-cache-line-size = <64>; 103 d-cache-sets = <128>; 104 i-cache-size = <0xC000>; 105 i-cache-line-size = <64>; 106 i-cache-sets = <192>; 107 next-level-cache = <&cluster2_l2>; 108 cpu-idle-states = <&cpu_pw15>; 109 #cooling-cells = <2>; 110 }; 111 112 cpu201: cpu@201 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a72"; 115 enable-method = "psci"; 116 reg = <0x201>; 117 clocks = <&clockgen 1 2>; 118 d-cache-size = <0x8000>; 119 d-cache-line-size = <64>; 120 d-cache-sets = <128>; 121 i-cache-size = <0xC000>; 122 i-cache-line-size = <64>; 123 i-cache-sets = <192>; 124 next-level-cache = <&cluster2_l2>; 125 cpu-idle-states = <&cpu_pw15>; 126 #cooling-cells = <2>; 127 }; 128 129 cpu300: cpu@300 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a72"; 132 enable-method = "psci"; 133 reg = <0x300>; 134 clocks = <&clockgen 1 3>; 135 d-cache-size = <0x8000>; 136 d-cache-line-size = <64>; 137 d-cache-sets = <128>; 138 i-cache-size = <0xC000>; 139 i-cache-line-size = <64>; 140 i-cache-sets = <192>; 141 next-level-cache = <&cluster3_l2>; 142 cpu-idle-states = <&cpu_pw15>; 143 #cooling-cells = <2>; 144 }; 145 146 cpu301: cpu@301 { 147 device_type = "cpu"; 148 compatible = "arm,cortex-a72"; 149 enable-method = "psci"; 150 reg = <0x301>; 151 clocks = <&clockgen 1 3>; 152 d-cache-size = <0x8000>; 153 d-cache-line-size = <64>; 154 d-cache-sets = <128>; 155 i-cache-size = <0xC000>; 156 i-cache-line-size = <64>; 157 i-cache-sets = <192>; 158 next-level-cache = <&cluster3_l2>; 159 cpu-idle-states = <&cpu_pw15>; 160 #cooling-cells = <2>; 161 }; 162 163 cpu400: cpu@400 { 164 device_type = "cpu"; 165 compatible = "arm,cortex-a72"; 166 enable-method = "psci"; 167 reg = <0x400>; 168 clocks = <&clockgen 1 4>; 169 d-cache-size = <0x8000>; 170 d-cache-line-size = <64>; 171 d-cache-sets = <128>; 172 i-cache-size = <0xC000>; 173 i-cache-line-size = <64>; 174 i-cache-sets = <192>; 175 next-level-cache = <&cluster4_l2>; 176 cpu-idle-states = <&cpu_pw15>; 177 #cooling-cells = <2>; 178 }; 179 180 cpu401: cpu@401 { 181 device_type = "cpu"; 182 compatible = "arm,cortex-a72"; 183 enable-method = "psci"; 184 reg = <0x401>; 185 clocks = <&clockgen 1 4>; 186 d-cache-size = <0x8000>; 187 d-cache-line-size = <64>; 188 d-cache-sets = <128>; 189 i-cache-size = <0xC000>; 190 i-cache-line-size = <64>; 191 i-cache-sets = <192>; 192 next-level-cache = <&cluster4_l2>; 193 cpu-idle-states = <&cpu_pw15>; 194 #cooling-cells = <2>; 195 }; 196 197 cpu500: cpu@500 { 198 device_type = "cpu"; 199 compatible = "arm,cortex-a72"; 200 enable-method = "psci"; 201 reg = <0x500>; 202 clocks = <&clockgen 1 5>; 203 d-cache-size = <0x8000>; 204 d-cache-line-size = <64>; 205 d-cache-sets = <128>; 206 i-cache-size = <0xC000>; 207 i-cache-line-size = <64>; 208 i-cache-sets = <192>; 209 next-level-cache = <&cluster5_l2>; 210 cpu-idle-states = <&cpu_pw15>; 211 #cooling-cells = <2>; 212 }; 213 214 cpu501: cpu@501 { 215 device_type = "cpu"; 216 compatible = "arm,cortex-a72"; 217 enable-method = "psci"; 218 reg = <0x501>; 219 clocks = <&clockgen 1 5>; 220 d-cache-size = <0x8000>; 221 d-cache-line-size = <64>; 222 d-cache-sets = <128>; 223 i-cache-size = <0xC000>; 224 i-cache-line-size = <64>; 225 i-cache-sets = <192>; 226 next-level-cache = <&cluster5_l2>; 227 cpu-idle-states = <&cpu_pw15>; 228 #cooling-cells = <2>; 229 }; 230 231 cpu600: cpu@600 { 232 device_type = "cpu"; 233 compatible = "arm,cortex-a72"; 234 enable-method = "psci"; 235 reg = <0x600>; 236 clocks = <&clockgen 1 6>; 237 d-cache-size = <0x8000>; 238 d-cache-line-size = <64>; 239 d-cache-sets = <128>; 240 i-cache-size = <0xC000>; 241 i-cache-line-size = <64>; 242 i-cache-sets = <192>; 243 next-level-cache = <&cluster6_l2>; 244 cpu-idle-states = <&cpu_pw15>; 245 #cooling-cells = <2>; 246 }; 247 248 cpu601: cpu@601 { 249 device_type = "cpu"; 250 compatible = "arm,cortex-a72"; 251 enable-method = "psci"; 252 reg = <0x601>; 253 clocks = <&clockgen 1 6>; 254 d-cache-size = <0x8000>; 255 d-cache-line-size = <64>; 256 d-cache-sets = <128>; 257 i-cache-size = <0xC000>; 258 i-cache-line-size = <64>; 259 i-cache-sets = <192>; 260 next-level-cache = <&cluster6_l2>; 261 cpu-idle-states = <&cpu_pw15>; 262 #cooling-cells = <2>; 263 }; 264 265 cpu700: cpu@700 { 266 device_type = "cpu"; 267 compatible = "arm,cortex-a72"; 268 enable-method = "psci"; 269 reg = <0x700>; 270 clocks = <&clockgen 1 7>; 271 d-cache-size = <0x8000>; 272 d-cache-line-size = <64>; 273 d-cache-sets = <128>; 274 i-cache-size = <0xC000>; 275 i-cache-line-size = <64>; 276 i-cache-sets = <192>; 277 next-level-cache = <&cluster7_l2>; 278 cpu-idle-states = <&cpu_pw15>; 279 #cooling-cells = <2>; 280 }; 281 282 cpu701: cpu@701 { 283 device_type = "cpu"; 284 compatible = "arm,cortex-a72"; 285 enable-method = "psci"; 286 reg = <0x701>; 287 clocks = <&clockgen 1 7>; 288 d-cache-size = <0x8000>; 289 d-cache-line-size = <64>; 290 d-cache-sets = <128>; 291 i-cache-size = <0xC000>; 292 i-cache-line-size = <64>; 293 i-cache-sets = <192>; 294 next-level-cache = <&cluster7_l2>; 295 cpu-idle-states = <&cpu_pw15>; 296 #cooling-cells = <2>; 297 }; 298 299 cluster0_l2: l2-cache0 { 300 compatible = "cache"; 301 cache-size = <0x100000>; 302 cache-line-size = <64>; 303 cache-sets = <1024>; 304 cache-level = <2>; 305 }; 306 307 cluster1_l2: l2-cache1 { 308 compatible = "cache"; 309 cache-size = <0x100000>; 310 cache-line-size = <64>; 311 cache-sets = <1024>; 312 cache-level = <2>; 313 }; 314 315 cluster2_l2: l2-cache2 { 316 compatible = "cache"; 317 cache-size = <0x100000>; 318 cache-line-size = <64>; 319 cache-sets = <1024>; 320 cache-level = <2>; 321 }; 322 323 cluster3_l2: l2-cache3 { 324 compatible = "cache"; 325 cache-size = <0x100000>; 326 cache-line-size = <64>; 327 cache-sets = <1024>; 328 cache-level = <2>; 329 }; 330 331 cluster4_l2: l2-cache4 { 332 compatible = "cache"; 333 cache-size = <0x100000>; 334 cache-line-size = <64>; 335 cache-sets = <1024>; 336 cache-level = <2>; 337 }; 338 339 cluster5_l2: l2-cache5 { 340 compatible = "cache"; 341 cache-size = <0x100000>; 342 cache-line-size = <64>; 343 cache-sets = <1024>; 344 cache-level = <2>; 345 }; 346 347 cluster6_l2: l2-cache6 { 348 compatible = "cache"; 349 cache-size = <0x100000>; 350 cache-line-size = <64>; 351 cache-sets = <1024>; 352 cache-level = <2>; 353 }; 354 355 cluster7_l2: l2-cache7 { 356 compatible = "cache"; 357 cache-size = <0x100000>; 358 cache-line-size = <64>; 359 cache-sets = <1024>; 360 cache-level = <2>; 361 }; 362 363 cpu_pw15: cpu-pw15 { 364 compatible = "arm,idle-state"; 365 idle-state-name = "PW15"; 366 arm,psci-suspend-param = <0x0>; 367 entry-latency-us = <2000>; 368 exit-latency-us = <2000>; 369 min-residency-us = <6000>; 370 }; 371 }; 372 373 gic: interrupt-controller@6000000 { 374 compatible = "arm,gic-v3"; 375 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist 376 <0x0 0x06200000 0 0x200000>, // GICR (RD_base + 377 // SGI_base) 378 <0x0 0x0c0c0000 0 0x2000>, // GICC 379 <0x0 0x0c0d0000 0 0x1000>, // GICH 380 <0x0 0x0c0e0000 0 0x20000>; // GICV 381 #interrupt-cells = <3>; 382 #address-cells = <2>; 383 #size-cells = <2>; 384 ranges; 385 interrupt-controller; 386 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 387 388 its: gic-its@6020000 { 389 compatible = "arm,gic-v3-its"; 390 msi-controller; 391 reg = <0x0 0x6020000 0 0x20000>; 392 }; 393 }; 394 395 timer { 396 compatible = "arm,armv8-timer"; 397 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 401 }; 402 403 pmu { 404 compatible = "arm,cortex-a72-pmu"; 405 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 406 }; 407 408 psci { 409 compatible = "arm,psci-0.2"; 410 method = "smc"; 411 }; 412 413 memory@80000000 { 414 // DRAM space - 1, size : 2 GB DRAM 415 device_type = "memory"; 416 reg = <0x00000000 0x80000000 0 0x80000000>; 417 }; 418 419 ddr1: memory-controller@1080000 { 420 compatible = "fsl,qoriq-memory-controller"; 421 reg = <0x0 0x1080000 0x0 0x1000>; 422 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 423 little-endian; 424 }; 425 426 ddr2: memory-controller@1090000 { 427 compatible = "fsl,qoriq-memory-controller"; 428 reg = <0x0 0x1090000 0x0 0x1000>; 429 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 430 little-endian; 431 }; 432 433 // One clock unit-sysclk node which bootloader require during DT fix-up 434 sysclk: sysclk { 435 compatible = "fixed-clock"; 436 #clock-cells = <0>; 437 clock-frequency = <100000000>; // fixed up by bootloader 438 clock-output-names = "sysclk"; 439 }; 440 441 thermal-zones { 442 core_thermal1: core-thermal1 { 443 polling-delay-passive = <1000>; 444 polling-delay = <5000>; 445 thermal-sensors = <&tmu 0>; 446 447 trips { 448 core_cluster_alert: core-cluster-alert { 449 temperature = <85000>; 450 hysteresis = <2000>; 451 type = "passive"; 452 }; 453 454 core_cluster_crit: core-cluster-crit { 455 temperature = <95000>; 456 hysteresis = <2000>; 457 type = "critical"; 458 }; 459 }; 460 461 }; 462 }; 463 464 soc { 465 compatible = "simple-bus"; 466 #address-cells = <2>; 467 #size-cells = <2>; 468 ranges; 469 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 470 471 crypto: crypto@8000000 { 472 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 473 fsl,sec-era = <10>; 474 #address-cells = <1>; 475 #size-cells = <1>; 476 ranges = <0x0 0x00 0x8000000 0x100000>; 477 reg = <0x00 0x8000000 0x0 0x100000>; 478 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 479 dma-coherent; 480 status = "disabled"; 481 482 sec_jr0: jr@10000 { 483 compatible = "fsl,sec-v5.0-job-ring", 484 "fsl,sec-v4.0-job-ring"; 485 reg = <0x10000 0x10000>; 486 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 487 status = "okay"; secure-status = "disabled"; /* NS-only */ 488 }; 489 490 sec_jr1: jr@20000 { 491 compatible = "fsl,sec-v5.0-job-ring", 492 "fsl,sec-v4.0-job-ring"; 493 reg = <0x20000 0x10000>; 494 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 495 status = "okay"; secure-status = "disabled"; /* NS-only */ 496 }; 497 498 sec_jr2: jr@30000 { 499 compatible = "fsl,sec-v5.0-job-ring", 500 "fsl,sec-v4.0-job-ring"; 501 reg = <0x30000 0x10000>; 502 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 503 status = "disabled"; secure-status = "okay"; /* S-only */ 504 }; 505 506 sec_jr3: jr@40000 { 507 compatible = "fsl,sec-v5.0-job-ring", 508 "fsl,sec-v4.0-job-ring"; 509 reg = <0x40000 0x10000>; 510 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 511 status = "okay"; secure-status = "disabled"; /* workaround for ATF */ 512 }; 513 }; 514 515 clockgen: clock-controller@1300000 { 516 compatible = "fsl,lx2160a-clockgen"; 517 reg = <0 0x1300000 0 0xa0000>; 518 #clock-cells = <2>; 519 clocks = <&sysclk>; 520 }; 521 522 dcfg: syscon@1e00000 { 523 compatible = "fsl,lx2160a-dcfg", "syscon"; 524 reg = <0x0 0x1e00000 0x0 0x10000>; 525 little-endian; 526 }; 527 528 sfp: sfp@1e80000 { 529 compatible = "fsl,lx2160a-sfp"; 530 reg = <0x0 0x1e80000 0x0 0x1000>; 531 }; 532 533 sec_mon: sec-mon@1e90000 { 534 compatible = "fsl,lx2160a-sec-mon"; 535 reg = <0x0 0x1e90000 0x0 0x1000>; 536 status = "disabled"; 537 secure-status = "okay"; 538 }; 539 540 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */ 541 emdio1: mdio@8b96000 { 542 compatible = "fsl,fman-memac-mdio"; 543 reg = <0x0 0x8b96000 0x0 0x1000>; 544 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 little-endian; /* force the driver in LE mode */ 548 status = "disabled"; 549 }; 550 551 /* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */ 552 emdio2: mdio@8b97000 { 553 compatible = "fsl,fman-memac-mdio"; 554 reg = <0x0 0x8b97000 0x0 0x1000>; 555 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 little-endian; /* force the driver in LE mode */ 559 status = "disabled"; 560 }; 561 562 i2c0: i2c@2000000 { 563 compatible = "fsl,vf610-i2c"; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 reg = <0x0 0x2000000 0x0 0x10000>; 567 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 568 clock-names = "i2c"; 569 clocks = <&clockgen 4 15>; 570 scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; 571 status = "disabled"; 572 }; 573 574 i2c1: i2c@2010000 { 575 compatible = "fsl,vf610-i2c"; 576 #address-cells = <1>; 577 #size-cells = <0>; 578 reg = <0x0 0x2010000 0x0 0x10000>; 579 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 580 clock-names = "i2c"; 581 clocks = <&clockgen 4 15>; 582 status = "disabled"; 583 }; 584 585 i2c2: i2c@2020000 { 586 compatible = "fsl,vf610-i2c"; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 reg = <0x0 0x2020000 0x0 0x10000>; 590 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 591 clock-names = "i2c"; 592 clocks = <&clockgen 4 15>; 593 status = "disabled"; 594 }; 595 596 i2c3: i2c@2030000 { 597 compatible = "fsl,vf610-i2c"; 598 #address-cells = <1>; 599 #size-cells = <0>; 600 reg = <0x0 0x2030000 0x0 0x10000>; 601 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 602 clock-names = "i2c"; 603 clocks = <&clockgen 4 15>; 604 status = "disabled"; 605 }; 606 607 i2c4: i2c@2040000 { 608 compatible = "fsl,vf610-i2c"; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 reg = <0x0 0x2040000 0x0 0x10000>; 612 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 613 clock-names = "i2c"; 614 clocks = <&clockgen 4 15>; 615 scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; 616 status = "disabled"; 617 }; 618 619 i2c5: i2c@2050000 { 620 compatible = "fsl,vf610-i2c"; 621 #address-cells = <1>; 622 #size-cells = <0>; 623 reg = <0x0 0x2050000 0x0 0x10000>; 624 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 625 clock-names = "i2c"; 626 clocks = <&clockgen 4 15>; 627 status = "disabled"; 628 }; 629 630 i2c6: i2c@2060000 { 631 compatible = "fsl,vf610-i2c"; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 reg = <0x0 0x2060000 0x0 0x10000>; 635 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 636 clock-names = "i2c"; 637 clocks = <&clockgen 4 15>; 638 status = "disabled"; 639 }; 640 641 i2c7: i2c@2070000 { 642 compatible = "fsl,vf610-i2c"; 643 #address-cells = <1>; 644 #size-cells = <0>; 645 reg = <0x0 0x2070000 0x0 0x10000>; 646 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 647 clock-names = "i2c"; 648 clocks = <&clockgen 4 15>; 649 status = "disabled"; 650 }; 651 652 fspi: spi@20c0000 { 653 compatible = "nxp,lx2160a-fspi"; 654 #address-cells = <1>; 655 #size-cells = <0>; 656 reg = <0x0 0x20c0000 0x0 0x10000>, 657 <0x0 0x20000000 0x0 0x10000000>; 658 reg-names = "fspi_base", "fspi_mmap"; 659 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 660 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 661 clock-names = "fspi_en", "fspi"; 662 status = "disabled"; 663 }; 664 665 dspi0: spi@2100000 { 666 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 667 #address-cells = <1>; 668 #size-cells = <0>; 669 reg = <0x0 0x2100000 0x0 0x10000>; 670 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&clockgen 4 7>; 672 clock-names = "dspi"; 673 spi-num-chipselects = <5>; 674 bus-num = <0>; 675 status = "disabled"; 676 }; 677 678 dspi1: spi@2110000 { 679 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 680 #address-cells = <1>; 681 #size-cells = <0>; 682 reg = <0x0 0x2110000 0x0 0x10000>; 683 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 684 clocks = <&clockgen 4 7>; 685 clock-names = "dspi"; 686 spi-num-chipselects = <5>; 687 bus-num = <1>; 688 status = "disabled"; 689 }; 690 691 dspi2: spi@2120000 { 692 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 693 #address-cells = <1>; 694 #size-cells = <0>; 695 reg = <0x0 0x2120000 0x0 0x10000>; 696 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&clockgen 4 7>; 698 clock-names = "dspi"; 699 spi-num-chipselects = <5>; 700 bus-num = <2>; 701 status = "disabled"; 702 }; 703 704 esdhc0: esdhc@2140000 { 705 compatible = "fsl,esdhc"; 706 reg = <0x0 0x2140000 0x0 0x10000>; 707 interrupts = <0 28 0x4>; /* Level high type */ 708 clocks = <&clockgen 4 1>; 709 voltage-ranges = <1800 1800 3300 3300>; 710 sdhci,auto-cmd12; 711 little-endian; 712 bus-width = <4>; 713 status = "disabled"; 714 }; 715 716 esdhc1: esdhc@2150000 { 717 compatible = "fsl,esdhc"; 718 reg = <0x0 0x2150000 0x0 0x10000>; 719 interrupts = <0 63 0x4>; /* Level high type */ 720 clocks = <&clockgen 4 1>; 721 voltage-ranges = <1800 1800 3300 3300>; 722 sdhci,auto-cmd12; 723 broken-cd; 724 little-endian; 725 bus-width = <4>; 726 status = "disabled"; 727 }; 728 729 can0: can@2180000 { 730 compatible = "fsl,lx2160ar1-flexcan"; 731 reg = <0x0 0x2180000 0x0 0x10000>; 732 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&sysclk>, <&clockgen 4 7>; 734 clock-names = "ipg", "per"; 735 status = "disabled"; 736 }; 737 738 can1: can@2190000 { 739 compatible = "fsl,lx2160ar1-flexcan"; 740 reg = <0x0 0x2190000 0x0 0x10000>; 741 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 742 clocks = <&sysclk>, <&clockgen 4 7>; 743 clock-names = "ipg", "per"; 744 status = "disabled"; 745 }; 746 747 tmu: tmu@1f80000 { 748 compatible = "fsl,qoriq-tmu"; 749 reg = <0x0 0x1f80000 0x0 0x10000>; 750 interrupts = <0 23 0x4>; 751 fsl,tmu-range = <0x800000E6 0x8001017D>; 752 fsl,tmu-calibration = 753 /* Calibration data group 1 */ 754 <0x00000000 0x00000035 755 /* Calibration data group 2 */ 756 0x00010001 0x00000154>; 757 little-endian; 758 #thermal-sensor-cells = <1>; 759 }; 760 761 uart0: serial@21c0000 { 762 compatible = "arm,sbsa-uart","arm,pl011"; 763 reg = <0x0 0x21c0000 0x0 0x1000>; 764 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 765 current-speed = <115200>; 766 status = "disabled"; 767 }; 768 769 uart1: serial@21d0000 { 770 compatible = "arm,sbsa-uart","arm,pl011"; 771 reg = <0x0 0x21d0000 0x0 0x1000>; 772 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 773 current-speed = <115200>; 774 status = "disabled"; 775 }; 776 777 uart2: serial@21e0000 { 778 compatible = "arm,sbsa-uart","arm,pl011"; 779 reg = <0x0 0x21e0000 0x0 0x1000>; 780 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 781 current-speed = <115200>; 782 status = "disabled"; 783 }; 784 785 uart3: serial@21f0000 { 786 compatible = "arm,sbsa-uart","arm,pl011"; 787 reg = <0x0 0x21f0000 0x0 0x1000>; 788 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 789 current-speed = <115200>; 790 status = "disabled"; 791 }; 792 793 gpio0: gpio@2300000 { 794 compatible = "fsl,qoriq-gpio"; 795 reg = <0x0 0x2300000 0x0 0x10000>; 796 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 797 gpio-controller; 798 little-endian; 799 #gpio-cells = <2>; 800 interrupt-controller; 801 #interrupt-cells = <2>; 802 }; 803 804 gpio1: gpio@2310000 { 805 compatible = "fsl,qoriq-gpio"; 806 reg = <0x0 0x2310000 0x0 0x10000>; 807 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 808 gpio-controller; 809 little-endian; 810 #gpio-cells = <2>; 811 interrupt-controller; 812 #interrupt-cells = <2>; 813 }; 814 815 gpio2: gpio@2320000 { 816 compatible = "fsl,qoriq-gpio"; 817 reg = <0x0 0x2320000 0x0 0x10000>; 818 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 819 gpio-controller; 820 little-endian; 821 #gpio-cells = <2>; 822 interrupt-controller; 823 #interrupt-cells = <2>; 824 }; 825 826 gpio3: gpio@2330000 { 827 compatible = "fsl,qoriq-gpio"; 828 reg = <0x0 0x2330000 0x0 0x10000>; 829 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 830 gpio-controller; 831 little-endian; 832 #gpio-cells = <2>; 833 interrupt-controller; 834 #interrupt-cells = <2>; 835 }; 836 837 watchdog@23a0000 { 838 compatible = "arm,sbsa-gwdt"; 839 reg = <0x0 0x23a0000 0 0x1000>, 840 <0x0 0x2390000 0 0x1000>; 841 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 842 timeout-sec = <30>; 843 }; 844 845 rcpm: rcpm@1e34040 { 846 compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+"; 847 reg = <0x0 0x1e34040 0x0 0x1c>; 848 #fsl,rcpm-wakeup-cells = <7>; 849 little-endian; 850 }; 851 852 ftm_alarm0: timer@2800000 { 853 compatible = "fsl,lx2160a-ftm-alarm"; 854 reg = <0x0 0x2800000 0x0 0x10000>; 855 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 856 interrupts = <0 44 4>; 857 }; 858 859 usb0: usb@3100000 { 860 compatible = "fsl,lx2160a-dwc3", "snps,dwc3"; 861 reg = <0x0 0x3100000 0x0 0x10000>; 862 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 863 dr_mode = "host"; 864 snps,quirk-frame-length-adjustment = <0x20>; 865 usb3-lpm-capable; 866 snps,dis-u1u2-when-u3-quirk; 867 snps,dis_rxdet_inp3_quirk; 868 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 869 snps,host-vbus-glitches; 870 dma-coherent; 871 status = "disabled"; 872 }; 873 874 usb1: usb@3110000 { 875 compatible = "fsl,lx2160a-dwc3", "snps,dwc3"; 876 reg = <0x0 0x3110000 0x0 0x10000>; 877 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 878 dr_mode = "host"; 879 snps,quirk-frame-length-adjustment = <0x20>; 880 usb3-lpm-capable; 881 snps,dis-u1u2-when-u3-quirk; 882 snps,dis_rxdet_inp3_quirk; 883 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 884 snps,host-vbus-glitches; 885 status = "disabled"; 886 }; 887 888 sata0: sata@3200000 { 889 compatible = "fsl,lx2160a-ahci"; 890 reg = <0x0 0x3200000 0x0 0x10000>, 891 <0x7 0x100520 0x0 0x4>; 892 reg-names = "ahci", "sata-ecc"; 893 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 894 clocks = <&clockgen 4 3>; 895 dma-coherent; 896 status = "disabled"; 897 }; 898 899 sata1: sata@3210000 { 900 compatible = "fsl,lx2160a-ahci"; 901 reg = <0x0 0x3210000 0x0 0x10000>, 902 <0x7 0x100520 0x0 0x4>; 903 reg-names = "ahci", "sata-ecc"; 904 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 905 clocks = <&clockgen 4 3>; 906 dma-coherent; 907 status = "disabled"; 908 }; 909 910 sata2: sata@3220000 { 911 compatible = "fsl,lx2160a-ahci"; 912 reg = <0x0 0x3220000 0x0 0x10000>, 913 <0x7 0x100520 0x0 0x4>; 914 reg-names = "ahci", "sata-ecc"; 915 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 916 clocks = <&clockgen 4 3>; 917 dma-coherent; 918 status = "disabled"; 919 }; 920 921 sata3: sata@3230000 { 922 compatible = "fsl,lx2160a-ahci"; 923 reg = <0x0 0x3230000 0x0 0x10000>, 924 <0x7 0x100520 0x0 0x4>; 925 reg-names = "ahci", "sata-ecc"; 926 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 927 clocks = <&clockgen 4 3>; 928 dma-coherent; 929 status = "disabled"; 930 }; 931 932 pcie@3400000 { 933 compatible = "fsl,lx2160a-pcie"; 934 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 935 0x80 0x00000000 0x0 0x00001000>; /* configuration space */ 936 reg-names = "csr_axi_slave", "config_axi_slave"; 937 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 938 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 939 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 940 interrupt-names = "aer", "pme", "intr"; 941 #address-cells = <3>; 942 #size-cells = <2>; 943 device_type = "pci"; 944 dma-coherent; 945 apio-wins = <8>; 946 ppio-wins = <8>; 947 bus-range = <0x0 0xff>; 948 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 949 msi-parent = <&its>; 950 iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ 951 #interrupt-cells = <1>; 952 interrupt-map-mask = <0 0 0 7>; 953 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 954 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 955 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 956 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 957 status = "disabled"; 958 }; 959 960 pcie_ep@3400000 { 961 compatible = "fsl,lx2160a-pcie-ep"; 962 reg = <0x00 0x03400000 0x0 0x00100000 963 0x80 0x00000000 0x8 0x00000000>; 964 reg-names = "regs", "addr_space"; 965 num-ob-windows = <256>; 966 status = "disabled"; 967 }; 968 969 pcie@3500000 { 970 compatible = "fsl,lx2160a-pcie"; 971 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 972 0x88 0x00000000 0x0 0x00001000>; /* configuration space */ 973 reg-names = "csr_axi_slave", "config_axi_slave"; 974 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 975 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 976 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 977 interrupt-names = "aer", "pme", "intr"; 978 #address-cells = <3>; 979 #size-cells = <2>; 980 device_type = "pci"; 981 dma-coherent; 982 apio-wins = <8>; 983 ppio-wins = <8>; 984 bus-range = <0x0 0xff>; 985 ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 986 msi-parent = <&its>; 987 iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ 988 #interrupt-cells = <1>; 989 interrupt-map-mask = <0 0 0 7>; 990 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 991 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 992 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 993 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 994 status = "disabled"; 995 }; 996 997 pcie_ep@3500000 { 998 compatible = "fsl,lx2160a-pcie-ep"; 999 reg = <0x00 0x03500000 0x0 0x00100000 1000 0x88 0x00000000 0x8 0x00000000>; 1001 reg-names = "regs", "addr_space"; 1002 num-ob-windows = <256>; 1003 status = "disabled"; 1004 }; 1005 1006 pcie@3600000 { 1007 compatible = "fsl,lx2160a-pcie"; 1008 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 1009 0x90 0x00000000 0x0 0x00001000>; /* configuration space */ 1010 reg-names = "csr_axi_slave", "config_axi_slave"; 1011 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1012 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1013 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1014 interrupt-names = "aer", "pme", "intr"; 1015 #address-cells = <3>; 1016 #size-cells = <2>; 1017 device_type = "pci"; 1018 dma-coherent; 1019 apio-wins = <8>; 1020 ppio-wins = <8>; 1021 bus-range = <0x0 0xff>; 1022 ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1023 msi-parent = <&its>; 1024 iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ 1025 #interrupt-cells = <1>; 1026 interrupt-map-mask = <0 0 0 7>; 1027 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1028 <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1029 <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1030 <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1031 status = "disabled"; 1032 }; 1033 1034 pcie_ep@3600000 { 1035 compatible = "fsl,lx2160a-pcie-ep"; 1036 reg = <0x00 0x03600000 0x0 0x00100000 1037 0x90 0x00000000 0x8 0x00000000>; 1038 reg-names = "regs", "addr_space"; 1039 num-ob-windows = <256>; 1040 max-functions = <2>; 1041 status = "disabled"; 1042 }; 1043 1044 pcie@3700000 { 1045 compatible = "fsl,lx2160a-pcie"; 1046 reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ 1047 0x98 0x00000000 0x0 0x00001000>; /* configuration space */ 1048 reg-names = "csr_axi_slave", "config_axi_slave"; 1049 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1050 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1051 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1052 interrupt-names = "aer", "pme", "intr"; 1053 #address-cells = <3>; 1054 #size-cells = <2>; 1055 device_type = "pci"; 1056 dma-coherent; 1057 apio-wins = <8>; 1058 ppio-wins = <8>; 1059 bus-range = <0x0 0xff>; 1060 ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1061 msi-parent = <&its>; 1062 iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ 1063 #interrupt-cells = <1>; 1064 interrupt-map-mask = <0 0 0 7>; 1065 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1066 <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1067 <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1068 <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1069 status = "disabled"; 1070 }; 1071 1072 pcie_ep@3700000 { 1073 compatible = "fsl,lx2160a-pcie-ep"; 1074 reg = <0x00 0x03700000 0x0 0x00100000 1075 0x98 0x00000000 0x8 0x00000000>; 1076 reg-names = "regs", "addr_space"; 1077 num-ob-windows = <256>; 1078 status = "disabled"; 1079 }; 1080 1081 pcie@3800000 { 1082 compatible = "fsl,lx2160a-pcie"; 1083 reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ 1084 0xa0 0x00000000 0x0 0x00001000>; /* configuration space */ 1085 reg-names = "csr_axi_slave", "config_axi_slave"; 1086 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1087 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1088 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1089 interrupt-names = "aer", "pme", "intr"; 1090 #address-cells = <3>; 1091 #size-cells = <2>; 1092 device_type = "pci"; 1093 dma-coherent; 1094 apio-wins = <8>; 1095 ppio-wins = <8>; 1096 bus-range = <0x0 0xff>; 1097 ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1098 msi-parent = <&its>; 1099 iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ 1100 #interrupt-cells = <1>; 1101 interrupt-map-mask = <0 0 0 7>; 1102 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1103 <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1104 <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1105 <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1106 status = "disabled"; 1107 }; 1108 1109 pcie_ep@3800000 { 1110 compatible = "fsl,lx2160a-pcie-ep"; 1111 reg = <0x00 0x03800000 0x0 0x00100000 1112 0xa0 0x00000000 0x8 0x00000000>; 1113 reg-names = "regs", "addr_space"; 1114 num-ob-windows = <256>; 1115 max-functions = <2>; 1116 status = "disabled"; 1117 }; 1118 1119 pcie@3900000 { 1120 compatible = "fsl,lx2160a-pcie"; 1121 reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ 1122 0xa8 0x00000000 0x0 0x00001000>; /* configuration space */ 1123 reg-names = "csr_axi_slave", "config_axi_slave"; 1124 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1125 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1126 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1127 interrupt-names = "aer", "pme", "intr"; 1128 #address-cells = <3>; 1129 #size-cells = <2>; 1130 device_type = "pci"; 1131 dma-coherent; 1132 apio-wins = <8>; 1133 ppio-wins = <8>; 1134 bus-range = <0x0 0xff>; 1135 ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1136 msi-parent = <&its>; 1137 iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ 1138 #interrupt-cells = <1>; 1139 interrupt-map-mask = <0 0 0 7>; 1140 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1141 <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1142 <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1143 <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1144 status = "disabled"; 1145 }; 1146 1147 pcie_ep@3900000 { 1148 compatible = "fsl,lx2160a-pcie-ep"; 1149 reg = <0x00 0x03900000 0x0 0x00100000 1150 0xa8 0x00000000 0x8 0x00000000>; 1151 reg-names = "regs", "addr_space"; 1152 num-ob-windows = <256>; 1153 status = "disabled"; 1154 }; 1155 1156 smmu: iommu@5000000 { 1157 compatible = "arm,mmu-500"; 1158 reg = <0 0x5000000 0 0x800000>; 1159 #iommu-cells = <1>; 1160 #global-interrupts = <14>; 1161 // global secure fault 1162 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1163 // combined secure 1164 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1165 // global non-secure fault 1166 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1167 // combined non-secure 1168 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1169 // performance counter interrupts 0-9 1170 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1180 // per context interrupt, 64 interrupts 1181 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1245 dma-coherent; 1246 }; 1247 1248 console@8340020 { 1249 compatible = "fsl,dpaa2-console"; 1250 reg = <0x00000000 0x08340020 0 0x2>; 1251 }; 1252 1253 ptp-timer@8b95000 { 1254 compatible = "fsl,dpaa2-ptp"; 1255 reg = <0x0 0x8b95000 0x0 0x100>; 1256 clocks = <&clockgen 4 1>; 1257 little-endian; 1258 fsl,extts-fifo; 1259 }; 1260 1261 fsl_mc: fsl-mc@80c000000 { 1262 compatible = "fsl,qoriq-mc"; 1263 reg = <0x00000008 0x0c000000 0 0x40>, 1264 <0x00000000 0x08340000 0 0x40000>; 1265 msi-parent = <&its>; 1266 /* iommu-map property is fixed up by u-boot */ 1267 iommu-map = <0 &smmu 0 0>; 1268 dma-coherent; 1269 #address-cells = <3>; 1270 #size-cells = <1>; 1271 1272 /* 1273 * Region type 0x0 - MC portals 1274 * Region type 0x1 - QBMAN portals 1275 */ 1276 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 1277 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 1278 1279 /* 1280 * Define the maximum number of MACs present on the SoC. 1281 */ 1282 dpmacs { 1283 #address-cells = <1>; 1284 #size-cells = <0>; 1285 1286 dpmac1: dpmac@1 { 1287 compatible = "fsl,qoriq-mc-dpmac"; 1288 reg = <0x1>; 1289 }; 1290 1291 dpmac2: dpmac@2 { 1292 compatible = "fsl,qoriq-mc-dpmac"; 1293 reg = <0x2>; 1294 }; 1295 1296 dpmac3: dpmac@3 { 1297 compatible = "fsl,qoriq-mc-dpmac"; 1298 reg = <0x3>; 1299 }; 1300 1301 dpmac4: dpmac@4 { 1302 compatible = "fsl,qoriq-mc-dpmac"; 1303 reg = <0x4>; 1304 }; 1305 1306 dpmac5: dpmac@5 { 1307 compatible = "fsl,qoriq-mc-dpmac"; 1308 reg = <0x5>; 1309 }; 1310 1311 dpmac6: dpmac@6 { 1312 compatible = "fsl,qoriq-mc-dpmac"; 1313 reg = <0x6>; 1314 }; 1315 1316 dpmac7: dpmac@7 { 1317 compatible = "fsl,qoriq-mc-dpmac"; 1318 reg = <0x7>; 1319 }; 1320 1321 dpmac8: dpmac@8 { 1322 compatible = "fsl,qoriq-mc-dpmac"; 1323 reg = <0x8>; 1324 }; 1325 1326 dpmac9: dpmac@9 { 1327 compatible = "fsl,qoriq-mc-dpmac"; 1328 reg = <0x9>; 1329 }; 1330 1331 dpmac10: dpmac@a { 1332 compatible = "fsl,qoriq-mc-dpmac"; 1333 reg = <0xa>; 1334 }; 1335 1336 dpmac11: dpmac@b { 1337 compatible = "fsl,qoriq-mc-dpmac"; 1338 reg = <0xb>; 1339 }; 1340 1341 dpmac12: dpmac@c { 1342 compatible = "fsl,qoriq-mc-dpmac"; 1343 reg = <0xc>; 1344 }; 1345 1346 dpmac13: dpmac@d { 1347 compatible = "fsl,qoriq-mc-dpmac"; 1348 reg = <0xd>; 1349 }; 1350 1351 dpmac14: dpmac@e { 1352 compatible = "fsl,qoriq-mc-dpmac"; 1353 reg = <0xe>; 1354 }; 1355 1356 dpmac15: dpmac@f { 1357 compatible = "fsl,qoriq-mc-dpmac"; 1358 reg = <0xf>; 1359 }; 1360 1361 dpmac16: dpmac@10 { 1362 compatible = "fsl,qoriq-mc-dpmac"; 1363 reg = <0x10>; 1364 }; 1365 1366 dpmac17: dpmac@11 { 1367 compatible = "fsl,qoriq-mc-dpmac"; 1368 reg = <0x11>; 1369 }; 1370 1371 dpmac18: dpmac@12 { 1372 compatible = "fsl,qoriq-mc-dpmac"; 1373 reg = <0x12>; 1374 }; 1375 }; 1376 }; 1377 }; 1378 1379 firmware { 1380 optee { 1381 compatible = "linaro,optee-tz"; 1382 method = "smc"; 1383 }; 1384 }; 1385}; 1386