1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 //
3 // cs35l45-tables.c -- CS35L45 ALSA SoC audio driver
4 //
5 // Copyright 2019-2022 Cirrus Logic, Inc.
6 //
7 // Author: James Schulman <james.schulman@cirrus.com>
8
9 #include <linux/module.h>
10 #include <linux/regmap.h>
11
12 #include "cs35l45.h"
13
14 static const struct reg_sequence cs35l45_patch[] = {
15 { 0x00000040, 0x00000055 },
16 { 0x00000040, 0x000000AA },
17 { 0x00000044, 0x00000055 },
18 { 0x00000044, 0x000000AA },
19 { 0x00006480, 0x0830500A },
20 { 0x00007C60, 0x1000850B },
21 { CS35L45_BOOST_OV_CFG, 0x007000D0 },
22 { CS35L45_LDPM_CONFIG, 0x0001B636 },
23 { 0x00002C08, 0x00000009 },
24 { 0x00006850, 0x0A30FFC4 },
25 { 0x00003820, 0x00040100 },
26 { 0x00003824, 0x00000000 },
27 { 0x00007CFC, 0x62870004 },
28 { 0x00007C60, 0x1001850B },
29 { 0x00000040, 0x00000000 },
30 { 0x00000044, 0x00000000 },
31 { CS35L45_BOOST_CCM_CFG, 0xF0000003 },
32 { CS35L45_BOOST_DCM_CFG, 0x08710220 },
33 { CS35L45_ERROR_RELEASE, 0x00200000 },
34 };
35
cs35l45_apply_patch(struct cs35l45_private * cs35l45)36 int cs35l45_apply_patch(struct cs35l45_private *cs35l45)
37 {
38 return regmap_register_patch(cs35l45->regmap, cs35l45_patch,
39 ARRAY_SIZE(cs35l45_patch));
40 }
41 EXPORT_SYMBOL_NS_GPL(cs35l45_apply_patch, SND_SOC_CS35L45);
42
43 static const struct reg_default cs35l45_defaults[] = {
44 { CS35L45_BLOCK_ENABLES, 0x00003323 },
45 { CS35L45_BLOCK_ENABLES2, 0x00000010 },
46 { CS35L45_REFCLK_INPUT, 0x00000510 },
47 { CS35L45_GLOBAL_SAMPLE_RATE, 0x00000003 },
48 { CS35L45_ASP_ENABLES1, 0x00000000 },
49 { CS35L45_ASP_CONTROL1, 0x00000028 },
50 { CS35L45_ASP_CONTROL2, 0x18180200 },
51 { CS35L45_ASP_CONTROL3, 0x00000002 },
52 { CS35L45_ASP_FRAME_CONTROL1, 0x03020100 },
53 { CS35L45_ASP_FRAME_CONTROL2, 0x00000004 },
54 { CS35L45_ASP_FRAME_CONTROL5, 0x00000100 },
55 { CS35L45_ASP_DATA_CONTROL1, 0x00000018 },
56 { CS35L45_ASP_DATA_CONTROL5, 0x00000018 },
57 { CS35L45_DACPCM1_INPUT, 0x00000008 },
58 { CS35L45_ASPTX1_INPUT, 0x00000018 },
59 { CS35L45_ASPTX2_INPUT, 0x00000019 },
60 { CS35L45_ASPTX3_INPUT, 0x00000020 },
61 { CS35L45_ASPTX4_INPUT, 0x00000028 },
62 { CS35L45_ASPTX5_INPUT, 0x00000048 },
63 { CS35L45_AMP_PCM_CONTROL, 0x00100000 },
64 };
65
cs35l45_readable_reg(struct device * dev,unsigned int reg)66 static bool cs35l45_readable_reg(struct device *dev, unsigned int reg)
67 {
68 switch (reg) {
69 case CS35L45_DEVID ... CS35L45_OTPID:
70 case CS35L45_SFT_RESET:
71 case CS35L45_GLOBAL_ENABLES:
72 case CS35L45_BLOCK_ENABLES:
73 case CS35L45_BLOCK_ENABLES2:
74 case CS35L45_ERROR_RELEASE:
75 case CS35L45_REFCLK_INPUT:
76 case CS35L45_GLOBAL_SAMPLE_RATE:
77 case CS35L45_ASP_ENABLES1:
78 case CS35L45_ASP_CONTROL1:
79 case CS35L45_ASP_CONTROL2:
80 case CS35L45_ASP_CONTROL3:
81 case CS35L45_ASP_FRAME_CONTROL1:
82 case CS35L45_ASP_FRAME_CONTROL2:
83 case CS35L45_ASP_FRAME_CONTROL5:
84 case CS35L45_ASP_DATA_CONTROL1:
85 case CS35L45_ASP_DATA_CONTROL5:
86 case CS35L45_DACPCM1_INPUT:
87 case CS35L45_ASPTX1_INPUT:
88 case CS35L45_ASPTX2_INPUT:
89 case CS35L45_ASPTX3_INPUT:
90 case CS35L45_ASPTX4_INPUT:
91 case CS35L45_ASPTX5_INPUT:
92 case CS35L45_AMP_PCM_CONTROL:
93 case CS35L45_AMP_PCM_HPF_TST:
94 case CS35L45_IRQ1_EINT_4:
95 return true;
96 default:
97 return false;
98 }
99 }
100
cs35l45_volatile_reg(struct device * dev,unsigned int reg)101 static bool cs35l45_volatile_reg(struct device *dev, unsigned int reg)
102 {
103 switch (reg) {
104 case CS35L45_DEVID ... CS35L45_OTPID:
105 case CS35L45_SFT_RESET:
106 case CS35L45_GLOBAL_ENABLES:
107 case CS35L45_ERROR_RELEASE:
108 case CS35L45_AMP_PCM_HPF_TST: /* not cachable */
109 case CS35L45_IRQ1_EINT_4:
110 return true;
111 default:
112 return false;
113 }
114 }
115
116 const struct regmap_config cs35l45_i2c_regmap = {
117 .reg_bits = 32,
118 .val_bits = 32,
119 .reg_stride = 4,
120 .reg_format_endian = REGMAP_ENDIAN_BIG,
121 .val_format_endian = REGMAP_ENDIAN_BIG,
122 .max_register = CS35L45_LASTREG,
123 .reg_defaults = cs35l45_defaults,
124 .num_reg_defaults = ARRAY_SIZE(cs35l45_defaults),
125 .volatile_reg = cs35l45_volatile_reg,
126 .readable_reg = cs35l45_readable_reg,
127 .cache_type = REGCACHE_RBTREE,
128 };
129 EXPORT_SYMBOL_NS_GPL(cs35l45_i2c_regmap, SND_SOC_CS35L45);
130
131 const struct regmap_config cs35l45_spi_regmap = {
132 .reg_bits = 32,
133 .val_bits = 32,
134 .pad_bits = 16,
135 .reg_stride = 4,
136 .reg_format_endian = REGMAP_ENDIAN_BIG,
137 .val_format_endian = REGMAP_ENDIAN_BIG,
138 .max_register = CS35L45_LASTREG,
139 .reg_defaults = cs35l45_defaults,
140 .num_reg_defaults = ARRAY_SIZE(cs35l45_defaults),
141 .volatile_reg = cs35l45_volatile_reg,
142 .readable_reg = cs35l45_readable_reg,
143 .cache_type = REGCACHE_RBTREE,
144 };
145 EXPORT_SYMBOL_NS_GPL(cs35l45_spi_regmap, SND_SOC_CS35L45);
146
147 static const struct {
148 u8 cfg_id;
149 u32 freq;
150 } cs35l45_pll_refclk_freq[] = {
151 { 0x0C, 128000 },
152 { 0x0F, 256000 },
153 { 0x11, 384000 },
154 { 0x12, 512000 },
155 { 0x15, 768000 },
156 { 0x17, 1024000 },
157 { 0x19, 1411200 },
158 { 0x1B, 1536000 },
159 { 0x1C, 2116800 },
160 { 0x1D, 2048000 },
161 { 0x1E, 2304000 },
162 { 0x1F, 2822400 },
163 { 0x21, 3072000 },
164 { 0x23, 4233600 },
165 { 0x24, 4096000 },
166 { 0x25, 4608000 },
167 { 0x26, 5644800 },
168 { 0x27, 6000000 },
169 { 0x28, 6144000 },
170 { 0x29, 6350400 },
171 { 0x2A, 6912000 },
172 { 0x2D, 7526400 },
173 { 0x2E, 8467200 },
174 { 0x2F, 8192000 },
175 { 0x30, 9216000 },
176 { 0x31, 11289600 },
177 { 0x33, 12288000 },
178 { 0x37, 16934400 },
179 { 0x38, 18432000 },
180 { 0x39, 22579200 },
181 { 0x3B, 24576000 },
182 };
183
cs35l45_get_clk_freq_id(unsigned int freq)184 unsigned int cs35l45_get_clk_freq_id(unsigned int freq)
185 {
186 int i;
187
188 if (freq == 0)
189 return -EINVAL;
190
191 for (i = 0; i < ARRAY_SIZE(cs35l45_pll_refclk_freq); ++i) {
192 if (cs35l45_pll_refclk_freq[i].freq == freq)
193 return cs35l45_pll_refclk_freq[i].cfg_id;
194 }
195
196 return -EINVAL;
197 }
198 EXPORT_SYMBOL_NS_GPL(cs35l45_get_clk_freq_id, SND_SOC_CS35L45);
199