1 /*
2 * Copyright 2013-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25 #include "dm_services.h"
26 #include "include/gpio_types.h"
27 #include "../hw_factory.h"
28
29
30 #include "../hw_gpio.h"
31 #include "../hw_ddc.h"
32 #include "../hw_hpd.h"
33 #include "../hw_generic.h"
34
35 #include "hw_factory_dcn20.h"
36
37
38 #include "dcn/dcn_2_0_0_offset.h"
39 #include "dcn/dcn_2_0_0_sh_mask.h"
40 #include "navi10_ip_offset.h"
41
42
43 #include "reg_helper.h"
44 #include "../hpd_regs.h"
45 /* begin *********************
46 * macros to expend register list macro defined in HW object header file */
47
48 /* DCN */
49 #define block HPD
50 #define reg_num 0
51
52 #undef BASE_INNER
53 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
54
55 #define BASE(seg) BASE_INNER(seg)
56
57
58
59 #define REG(reg_name)\
60 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
61
62 #define SF_HPD(reg_name, field_name, post_fix)\
63 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
64
65 #define REGI(reg_name, block, id)\
66 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
67 mm ## block ## id ## _ ## reg_name
68
69 #define SF(reg_name, field_name, post_fix)\
70 .field_name = reg_name ## __ ## field_name ## post_fix
71
72 /* macros to expend register list macro defined in HW object header file
73 * end *********************/
74
75
76
77 #define hpd_regs(id) \
78 {\
79 HPD_REG_LIST(id)\
80 }
81
82 static const struct hpd_registers hpd_regs[] = {
83 hpd_regs(0),
84 hpd_regs(1),
85 hpd_regs(2),
86 hpd_regs(3),
87 hpd_regs(4),
88 hpd_regs(5),
89 };
90
91 static const struct hpd_sh_mask hpd_shift = {
92 HPD_MASK_SH_LIST(__SHIFT)
93 };
94
95 static const struct hpd_sh_mask hpd_mask = {
96 HPD_MASK_SH_LIST(_MASK)
97 };
98
99 #include "../ddc_regs.h"
100
101 /* set field name */
102 #define SF_DDC(reg_name, field_name, post_fix)\
103 .field_name = reg_name ## __ ## field_name ## post_fix
104
105 static const struct ddc_registers ddc_data_regs_dcn[] = {
106 ddc_data_regs_dcn2(1),
107 ddc_data_regs_dcn2(2),
108 ddc_data_regs_dcn2(3),
109 ddc_data_regs_dcn2(4),
110 ddc_data_regs_dcn2(5),
111 ddc_data_regs_dcn2(6),
112 {
113 DDC_GPIO_VGA_REG_LIST(DATA),
114 .ddc_setup = 0,
115 .phy_aux_cntl = 0,
116 .dc_gpio_aux_ctrl_5 = 0
117 }
118 };
119
120 static const struct ddc_registers ddc_clk_regs_dcn[] = {
121 ddc_clk_regs_dcn2(1),
122 ddc_clk_regs_dcn2(2),
123 ddc_clk_regs_dcn2(3),
124 ddc_clk_regs_dcn2(4),
125 ddc_clk_regs_dcn2(5),
126 ddc_clk_regs_dcn2(6),
127 {
128 DDC_GPIO_VGA_REG_LIST(CLK),
129 .ddc_setup = 0,
130 .phy_aux_cntl = 0,
131 .dc_gpio_aux_ctrl_5 = 0
132 }
133 };
134
135 static const struct ddc_sh_mask ddc_shift[] = {
136 DDC_MASK_SH_LIST_DCN2(__SHIFT, 1),
137 DDC_MASK_SH_LIST_DCN2(__SHIFT, 2),
138 DDC_MASK_SH_LIST_DCN2(__SHIFT, 3),
139 DDC_MASK_SH_LIST_DCN2(__SHIFT, 4),
140 DDC_MASK_SH_LIST_DCN2(__SHIFT, 5),
141 DDC_MASK_SH_LIST_DCN2(__SHIFT, 6),
142 DDC_MASK_SH_LIST_DCN2_VGA(__SHIFT)
143 };
144
145 static const struct ddc_sh_mask ddc_mask[] = {
146 DDC_MASK_SH_LIST_DCN2(_MASK, 1),
147 DDC_MASK_SH_LIST_DCN2(_MASK, 2),
148 DDC_MASK_SH_LIST_DCN2(_MASK, 3),
149 DDC_MASK_SH_LIST_DCN2(_MASK, 4),
150 DDC_MASK_SH_LIST_DCN2(_MASK, 5),
151 DDC_MASK_SH_LIST_DCN2(_MASK, 6),
152 DDC_MASK_SH_LIST_DCN2_VGA(_MASK)
153 };
154
155 #include "../generic_regs.h"
156
157 /* set field name */
158 #define SF_GENERIC(reg_name, field_name, post_fix)\
159 .field_name = reg_name ## __ ## field_name ## post_fix
160
161 #define generic_regs(id) \
162 {\
163 GENERIC_REG_LIST(id)\
164 }
165
166 static const struct generic_registers generic_regs[] = {
167 generic_regs(A),
168 generic_regs(B),
169 };
170
171 static const struct generic_sh_mask generic_shift[] = {
172 GENERIC_MASK_SH_LIST(__SHIFT, A),
173 GENERIC_MASK_SH_LIST(__SHIFT, B),
174 };
175
176 static const struct generic_sh_mask generic_mask[] = {
177 GENERIC_MASK_SH_LIST(_MASK, A),
178 GENERIC_MASK_SH_LIST(_MASK, B),
179 };
180
define_ddc_registers(struct hw_gpio_pin * pin,uint32_t en)181 static void define_ddc_registers(
182 struct hw_gpio_pin *pin,
183 uint32_t en)
184 {
185 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
186
187 switch (pin->id) {
188 case GPIO_ID_DDC_DATA:
189 ddc->regs = &ddc_data_regs_dcn[en];
190 ddc->base.regs = &ddc_data_regs_dcn[en].gpio;
191 break;
192 case GPIO_ID_DDC_CLOCK:
193 ddc->regs = &ddc_clk_regs_dcn[en];
194 ddc->base.regs = &ddc_clk_regs_dcn[en].gpio;
195 break;
196 default:
197 ASSERT_CRITICAL(false);
198 return;
199 }
200
201 ddc->shifts = &ddc_shift[en];
202 ddc->masks = &ddc_mask[en];
203
204 }
205
define_hpd_registers(struct hw_gpio_pin * pin,uint32_t en)206 static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
207 {
208 struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
209
210 hpd->regs = &hpd_regs[en];
211 hpd->shifts = &hpd_shift;
212 hpd->masks = &hpd_mask;
213 hpd->base.regs = &hpd_regs[en].gpio;
214 }
215
define_generic_registers(struct hw_gpio_pin * pin,uint32_t en)216 static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)
217 {
218 struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin);
219
220 generic->regs = &generic_regs[en];
221 generic->shifts = &generic_shift[en];
222 generic->masks = &generic_mask[en];
223 generic->base.regs = &generic_regs[en].gpio;
224 }
225
226 /* function table */
227 static const struct hw_factory_funcs funcs = {
228 .init_ddc_data = dal_hw_ddc_init,
229 .init_generic = dal_hw_generic_init,
230 .init_hpd = dal_hw_hpd_init,
231 .get_ddc_pin = dal_hw_ddc_get_pin,
232 .get_hpd_pin = dal_hw_hpd_get_pin,
233 .get_generic_pin = dal_hw_generic_get_pin,
234 .define_hpd_registers = define_hpd_registers,
235 .define_ddc_registers = define_ddc_registers,
236 .define_generic_registers = define_generic_registers,
237 };
238 /*
239 * dal_hw_factory_dcn10_init
240 *
241 * @brief
242 * Initialize HW factory function pointers and pin info
243 *
244 * @param
245 * struct hw_factory *factory - [out] struct of function pointers
246 */
dal_hw_factory_dcn20_init(struct hw_factory * factory)247 void dal_hw_factory_dcn20_init(struct hw_factory *factory)
248 {
249 /*TODO check ASIC CAPs*/
250 factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
251 factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
252 factory->number_of_pins[GPIO_ID_GENERIC] = 4;
253 factory->number_of_pins[GPIO_ID_HPD] = 6;
254 factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28;
255 factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
256 factory->number_of_pins[GPIO_ID_SYNC] = 0;
257 factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/
258
259 factory->funcs = &funcs;
260 }
261
262