1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Support for Medifield PNW Camera Imaging ISP subsystem.
4 *
5 * Copyright (c) 2010-2017 Intel Corporation. All Rights Reserved.
6 *
7 * Copyright (c) 2010 Silicon Hive www.siliconhive.com.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License version
11 * 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 *
19 */
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/pm_domain.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/pm_qos.h>
25 #include <linux/timer.h>
26 #include <linux/delay.h>
27 #include <linux/dmi.h>
28 #include <linux/interrupt.h>
29 #include <linux/bits.h>
30
31 #include <asm/iosf_mbi.h>
32
33 #include "../../include/linux/atomisp_gmin_platform.h"
34
35 #include "atomisp_cmd.h"
36 #include "atomisp_common.h"
37 #include "atomisp_fops.h"
38 #include "atomisp_ioctl.h"
39 #include "atomisp_internal.h"
40 #include "atomisp-regs.h"
41 #include "atomisp_dfs_tables.h"
42 #include "atomisp_drvfs.h"
43 #include "hmm/hmm.h"
44 #include "atomisp_trace_event.h"
45
46 #include "sh_css_firmware.h"
47
48 #include "device_access.h"
49
50 /* Timeouts to wait for all subdevs to be registered */
51 #define SUBDEV_WAIT_TIMEOUT 50 /* ms */
52 #define SUBDEV_WAIT_TIMEOUT_MAX_COUNT 40 /* up to 2 seconds */
53
54 /* G-Min addition: pull this in from intel_mid_pm.h */
55 #define CSTATE_EXIT_LATENCY_C1 1
56
57 static uint skip_fwload;
58 module_param(skip_fwload, uint, 0644);
59 MODULE_PARM_DESC(skip_fwload, "Skip atomisp firmware load");
60
61 /* cross componnet debug message flag */
62 int dbg_level;
63 module_param(dbg_level, int, 0644);
64 MODULE_PARM_DESC(dbg_level, "debug message level (default:0)");
65
66 /* log function switch */
67 int dbg_func = 2;
68 module_param(dbg_func, int, 0644);
69 MODULE_PARM_DESC(dbg_func,
70 "log function switch non/trace_printk/printk (default:printk)");
71
72 int mipicsi_flag;
73 module_param(mipicsi_flag, int, 0644);
74 MODULE_PARM_DESC(mipicsi_flag, "mipi csi compression predictor algorithm");
75
76 static char firmware_name[256];
77 module_param_string(firmware_name, firmware_name, sizeof(firmware_name), 0);
78 MODULE_PARM_DESC(firmware_name, "Firmware file name. Allows overriding the default firmware name.");
79
80 /*set to 16x16 since this is the amount of lines and pixels the sensor
81 exports extra. If these are kept at the 10x8 that they were on, in yuv
82 downscaling modes incorrect resolutions where requested to the sensor
83 driver with strange outcomes as a result. The proper way tot do this
84 would be to have a list of tables the specify the sensor res, mipi rec,
85 output res, and isp output res. however since we do not have this yet,
86 the chosen solution is the next best thing. */
87 int pad_w = 16;
88 module_param(pad_w, int, 0644);
89 MODULE_PARM_DESC(pad_w, "extra data for ISP processing");
90
91 int pad_h = 16;
92 module_param(pad_h, int, 0644);
93 MODULE_PARM_DESC(pad_h, "extra data for ISP processing");
94
95 /*
96 * FIXME: this is a hack to make easier to support ISP2401 variant.
97 * As a given system will either be ISP2401 or not, we can just use
98 * a boolean, in order to replace existing #ifdef ISP2401 everywhere.
99 *
100 * Once this driver gets into a better shape, however, the best would
101 * be to replace this to something stored inside atomisp allocated
102 * structures.
103 */
104
105 struct device *atomisp_dev;
106
107 static const struct atomisp_freq_scaling_rule dfs_rules_merr[] = {
108 {
109 .width = ISP_FREQ_RULE_ANY,
110 .height = ISP_FREQ_RULE_ANY,
111 .fps = ISP_FREQ_RULE_ANY,
112 .isp_freq = ISP_FREQ_400MHZ,
113 .run_mode = ATOMISP_RUN_MODE_VIDEO,
114 },
115 {
116 .width = ISP_FREQ_RULE_ANY,
117 .height = ISP_FREQ_RULE_ANY,
118 .fps = ISP_FREQ_RULE_ANY,
119 .isp_freq = ISP_FREQ_400MHZ,
120 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
121 },
122 {
123 .width = ISP_FREQ_RULE_ANY,
124 .height = ISP_FREQ_RULE_ANY,
125 .fps = ISP_FREQ_RULE_ANY,
126 .isp_freq = ISP_FREQ_400MHZ,
127 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
128 },
129 {
130 .width = ISP_FREQ_RULE_ANY,
131 .height = ISP_FREQ_RULE_ANY,
132 .fps = ISP_FREQ_RULE_ANY,
133 .isp_freq = ISP_FREQ_400MHZ,
134 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
135 },
136 {
137 .width = ISP_FREQ_RULE_ANY,
138 .height = ISP_FREQ_RULE_ANY,
139 .fps = ISP_FREQ_RULE_ANY,
140 .isp_freq = ISP_FREQ_457MHZ,
141 .run_mode = ATOMISP_RUN_MODE_SDV,
142 },
143 };
144
145 /* Merrifield and Moorefield DFS rules */
146 static const struct atomisp_dfs_config dfs_config_merr = {
147 .lowest_freq = ISP_FREQ_200MHZ,
148 .max_freq_at_vmin = ISP_FREQ_400MHZ,
149 .highest_freq = ISP_FREQ_457MHZ,
150 .dfs_table = dfs_rules_merr,
151 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr),
152 };
153
154 static const struct atomisp_freq_scaling_rule dfs_rules_merr_1179[] = {
155 {
156 .width = ISP_FREQ_RULE_ANY,
157 .height = ISP_FREQ_RULE_ANY,
158 .fps = ISP_FREQ_RULE_ANY,
159 .isp_freq = ISP_FREQ_400MHZ,
160 .run_mode = ATOMISP_RUN_MODE_VIDEO,
161 },
162 {
163 .width = ISP_FREQ_RULE_ANY,
164 .height = ISP_FREQ_RULE_ANY,
165 .fps = ISP_FREQ_RULE_ANY,
166 .isp_freq = ISP_FREQ_400MHZ,
167 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
168 },
169 {
170 .width = ISP_FREQ_RULE_ANY,
171 .height = ISP_FREQ_RULE_ANY,
172 .fps = ISP_FREQ_RULE_ANY,
173 .isp_freq = ISP_FREQ_400MHZ,
174 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
175 },
176 {
177 .width = ISP_FREQ_RULE_ANY,
178 .height = ISP_FREQ_RULE_ANY,
179 .fps = ISP_FREQ_RULE_ANY,
180 .isp_freq = ISP_FREQ_400MHZ,
181 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
182 },
183 {
184 .width = ISP_FREQ_RULE_ANY,
185 .height = ISP_FREQ_RULE_ANY,
186 .fps = ISP_FREQ_RULE_ANY,
187 .isp_freq = ISP_FREQ_400MHZ,
188 .run_mode = ATOMISP_RUN_MODE_SDV,
189 },
190 };
191
192 static const struct atomisp_dfs_config dfs_config_merr_1179 = {
193 .lowest_freq = ISP_FREQ_200MHZ,
194 .max_freq_at_vmin = ISP_FREQ_400MHZ,
195 .highest_freq = ISP_FREQ_400MHZ,
196 .dfs_table = dfs_rules_merr_1179,
197 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_1179),
198 };
199
200 static const struct atomisp_freq_scaling_rule dfs_rules_merr_117a[] = {
201 {
202 .width = 1920,
203 .height = 1080,
204 .fps = 30,
205 .isp_freq = ISP_FREQ_266MHZ,
206 .run_mode = ATOMISP_RUN_MODE_VIDEO,
207 },
208 {
209 .width = 1080,
210 .height = 1920,
211 .fps = 30,
212 .isp_freq = ISP_FREQ_266MHZ,
213 .run_mode = ATOMISP_RUN_MODE_VIDEO,
214 },
215 {
216 .width = 1920,
217 .height = 1080,
218 .fps = 45,
219 .isp_freq = ISP_FREQ_320MHZ,
220 .run_mode = ATOMISP_RUN_MODE_VIDEO,
221 },
222 {
223 .width = 1080,
224 .height = 1920,
225 .fps = 45,
226 .isp_freq = ISP_FREQ_320MHZ,
227 .run_mode = ATOMISP_RUN_MODE_VIDEO,
228 },
229 {
230 .width = ISP_FREQ_RULE_ANY,
231 .height = ISP_FREQ_RULE_ANY,
232 .fps = 60,
233 .isp_freq = ISP_FREQ_356MHZ,
234 .run_mode = ATOMISP_RUN_MODE_VIDEO,
235 },
236 {
237 .width = ISP_FREQ_RULE_ANY,
238 .height = ISP_FREQ_RULE_ANY,
239 .fps = ISP_FREQ_RULE_ANY,
240 .isp_freq = ISP_FREQ_200MHZ,
241 .run_mode = ATOMISP_RUN_MODE_VIDEO,
242 },
243 {
244 .width = ISP_FREQ_RULE_ANY,
245 .height = ISP_FREQ_RULE_ANY,
246 .fps = ISP_FREQ_RULE_ANY,
247 .isp_freq = ISP_FREQ_400MHZ,
248 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
249 },
250 {
251 .width = ISP_FREQ_RULE_ANY,
252 .height = ISP_FREQ_RULE_ANY,
253 .fps = ISP_FREQ_RULE_ANY,
254 .isp_freq = ISP_FREQ_400MHZ,
255 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
256 },
257 {
258 .width = ISP_FREQ_RULE_ANY,
259 .height = ISP_FREQ_RULE_ANY,
260 .fps = ISP_FREQ_RULE_ANY,
261 .isp_freq = ISP_FREQ_200MHZ,
262 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
263 },
264 {
265 .width = ISP_FREQ_RULE_ANY,
266 .height = ISP_FREQ_RULE_ANY,
267 .fps = ISP_FREQ_RULE_ANY,
268 .isp_freq = ISP_FREQ_400MHZ,
269 .run_mode = ATOMISP_RUN_MODE_SDV,
270 },
271 };
272
273 static struct atomisp_dfs_config dfs_config_merr_117a = {
274 .lowest_freq = ISP_FREQ_200MHZ,
275 .max_freq_at_vmin = ISP_FREQ_200MHZ,
276 .highest_freq = ISP_FREQ_400MHZ,
277 .dfs_table = dfs_rules_merr_117a,
278 .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_117a),
279 };
280
281 static const struct atomisp_freq_scaling_rule dfs_rules_byt[] = {
282 {
283 .width = ISP_FREQ_RULE_ANY,
284 .height = ISP_FREQ_RULE_ANY,
285 .fps = ISP_FREQ_RULE_ANY,
286 .isp_freq = ISP_FREQ_400MHZ,
287 .run_mode = ATOMISP_RUN_MODE_VIDEO,
288 },
289 {
290 .width = ISP_FREQ_RULE_ANY,
291 .height = ISP_FREQ_RULE_ANY,
292 .fps = ISP_FREQ_RULE_ANY,
293 .isp_freq = ISP_FREQ_400MHZ,
294 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
295 },
296 {
297 .width = ISP_FREQ_RULE_ANY,
298 .height = ISP_FREQ_RULE_ANY,
299 .fps = ISP_FREQ_RULE_ANY,
300 .isp_freq = ISP_FREQ_400MHZ,
301 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
302 },
303 {
304 .width = ISP_FREQ_RULE_ANY,
305 .height = ISP_FREQ_RULE_ANY,
306 .fps = ISP_FREQ_RULE_ANY,
307 .isp_freq = ISP_FREQ_400MHZ,
308 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
309 },
310 {
311 .width = ISP_FREQ_RULE_ANY,
312 .height = ISP_FREQ_RULE_ANY,
313 .fps = ISP_FREQ_RULE_ANY,
314 .isp_freq = ISP_FREQ_400MHZ,
315 .run_mode = ATOMISP_RUN_MODE_SDV,
316 },
317 };
318
319 static const struct atomisp_dfs_config dfs_config_byt = {
320 .lowest_freq = ISP_FREQ_200MHZ,
321 .max_freq_at_vmin = ISP_FREQ_400MHZ,
322 .highest_freq = ISP_FREQ_400MHZ,
323 .dfs_table = dfs_rules_byt,
324 .dfs_table_size = ARRAY_SIZE(dfs_rules_byt),
325 };
326
327 static const struct atomisp_freq_scaling_rule dfs_rules_cht[] = {
328 {
329 .width = ISP_FREQ_RULE_ANY,
330 .height = ISP_FREQ_RULE_ANY,
331 .fps = ISP_FREQ_RULE_ANY,
332 .isp_freq = ISP_FREQ_320MHZ,
333 .run_mode = ATOMISP_RUN_MODE_VIDEO,
334 },
335 {
336 .width = ISP_FREQ_RULE_ANY,
337 .height = ISP_FREQ_RULE_ANY,
338 .fps = ISP_FREQ_RULE_ANY,
339 .isp_freq = ISP_FREQ_356MHZ,
340 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
341 },
342 {
343 .width = ISP_FREQ_RULE_ANY,
344 .height = ISP_FREQ_RULE_ANY,
345 .fps = ISP_FREQ_RULE_ANY,
346 .isp_freq = ISP_FREQ_320MHZ,
347 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
348 },
349 {
350 .width = ISP_FREQ_RULE_ANY,
351 .height = ISP_FREQ_RULE_ANY,
352 .fps = ISP_FREQ_RULE_ANY,
353 .isp_freq = ISP_FREQ_320MHZ,
354 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
355 },
356 {
357 .width = 1280,
358 .height = 720,
359 .fps = ISP_FREQ_RULE_ANY,
360 .isp_freq = ISP_FREQ_320MHZ,
361 .run_mode = ATOMISP_RUN_MODE_SDV,
362 },
363 {
364 .width = ISP_FREQ_RULE_ANY,
365 .height = ISP_FREQ_RULE_ANY,
366 .fps = ISP_FREQ_RULE_ANY,
367 .isp_freq = ISP_FREQ_356MHZ,
368 .run_mode = ATOMISP_RUN_MODE_SDV,
369 },
370 };
371
372 static const struct atomisp_freq_scaling_rule dfs_rules_cht_soc[] = {
373 {
374 .width = ISP_FREQ_RULE_ANY,
375 .height = ISP_FREQ_RULE_ANY,
376 .fps = ISP_FREQ_RULE_ANY,
377 .isp_freq = ISP_FREQ_356MHZ,
378 .run_mode = ATOMISP_RUN_MODE_VIDEO,
379 },
380 {
381 .width = ISP_FREQ_RULE_ANY,
382 .height = ISP_FREQ_RULE_ANY,
383 .fps = ISP_FREQ_RULE_ANY,
384 .isp_freq = ISP_FREQ_356MHZ,
385 .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE,
386 },
387 {
388 .width = ISP_FREQ_RULE_ANY,
389 .height = ISP_FREQ_RULE_ANY,
390 .fps = ISP_FREQ_RULE_ANY,
391 .isp_freq = ISP_FREQ_320MHZ,
392 .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE,
393 },
394 {
395 .width = ISP_FREQ_RULE_ANY,
396 .height = ISP_FREQ_RULE_ANY,
397 .fps = ISP_FREQ_RULE_ANY,
398 .isp_freq = ISP_FREQ_320MHZ,
399 .run_mode = ATOMISP_RUN_MODE_PREVIEW,
400 },
401 {
402 .width = ISP_FREQ_RULE_ANY,
403 .height = ISP_FREQ_RULE_ANY,
404 .fps = ISP_FREQ_RULE_ANY,
405 .isp_freq = ISP_FREQ_356MHZ,
406 .run_mode = ATOMISP_RUN_MODE_SDV,
407 },
408 };
409
410 static const struct atomisp_dfs_config dfs_config_cht = {
411 .lowest_freq = ISP_FREQ_100MHZ,
412 .max_freq_at_vmin = ISP_FREQ_356MHZ,
413 .highest_freq = ISP_FREQ_356MHZ,
414 .dfs_table = dfs_rules_cht,
415 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht),
416 };
417
418 /* This one should be visible also by atomisp_cmd.c */
419 const struct atomisp_dfs_config dfs_config_cht_soc = {
420 .lowest_freq = ISP_FREQ_100MHZ,
421 .max_freq_at_vmin = ISP_FREQ_356MHZ,
422 .highest_freq = ISP_FREQ_356MHZ,
423 .dfs_table = dfs_rules_cht_soc,
424 .dfs_table_size = ARRAY_SIZE(dfs_rules_cht_soc),
425 };
426
atomisp_video_init(struct atomisp_video_pipe * video,const char * name,unsigned int run_mode)427 int atomisp_video_init(struct atomisp_video_pipe *video, const char *name,
428 unsigned int run_mode)
429 {
430 int ret;
431 const char *direction;
432
433 switch (video->type) {
434 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
435 direction = "output";
436 video->pad.flags = MEDIA_PAD_FL_SINK;
437 video->vdev.fops = &atomisp_fops;
438 video->vdev.ioctl_ops = &atomisp_ioctl_ops;
439 video->vdev.lock = &video->isp->mutex;
440 break;
441 default:
442 return -EINVAL;
443 }
444
445 ret = media_entity_pads_init(&video->vdev.entity, 1, &video->pad);
446 if (ret < 0)
447 return ret;
448
449 /* Initialize the video device. */
450 snprintf(video->vdev.name, sizeof(video->vdev.name),
451 "ATOMISP ISP %s %s", name, direction);
452 video->vdev.release = video_device_release_empty;
453 video_set_drvdata(&video->vdev, video->isp);
454 video->default_run_mode = run_mode;
455
456 return 0;
457 }
458
atomisp_video_unregister(struct atomisp_video_pipe * video)459 void atomisp_video_unregister(struct atomisp_video_pipe *video)
460 {
461 if (video_is_registered(&video->vdev)) {
462 media_entity_cleanup(&video->vdev.entity);
463 video_unregister_device(&video->vdev);
464 }
465 }
466
atomisp_save_iunit_reg(struct atomisp_device * isp)467 static int atomisp_save_iunit_reg(struct atomisp_device *isp)
468 {
469 struct pci_dev *pdev = to_pci_dev(isp->dev);
470
471 dev_dbg(isp->dev, "%s\n", __func__);
472
473 pci_read_config_word(pdev, PCI_COMMAND, &isp->saved_regs.pcicmdsts);
474 /* isp->saved_regs.ispmmadr is set from the atomisp_pci_probe() */
475 pci_read_config_dword(pdev, PCI_MSI_CAPID, &isp->saved_regs.msicap);
476 pci_read_config_dword(pdev, PCI_MSI_ADDR, &isp->saved_regs.msi_addr);
477 pci_read_config_word(pdev, PCI_MSI_DATA, &isp->saved_regs.msi_data);
478 pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &isp->saved_regs.intr);
479 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &isp->saved_regs.interrupt_control);
480
481 pci_read_config_dword(pdev, MRFLD_PCI_PMCS, &isp->saved_regs.pmcs);
482 /* Ensure read/write combining is enabled. */
483 pci_read_config_dword(pdev, PCI_I_CONTROL, &isp->saved_regs.i_control);
484 isp->saved_regs.i_control |=
485 MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING |
486 MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING;
487 pci_read_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL,
488 &isp->saved_regs.csi_access_viol);
489 pci_read_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL,
490 &isp->saved_regs.csi_rcomp_config);
491 /*
492 * Hardware bugs require setting CSI_HS_OVR_CLK_GATE_ON_UPDATE.
493 * ANN/CHV: RCOMP updates do not happen when using CSI2+ path
494 * and sensor sending "continuous clock".
495 * TNG/ANN/CHV: MIPI packets are lost if the HS entry sequence
496 * is missed, and IUNIT can hang.
497 * For both issues, setting this bit is a workaround.
498 */
499 isp->saved_regs.csi_rcomp_config |= MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE;
500 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
501 &isp->saved_regs.csi_afe_dly);
502 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL,
503 &isp->saved_regs.csi_control);
504 if (isp->media_dev.hw_revision >=
505 (ATOMISP_HW_REVISION_ISP2401 << ATOMISP_HW_REVISION_SHIFT))
506 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_PARPATHEN;
507 /*
508 * On CHT CSI_READY bit should be enabled before stream on
509 */
510 if (IS_CHT && (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 <<
511 ATOMISP_HW_REVISION_SHIFT) | ATOMISP_HW_STEPPING_B0)))
512 isp->saved_regs.csi_control |= MRFLD_PCI_CSI_CONTROL_CSI_READY;
513 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL,
514 &isp->saved_regs.csi_afe_rcomp_config);
515 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL,
516 &isp->saved_regs.csi_afe_hs_control);
517 pci_read_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL,
518 &isp->saved_regs.csi_deadline_control);
519 return 0;
520 }
521
atomisp_restore_iunit_reg(struct atomisp_device * isp)522 static int atomisp_restore_iunit_reg(struct atomisp_device *isp)
523 {
524 struct pci_dev *pdev = to_pci_dev(isp->dev);
525
526 dev_dbg(isp->dev, "%s\n", __func__);
527
528 pci_write_config_word(pdev, PCI_COMMAND, isp->saved_regs.pcicmdsts);
529 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, isp->saved_regs.ispmmadr);
530 pci_write_config_dword(pdev, PCI_MSI_CAPID, isp->saved_regs.msicap);
531 pci_write_config_dword(pdev, PCI_MSI_ADDR, isp->saved_regs.msi_addr);
532 pci_write_config_word(pdev, PCI_MSI_DATA, isp->saved_regs.msi_data);
533 pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, isp->saved_regs.intr);
534 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, isp->saved_regs.interrupt_control);
535 pci_write_config_dword(pdev, PCI_I_CONTROL, isp->saved_regs.i_control);
536
537 pci_write_config_dword(pdev, MRFLD_PCI_PMCS, isp->saved_regs.pmcs);
538 pci_write_config_dword(pdev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL,
539 isp->saved_regs.csi_access_viol);
540 pci_write_config_dword(pdev, MRFLD_PCI_CSI_RCOMP_CONTROL,
541 isp->saved_regs.csi_rcomp_config);
542 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL,
543 isp->saved_regs.csi_afe_dly);
544 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL,
545 isp->saved_regs.csi_control);
546 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL,
547 isp->saved_regs.csi_afe_rcomp_config);
548 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_HS_CONTROL,
549 isp->saved_regs.csi_afe_hs_control);
550 pci_write_config_dword(pdev, MRFLD_PCI_CSI_DEADLINE_CONTROL,
551 isp->saved_regs.csi_deadline_control);
552
553 /*
554 * for MRFLD, Software/firmware needs to write a 1 to bit0
555 * of the register at CSI_RECEIVER_SELECTION_REG to enable
556 * SH CSI backend write 0 will enable Arasan CSI backend,
557 * which has bugs(like sighting:4567697 and 4567699) and
558 * will be removed in B0
559 */
560 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1);
561 return 0;
562 }
563
atomisp_mrfld_pre_power_down(struct atomisp_device * isp)564 static int atomisp_mrfld_pre_power_down(struct atomisp_device *isp)
565 {
566 struct pci_dev *pdev = to_pci_dev(isp->dev);
567 u32 irq;
568 unsigned long flags;
569
570 spin_lock_irqsave(&isp->lock, flags);
571
572 /*
573 * MRFLD HAS requirement: cannot power off i-unit if
574 * ISP has IRQ not serviced.
575 * So, here we need to check if there is any pending
576 * IRQ, if so, waiting for it to be served
577 */
578 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
579 irq &= BIT(INTR_IIR);
580 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
581
582 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
583 if (!(irq & BIT(INTR_IIR)))
584 goto done;
585
586 atomisp_css2_hw_store_32(MRFLD_INTR_CLEAR_REG, 0xFFFFFFFF);
587 atomisp_load_uint32(MRFLD_INTR_STATUS_REG, &irq);
588 if (irq != 0) {
589 dev_err(isp->dev,
590 "%s: fail to clear isp interrupt status reg=0x%x\n",
591 __func__, irq);
592 spin_unlock_irqrestore(&isp->lock, flags);
593 return -EAGAIN;
594 } else {
595 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
596 irq &= BIT(INTR_IIR);
597 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
598
599 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
600 if (!(irq & BIT(INTR_IIR))) {
601 atomisp_css2_hw_store_32(MRFLD_INTR_ENABLE_REG, 0x0);
602 goto done;
603 }
604 dev_err(isp->dev,
605 "%s: error in iunit interrupt. status reg=0x%x\n",
606 __func__, irq);
607 spin_unlock_irqrestore(&isp->lock, flags);
608 return -EAGAIN;
609 }
610 done:
611 /*
612 * MRFLD WORKAROUND:
613 * before powering off IUNIT, clear the pending interrupts
614 * and disable the interrupt. driver should avoid writing 0
615 * to IIR. It could block subsequent interrupt messages.
616 * HW sighting:4568410.
617 */
618 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
619 irq &= ~BIT(INTR_IER);
620 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
621
622 atomisp_msi_irq_uninit(isp);
623 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true);
624 spin_unlock_irqrestore(&isp->lock, flags);
625
626 return 0;
627 }
628
629 /*
630 * WA for DDR DVFS enable/disable
631 * By default, ISP will force DDR DVFS 1600MHz before disable DVFS
632 */
punit_ddr_dvfs_enable(bool enable)633 static void punit_ddr_dvfs_enable(bool enable)
634 {
635 int reg;
636
637 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSDVFS, ®);
638 if (enable) {
639 reg &= ~(MRFLD_BIT0 | MRFLD_BIT1);
640 } else {
641 reg |= MRFLD_BIT1;
642 reg &= ~(MRFLD_BIT0);
643 }
644 iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_REG_WRITE, MRFLD_ISPSSDVFS, reg);
645 }
646
atomisp_mrfld_power(struct atomisp_device * isp,bool enable)647 static int atomisp_mrfld_power(struct atomisp_device *isp, bool enable)
648 {
649 struct pci_dev *pdev = to_pci_dev(isp->dev);
650 unsigned long timeout;
651 u32 val = enable ? MRFLD_ISPSSPM0_IUNIT_POWER_ON :
652 MRFLD_ISPSSPM0_IUNIT_POWER_OFF;
653
654 dev_dbg(isp->dev, "IUNIT power-%s.\n", enable ? "on" : "off");
655
656 /* WA for P-Unit, if DVFS enabled, ISP timeout observed */
657 if (IS_CHT && enable) {
658 punit_ddr_dvfs_enable(false);
659 msleep(20);
660 }
661
662 /* Write to ISPSSPM0 bit[1:0] to power on/off the IUNIT */
663 iosf_mbi_modify(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0,
664 val, MRFLD_ISPSSPM0_ISPSSC_MASK);
665
666 /* WA:Enable DVFS */
667 if (IS_CHT && !enable)
668 punit_ddr_dvfs_enable(true);
669
670 /*
671 * There should be no IUNIT access while power-down is
672 * in progress. HW sighting: 4567865.
673 * Wait up to 50 ms for the IUNIT to shut down.
674 * And we do the same for power on.
675 */
676 timeout = jiffies + msecs_to_jiffies(50);
677 do {
678 u32 tmp;
679
680 /* Wait until ISPSSPM0 bit[25:24] shows the right value */
681 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_REG_READ, MRFLD_ISPSSPM0, &tmp);
682 tmp = (tmp >> MRFLD_ISPSSPM0_ISPSSS_OFFSET) & MRFLD_ISPSSPM0_ISPSSC_MASK;
683 if (tmp == val) {
684 trace_ipu_cstate(enable);
685 pdev->current_state = enable ? PCI_D0 : PCI_D3cold;
686 return 0;
687 }
688
689 if (time_after(jiffies, timeout))
690 break;
691
692 /* FIXME: experienced value for delay */
693 usleep_range(100, 150);
694 } while (1);
695
696 if (enable)
697 msleep(10);
698
699 dev_err(isp->dev, "IUNIT power-%s timeout.\n", enable ? "on" : "off");
700 return -EBUSY;
701 }
702
atomisp_power_off(struct device * dev)703 int atomisp_power_off(struct device *dev)
704 {
705 struct atomisp_device *isp = dev_get_drvdata(dev);
706 struct pci_dev *pdev = to_pci_dev(dev);
707 int ret;
708 u32 reg;
709
710 atomisp_css_uninit(isp);
711
712 ret = atomisp_mrfld_pre_power_down(isp);
713 if (ret)
714 return ret;
715
716 /*
717 * MRFLD IUNIT DPHY is located in an always-power-on island
718 * MRFLD HW design need all CSI ports are disabled before
719 * powering down the IUNIT.
720 */
721 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, ®);
722 reg |= MRFLD_ALL_CSI_PORTS_OFF_MASK;
723 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, reg);
724
725 cpu_latency_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
726 pci_save_state(pdev);
727 return atomisp_mrfld_power(isp, false);
728 }
729
atomisp_power_on(struct device * dev)730 int atomisp_power_on(struct device *dev)
731 {
732 struct atomisp_device *isp = (struct atomisp_device *)
733 dev_get_drvdata(dev);
734 int ret;
735
736 ret = atomisp_mrfld_power(isp, true);
737 if (ret)
738 return ret;
739
740 pci_restore_state(to_pci_dev(dev));
741 cpu_latency_qos_update_request(&isp->pm_qos, isp->max_isr_latency);
742
743 /*restore register values for iUnit and iUnitPHY registers*/
744 if (isp->saved_regs.pcicmdsts)
745 atomisp_restore_iunit_reg(isp);
746
747 atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true);
748
749 return atomisp_css_init(isp);
750 }
751
atomisp_suspend(struct device * dev)752 static int atomisp_suspend(struct device *dev)
753 {
754 struct atomisp_device *isp = (struct atomisp_device *)
755 dev_get_drvdata(dev);
756 /* FIXME: only has one isp_subdev at present */
757 struct atomisp_sub_device *asd = &isp->asd[0];
758 unsigned long flags;
759
760 /*
761 * FIXME: Suspend is not supported by sensors. Abort if any video
762 * node was opened.
763 */
764 if (atomisp_dev_users(isp))
765 return -EBUSY;
766
767 spin_lock_irqsave(&isp->lock, flags);
768 if (asd->streaming != ATOMISP_DEVICE_STREAMING_DISABLED) {
769 spin_unlock_irqrestore(&isp->lock, flags);
770 dev_err(isp->dev, "atomisp cannot suspend at this time.\n");
771 return -EINVAL;
772 }
773 spin_unlock_irqrestore(&isp->lock, flags);
774
775 pm_runtime_resume(dev);
776
777 return atomisp_power_off(dev);
778 }
779
atomisp_resume(struct device * dev)780 static int atomisp_resume(struct device *dev)
781 {
782 return atomisp_power_on(dev);
783 }
784
atomisp_csi_lane_config(struct atomisp_device * isp)785 int atomisp_csi_lane_config(struct atomisp_device *isp)
786 {
787 struct pci_dev *pdev = to_pci_dev(isp->dev);
788 static const struct {
789 u8 code;
790 u8 lanes[MRFLD_PORT_NUM];
791 } portconfigs[] = {
792 /* Tangier/Merrifield available lane configurations */
793 { 0x00, { 4, 1, 0 } }, /* 00000 */
794 { 0x01, { 3, 1, 0 } }, /* 00001 */
795 { 0x02, { 2, 1, 0 } }, /* 00010 */
796 { 0x03, { 1, 1, 0 } }, /* 00011 */
797 { 0x04, { 2, 1, 2 } }, /* 00100 */
798 { 0x08, { 3, 1, 1 } }, /* 01000 */
799 { 0x09, { 2, 1, 1 } }, /* 01001 */
800 { 0x0a, { 1, 1, 1 } }, /* 01010 */
801
802 /* Anniedale/Moorefield only configurations */
803 { 0x10, { 4, 2, 0 } }, /* 10000 */
804 { 0x11, { 3, 2, 0 } }, /* 10001 */
805 { 0x12, { 2, 2, 0 } }, /* 10010 */
806 { 0x13, { 1, 2, 0 } }, /* 10011 */
807 { 0x14, { 2, 2, 2 } }, /* 10100 */
808 { 0x18, { 3, 2, 1 } }, /* 11000 */
809 { 0x19, { 2, 2, 1 } }, /* 11001 */
810 { 0x1a, { 1, 2, 1 } }, /* 11010 */
811 };
812
813 unsigned int i, j;
814 u8 sensor_lanes[MRFLD_PORT_NUM] = { 0 };
815 u32 csi_control;
816 int nportconfigs;
817 u32 port_config_mask;
818 int port3_lanes_shift;
819
820 if (isp->media_dev.hw_revision <
821 ATOMISP_HW_REVISION_ISP2401_LEGACY <<
822 ATOMISP_HW_REVISION_SHIFT) {
823 /* Merrifield */
824 port_config_mask = MRFLD_PORT_CONFIG_MASK;
825 port3_lanes_shift = MRFLD_PORT3_LANES_SHIFT;
826 } else {
827 /* Moorefield / Cherryview */
828 port_config_mask = CHV_PORT_CONFIG_MASK;
829 port3_lanes_shift = CHV_PORT3_LANES_SHIFT;
830 }
831
832 if (isp->media_dev.hw_revision <
833 ATOMISP_HW_REVISION_ISP2401 <<
834 ATOMISP_HW_REVISION_SHIFT) {
835 /* Merrifield / Moorefield legacy input system */
836 nportconfigs = MRFLD_PORT_CONFIG_NUM;
837 } else {
838 /* Moorefield / Cherryview new input system */
839 nportconfigs = ARRAY_SIZE(portconfigs);
840 }
841
842 for (i = 0; i < isp->input_cnt; i++) {
843 struct camera_mipi_info *mipi_info;
844
845 if (isp->inputs[i].type != RAW_CAMERA &&
846 isp->inputs[i].type != SOC_CAMERA)
847 continue;
848
849 mipi_info = atomisp_to_sensor_mipi_info(isp->inputs[i].camera);
850 if (!mipi_info)
851 continue;
852
853 switch (mipi_info->port) {
854 case ATOMISP_CAMERA_PORT_PRIMARY:
855 sensor_lanes[0] = mipi_info->num_lanes;
856 break;
857 case ATOMISP_CAMERA_PORT_SECONDARY:
858 sensor_lanes[1] = mipi_info->num_lanes;
859 break;
860 case ATOMISP_CAMERA_PORT_TERTIARY:
861 sensor_lanes[2] = mipi_info->num_lanes;
862 break;
863 default:
864 dev_err(isp->dev,
865 "%s: invalid port: %d for the %dth sensor\n",
866 __func__, mipi_info->port, i);
867 return -EINVAL;
868 }
869 }
870
871 for (i = 0; i < nportconfigs; i++) {
872 for (j = 0; j < MRFLD_PORT_NUM; j++)
873 if (sensor_lanes[j] &&
874 sensor_lanes[j] != portconfigs[i].lanes[j])
875 break;
876
877 if (j == MRFLD_PORT_NUM)
878 break; /* Found matching setting */
879 }
880
881 if (i >= nportconfigs) {
882 dev_err(isp->dev,
883 "%s: could not find the CSI port setting for %d-%d-%d\n",
884 __func__,
885 sensor_lanes[0], sensor_lanes[1], sensor_lanes[2]);
886 return -EINVAL;
887 }
888
889 pci_read_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, &csi_control);
890 csi_control &= ~port_config_mask;
891 csi_control |= (portconfigs[i].code << MRFLD_PORT_CONFIGCODE_SHIFT)
892 | (portconfigs[i].lanes[0] ? 0 : (1 << MRFLD_PORT1_ENABLE_SHIFT))
893 | (portconfigs[i].lanes[1] ? 0 : (1 << MRFLD_PORT2_ENABLE_SHIFT))
894 | (portconfigs[i].lanes[2] ? 0 : (1 << MRFLD_PORT3_ENABLE_SHIFT))
895 | (((1 << portconfigs[i].lanes[0]) - 1) << MRFLD_PORT1_LANES_SHIFT)
896 | (((1 << portconfigs[i].lanes[1]) - 1) << MRFLD_PORT2_LANES_SHIFT)
897 | (((1 << portconfigs[i].lanes[2]) - 1) << port3_lanes_shift);
898
899 pci_write_config_dword(pdev, MRFLD_PCI_CSI_CONTROL, csi_control);
900
901 dev_dbg(isp->dev,
902 "%s: the portconfig is %d-%d-%d, CSI_CONTROL is 0x%08X\n",
903 __func__, portconfigs[i].lanes[0], portconfigs[i].lanes[1],
904 portconfigs[i].lanes[2], csi_control);
905
906 return 0;
907 }
908
atomisp_subdev_probe(struct atomisp_device * isp)909 static int atomisp_subdev_probe(struct atomisp_device *isp)
910 {
911 const struct atomisp_platform_data *pdata;
912 struct intel_v4l2_subdev_table *subdevs;
913 int ret, raw_index = -1, count;
914
915 pdata = atomisp_get_platform_data();
916 if (!pdata) {
917 dev_err(isp->dev, "no platform data available\n");
918 return 0;
919 }
920
921 /* FIXME: should return -EPROBE_DEFER if not all subdevs were probed */
922 for (count = 0; count < SUBDEV_WAIT_TIMEOUT_MAX_COUNT; count++) {
923 int camera_count = 0;
924
925 for (subdevs = pdata->subdevs; subdevs->type; ++subdevs) {
926 if (subdevs->type == RAW_CAMERA ||
927 subdevs->type == SOC_CAMERA)
928 camera_count++;
929 }
930 if (camera_count)
931 break;
932 msleep(SUBDEV_WAIT_TIMEOUT);
933 }
934 /* Wait more time to give more time for subdev init code to finish */
935 msleep(5 * SUBDEV_WAIT_TIMEOUT);
936
937 /* FIXME: should, instead, use I2C probe */
938
939 for (subdevs = pdata->subdevs; subdevs->type; ++subdevs) {
940 ret = v4l2_device_register_subdev(&isp->v4l2_dev, subdevs->subdev);
941 if (ret)
942 continue;
943
944 switch (subdevs->type) {
945 case RAW_CAMERA:
946 dev_dbg(isp->dev, "raw_index: %d\n", raw_index);
947 raw_index = isp->input_cnt;
948 fallthrough;
949 case SOC_CAMERA:
950 dev_dbg(isp->dev, "SOC_INDEX: %d\n", isp->input_cnt);
951 if (isp->input_cnt >= ATOM_ISP_MAX_INPUTS) {
952 dev_warn(isp->dev,
953 "too many atomisp inputs, ignored\n");
954 break;
955 }
956
957 isp->inputs[isp->input_cnt].type = subdevs->type;
958 isp->inputs[isp->input_cnt].port = subdevs->port;
959 isp->inputs[isp->input_cnt].camera = subdevs->subdev;
960 isp->inputs[isp->input_cnt].sensor_index = 0;
961 /*
962 * initialize the subdev frame size, then next we can
963 * judge whether frame_size store effective value via
964 * pixel_format.
965 */
966 isp->inputs[isp->input_cnt].frame_size.pixel_format = 0;
967 isp->input_cnt++;
968 break;
969 case CAMERA_MOTOR:
970 if (isp->motor) {
971 dev_warn(isp->dev, "too many atomisp motors\n");
972 continue;
973 }
974 isp->motor = subdevs->subdev;
975 break;
976 case LED_FLASH:
977 case XENON_FLASH:
978 if (isp->flash) {
979 dev_warn(isp->dev, "too many atomisp flash devices\n");
980 continue;
981 }
982 isp->flash = subdevs->subdev;
983 break;
984 default:
985 dev_dbg(isp->dev, "unknown subdev probed\n");
986 break;
987 }
988 }
989
990 /*
991 * HACK: Currently VCM belongs to primary sensor only, but correct
992 * approach must be to acquire from platform code which sensor
993 * owns it.
994 */
995 if (isp->motor && raw_index >= 0)
996 isp->inputs[raw_index].motor = isp->motor;
997
998 /* Proceed even if no modules detected. For COS mode and no modules. */
999 if (!isp->input_cnt)
1000 dev_warn(isp->dev, "no camera attached or fail to detect\n");
1001 else
1002 dev_info(isp->dev, "detected %d camera sensors\n",
1003 isp->input_cnt);
1004
1005 return atomisp_csi_lane_config(isp);
1006 }
1007
atomisp_unregister_entities(struct atomisp_device * isp)1008 static void atomisp_unregister_entities(struct atomisp_device *isp)
1009 {
1010 unsigned int i;
1011 struct v4l2_subdev *sd, *next;
1012
1013 for (i = 0; i < isp->num_of_streams; i++)
1014 atomisp_subdev_unregister_entities(&isp->asd[i]);
1015 atomisp_tpg_unregister_entities(&isp->tpg);
1016 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++)
1017 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]);
1018
1019 list_for_each_entry_safe(sd, next, &isp->v4l2_dev.subdevs, list)
1020 v4l2_device_unregister_subdev(sd);
1021
1022 v4l2_device_unregister(&isp->v4l2_dev);
1023 media_device_unregister(&isp->media_dev);
1024 media_device_cleanup(&isp->media_dev);
1025 }
1026
atomisp_register_entities(struct atomisp_device * isp)1027 static int atomisp_register_entities(struct atomisp_device *isp)
1028 {
1029 int ret = 0;
1030 unsigned int i;
1031
1032 isp->media_dev.dev = isp->dev;
1033
1034 strscpy(isp->media_dev.model, "Intel Atom ISP",
1035 sizeof(isp->media_dev.model));
1036
1037 media_device_init(&isp->media_dev);
1038 isp->v4l2_dev.mdev = &isp->media_dev;
1039 ret = v4l2_device_register(isp->dev, &isp->v4l2_dev);
1040 if (ret < 0) {
1041 dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n",
1042 __func__, ret);
1043 goto v4l2_device_failed;
1044 }
1045
1046 ret = atomisp_subdev_probe(isp);
1047 if (ret < 0)
1048 goto csi_and_subdev_probe_failed;
1049
1050 /* Register internal entities */
1051 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) {
1052 ret = atomisp_mipi_csi2_register_entities(&isp->csi2_port[i],
1053 &isp->v4l2_dev);
1054 if (ret == 0)
1055 continue;
1056
1057 /* error case */
1058 dev_err(isp->dev, "failed to register the CSI port: %d\n", i);
1059 /* deregister all registered CSI ports */
1060 while (i--)
1061 atomisp_mipi_csi2_unregister_entities(
1062 &isp->csi2_port[i]);
1063
1064 goto csi_and_subdev_probe_failed;
1065 }
1066
1067 ret = atomisp_tpg_register_entities(&isp->tpg, &isp->v4l2_dev);
1068 if (ret < 0) {
1069 dev_err(isp->dev, "atomisp_tpg_register_entities\n");
1070 goto tpg_register_failed;
1071 }
1072
1073 for (i = 0; i < isp->num_of_streams; i++) {
1074 struct atomisp_sub_device *asd = &isp->asd[i];
1075
1076 ret = atomisp_subdev_register_subdev(asd, &isp->v4l2_dev);
1077 if (ret < 0) {
1078 dev_err(isp->dev, "atomisp_subdev_register_subdev fail\n");
1079 for (; i > 0; i--)
1080 atomisp_subdev_unregister_entities(
1081 &isp->asd[i - 1]);
1082 goto subdev_register_failed;
1083 }
1084 }
1085
1086 for (i = 0; i < isp->num_of_streams; i++) {
1087 struct atomisp_sub_device *asd = &isp->asd[i];
1088
1089 init_completion(&asd->init_done);
1090
1091 asd->delayed_init_workq =
1092 alloc_workqueue(isp->v4l2_dev.name, WQ_CPU_INTENSIVE,
1093 1);
1094 if (!asd->delayed_init_workq) {
1095 dev_err(isp->dev,
1096 "Failed to initialize delayed init workq\n");
1097 ret = -ENOMEM;
1098
1099 for (; i > 0; i--)
1100 destroy_workqueue(isp->asd[i - 1].
1101 delayed_init_workq);
1102 goto wq_alloc_failed;
1103 }
1104 INIT_WORK(&asd->delayed_init_work, atomisp_delayed_init_work);
1105 }
1106
1107 for (i = 0; i < isp->input_cnt; i++) {
1108 if (isp->inputs[i].port >= ATOMISP_CAMERA_NR_PORTS) {
1109 dev_err(isp->dev, "isp->inputs port %d not supported\n",
1110 isp->inputs[i].port);
1111 ret = -EINVAL;
1112 goto link_failed;
1113 }
1114 }
1115
1116 if (isp->input_cnt < ATOM_ISP_MAX_INPUTS) {
1117 dev_dbg(isp->dev,
1118 "TPG detected, camera_cnt: %d\n", isp->input_cnt);
1119 isp->inputs[isp->input_cnt].type = TEST_PATTERN;
1120 isp->inputs[isp->input_cnt].port = -1;
1121 isp->inputs[isp->input_cnt++].camera = &isp->tpg.sd;
1122 } else {
1123 dev_warn(isp->dev, "too many atomisp inputs, TPG ignored.\n");
1124 }
1125
1126 return 0;
1127
1128 link_failed:
1129 for (i = 0; i < isp->num_of_streams; i++)
1130 destroy_workqueue(isp->asd[i].
1131 delayed_init_workq);
1132 wq_alloc_failed:
1133 for (i = 0; i < isp->num_of_streams; i++)
1134 atomisp_subdev_unregister_entities(
1135 &isp->asd[i]);
1136 subdev_register_failed:
1137 atomisp_tpg_unregister_entities(&isp->tpg);
1138 tpg_register_failed:
1139 for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++)
1140 atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]);
1141 csi_and_subdev_probe_failed:
1142 v4l2_device_unregister(&isp->v4l2_dev);
1143 v4l2_device_failed:
1144 media_device_unregister(&isp->media_dev);
1145 media_device_cleanup(&isp->media_dev);
1146 return ret;
1147 }
1148
atomisp_register_device_nodes(struct atomisp_device * isp)1149 static int atomisp_register_device_nodes(struct atomisp_device *isp)
1150 {
1151 int i, err;
1152
1153 for (i = 0; i < isp->num_of_streams; i++) {
1154 err = atomisp_subdev_register_video_nodes(&isp->asd[i], &isp->v4l2_dev);
1155 if (err)
1156 return err;
1157 }
1158
1159 err = atomisp_create_pads_links(isp);
1160 if (err)
1161 return err;
1162
1163 err = v4l2_device_register_subdev_nodes(&isp->v4l2_dev);
1164 if (err)
1165 return err;
1166
1167 return media_device_register(&isp->media_dev);
1168 }
1169
atomisp_initialize_modules(struct atomisp_device * isp)1170 static int atomisp_initialize_modules(struct atomisp_device *isp)
1171 {
1172 int ret;
1173
1174 ret = atomisp_mipi_csi2_init(isp);
1175 if (ret < 0) {
1176 dev_err(isp->dev, "mipi csi2 initialization failed\n");
1177 goto error_mipi_csi2;
1178 }
1179
1180 ret = atomisp_tpg_init(isp);
1181 if (ret < 0) {
1182 dev_err(isp->dev, "tpg initialization failed\n");
1183 goto error_tpg;
1184 }
1185
1186 ret = atomisp_subdev_init(isp);
1187 if (ret < 0) {
1188 dev_err(isp->dev, "ISP subdev initialization failed\n");
1189 goto error_isp_subdev;
1190 }
1191
1192 return 0;
1193
1194 error_isp_subdev:
1195 error_tpg:
1196 atomisp_tpg_cleanup(isp);
1197 error_mipi_csi2:
1198 atomisp_mipi_csi2_cleanup(isp);
1199 return ret;
1200 }
1201
atomisp_uninitialize_modules(struct atomisp_device * isp)1202 static void atomisp_uninitialize_modules(struct atomisp_device *isp)
1203 {
1204 atomisp_tpg_cleanup(isp);
1205 atomisp_mipi_csi2_cleanup(isp);
1206 }
1207
1208 const struct firmware *
atomisp_load_firmware(struct atomisp_device * isp)1209 atomisp_load_firmware(struct atomisp_device *isp)
1210 {
1211 const struct firmware *fw;
1212 int rc;
1213 char *fw_path = NULL;
1214
1215 if (skip_fwload)
1216 return NULL;
1217
1218 if (firmware_name[0] != '\0') {
1219 fw_path = firmware_name;
1220 } else {
1221 if ((isp->media_dev.hw_revision >> ATOMISP_HW_REVISION_SHIFT)
1222 == ATOMISP_HW_REVISION_ISP2401)
1223 fw_path = "shisp_2401a0_v21.bin";
1224
1225 if (isp->media_dev.hw_revision ==
1226 ((ATOMISP_HW_REVISION_ISP2401_LEGACY << ATOMISP_HW_REVISION_SHIFT)
1227 | ATOMISP_HW_STEPPING_A0))
1228 fw_path = "shisp_2401a0_legacy_v21.bin";
1229
1230 if (isp->media_dev.hw_revision ==
1231 ((ATOMISP_HW_REVISION_ISP2400 << ATOMISP_HW_REVISION_SHIFT)
1232 | ATOMISP_HW_STEPPING_B0))
1233 fw_path = "shisp_2400b0_v21.bin";
1234 }
1235
1236 if (!fw_path) {
1237 dev_err(isp->dev, "Unsupported hw_revision 0x%x\n",
1238 isp->media_dev.hw_revision);
1239 return NULL;
1240 }
1241
1242 rc = request_firmware(&fw, fw_path, isp->dev);
1243 if (rc) {
1244 dev_err(isp->dev,
1245 "atomisp: Error %d while requesting firmware %s\n",
1246 rc, fw_path);
1247 return NULL;
1248 }
1249
1250 return fw;
1251 }
1252
1253 /*
1254 * Check for flags the driver was compiled with against the PCI
1255 * device. Always returns true on other than ISP 2400.
1256 */
is_valid_device(struct pci_dev * pdev,const struct pci_device_id * id)1257 static bool is_valid_device(struct pci_dev *pdev, const struct pci_device_id *id)
1258 {
1259 const char *name;
1260 const char *product;
1261
1262 product = dmi_get_system_info(DMI_PRODUCT_NAME);
1263
1264 switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) {
1265 case ATOMISP_PCI_DEVICE_SOC_MRFLD:
1266 name = "Merrifield";
1267 break;
1268 case ATOMISP_PCI_DEVICE_SOC_BYT:
1269 name = "Baytrail";
1270 break;
1271 case ATOMISP_PCI_DEVICE_SOC_ANN:
1272 name = "Anniedale";
1273 break;
1274 case ATOMISP_PCI_DEVICE_SOC_CHT:
1275 name = "Cherrytrail";
1276 break;
1277 default:
1278 dev_err(&pdev->dev, "%s: unknown device ID %x04:%x04\n",
1279 product, id->vendor, id->device);
1280 return false;
1281 }
1282
1283 if (pdev->revision <= ATOMISP_PCI_REV_BYT_A0_MAX) {
1284 dev_err(&pdev->dev, "%s revision %d is not unsupported\n",
1285 name, pdev->revision);
1286 return false;
1287 }
1288
1289 /*
1290 * FIXME:
1291 * remove the if once the driver become generic
1292 */
1293
1294 #ifndef ISP2401
1295 if (IS_ISP2401) {
1296 dev_err(&pdev->dev, "Support for %s (ISP2401) was disabled at compile time\n",
1297 name);
1298 return false;
1299 }
1300 #else
1301 if (!IS_ISP2401) {
1302 dev_err(&pdev->dev, "Support for %s (ISP2400) was disabled at compile time\n",
1303 name);
1304 return false;
1305 }
1306 #endif
1307
1308 dev_info(&pdev->dev, "Detected %s version %d (ISP240%c) on %s\n",
1309 name, pdev->revision, IS_ISP2401 ? '1' : '0', product);
1310
1311 return true;
1312 }
1313
1314 #define ATOM_ISP_PCI_BAR 0
1315
atomisp_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)1316 static int atomisp_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1317 {
1318 const struct atomisp_platform_data *pdata;
1319 struct atomisp_device *isp;
1320 unsigned int start;
1321 int err, val;
1322 u32 irq;
1323
1324 if (!is_valid_device(pdev, id))
1325 return -ENODEV;
1326
1327 /* Pointer to struct device. */
1328 atomisp_dev = &pdev->dev;
1329
1330 pdata = atomisp_get_platform_data();
1331 if (!pdata)
1332 dev_warn(&pdev->dev, "no platform data available\n");
1333
1334 err = pcim_enable_device(pdev);
1335 if (err) {
1336 dev_err(&pdev->dev, "Failed to enable CI ISP device (%d)\n", err);
1337 return err;
1338 }
1339
1340 start = pci_resource_start(pdev, ATOM_ISP_PCI_BAR);
1341 dev_dbg(&pdev->dev, "start: 0x%x\n", start);
1342
1343 err = pcim_iomap_regions(pdev, BIT(ATOM_ISP_PCI_BAR), pci_name(pdev));
1344 if (err) {
1345 dev_err(&pdev->dev, "Failed to I/O memory remapping (%d)\n", err);
1346 goto ioremap_fail;
1347 }
1348
1349 isp = devm_kzalloc(&pdev->dev, sizeof(*isp), GFP_KERNEL);
1350 if (!isp) {
1351 err = -ENOMEM;
1352 goto atomisp_dev_alloc_fail;
1353 }
1354
1355 isp->dev = &pdev->dev;
1356 isp->base = pcim_iomap_table(pdev)[ATOM_ISP_PCI_BAR];
1357 isp->saved_regs.ispmmadr = start;
1358
1359 dev_dbg(&pdev->dev, "atomisp mmio base: %p\n", isp->base);
1360
1361 mutex_init(&isp->mutex);
1362 spin_lock_init(&isp->lock);
1363
1364 /* This is not a true PCI device on SoC, so the delay is not needed. */
1365 pdev->d3hot_delay = 0;
1366
1367 pci_set_drvdata(pdev, isp);
1368
1369 switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) {
1370 case ATOMISP_PCI_DEVICE_SOC_MRFLD:
1371 isp->media_dev.hw_revision =
1372 (ATOMISP_HW_REVISION_ISP2400
1373 << ATOMISP_HW_REVISION_SHIFT) |
1374 ATOMISP_HW_STEPPING_B0;
1375
1376 switch (id->device) {
1377 case ATOMISP_PCI_DEVICE_SOC_MRFLD_1179:
1378 isp->dfs = &dfs_config_merr_1179;
1379 break;
1380 case ATOMISP_PCI_DEVICE_SOC_MRFLD_117A:
1381 isp->dfs = &dfs_config_merr_117a;
1382
1383 break;
1384 default:
1385 isp->dfs = &dfs_config_merr;
1386 break;
1387 }
1388 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1389 break;
1390 case ATOMISP_PCI_DEVICE_SOC_BYT:
1391 isp->media_dev.hw_revision =
1392 (ATOMISP_HW_REVISION_ISP2400
1393 << ATOMISP_HW_REVISION_SHIFT) |
1394 ATOMISP_HW_STEPPING_B0;
1395
1396 /*
1397 * Note: some Intel-based tablets with Android use a different
1398 * DFS table. Based on the comments at the Yocto Aero meta
1399 * version of this driver (at the ssid.h header), they're
1400 * identified via a "spid" var:
1401 *
1402 * androidboot.spid=vend:cust:manu:plat:prod:hard
1403 *
1404 * As we don't have this upstream, nor we know enough details
1405 * to use a DMI or PCI match table, the old code was just
1406 * removed, but let's keep a note here as a reminder that,
1407 * for certain devices, we may need to limit the max DFS
1408 * frequency to be below certain values, adjusting the
1409 * resolution accordingly.
1410 */
1411 isp->dfs = &dfs_config_byt;
1412
1413 /*
1414 * HPLL frequency is known to be device-specific, but we don't
1415 * have specs yet for exactly how it varies. Default to
1416 * BYT-CR but let provisioning set it via EFI variable
1417 */
1418 isp->hpll_freq = gmin_get_var_int(&pdev->dev, false, "HpllFreq", HPLL_FREQ_2000MHZ);
1419
1420 /*
1421 * for BYT/CHT we are put isp into D3cold to avoid pci registers access
1422 * in power off. Set d3cold_delay to 0 since default 100ms is not
1423 * necessary.
1424 */
1425 pdev->d3cold_delay = 0;
1426 break;
1427 case ATOMISP_PCI_DEVICE_SOC_ANN:
1428 isp->media_dev.hw_revision = ( ATOMISP_HW_REVISION_ISP2401
1429 << ATOMISP_HW_REVISION_SHIFT);
1430 isp->media_dev.hw_revision |= pdev->revision < 2 ?
1431 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0;
1432 isp->dfs = &dfs_config_merr;
1433 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1434 break;
1435 case ATOMISP_PCI_DEVICE_SOC_CHT:
1436 isp->media_dev.hw_revision = ( ATOMISP_HW_REVISION_ISP2401
1437 << ATOMISP_HW_REVISION_SHIFT);
1438 isp->media_dev.hw_revision |= pdev->revision < 2 ?
1439 ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0;
1440
1441 isp->dfs = &dfs_config_cht;
1442 pdev->d3cold_delay = 0;
1443
1444 iosf_mbi_read(BT_MBI_UNIT_CCK, MBI_REG_READ, CCK_FUSE_REG_0, &val);
1445 switch (val & CCK_FUSE_HPLL_FREQ_MASK) {
1446 case 0x00:
1447 isp->hpll_freq = HPLL_FREQ_800MHZ;
1448 break;
1449 case 0x01:
1450 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1451 break;
1452 case 0x02:
1453 isp->hpll_freq = HPLL_FREQ_2000MHZ;
1454 break;
1455 default:
1456 isp->hpll_freq = HPLL_FREQ_1600MHZ;
1457 dev_warn(&pdev->dev, "read HPLL from cck failed. Default to 1600 MHz.\n");
1458 }
1459 break;
1460 default:
1461 dev_err(&pdev->dev, "un-supported IUNIT device\n");
1462 err = -ENODEV;
1463 goto atomisp_dev_alloc_fail;
1464 }
1465
1466 dev_info(&pdev->dev, "ISP HPLL frequency base = %d MHz\n", isp->hpll_freq);
1467
1468 isp->max_isr_latency = ATOMISP_MAX_ISR_LATENCY;
1469
1470 /* Load isp firmware from user space */
1471 isp->firmware = atomisp_load_firmware(isp);
1472 if (!isp->firmware) {
1473 err = -ENOENT;
1474 dev_dbg(&pdev->dev, "Firmware load failed\n");
1475 goto load_fw_fail;
1476 }
1477
1478 err = sh_css_check_firmware_version(isp->dev, isp->firmware->data);
1479 if (err) {
1480 dev_dbg(&pdev->dev, "Firmware version check failed\n");
1481 goto fw_validation_fail;
1482 }
1483
1484 pci_set_master(pdev);
1485
1486 err = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1487 if (err < 0) {
1488 dev_err(&pdev->dev, "Failed to enable msi (%d)\n", err);
1489 goto enable_msi_fail;
1490 }
1491
1492 atomisp_msi_irq_init(isp);
1493
1494 cpu_latency_qos_add_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE);
1495
1496 /*
1497 * for MRFLD, Software/firmware needs to write a 1 to bit 0 of
1498 * the register at CSI_RECEIVER_SELECTION_REG to enable SH CSI
1499 * backend write 0 will enable Arasan CSI backend, which has
1500 * bugs(like sighting:4567697 and 4567699) and will be removed
1501 * in B0
1502 */
1503 atomisp_css2_hw_store_32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1);
1504
1505 if ((id->device & ATOMISP_PCI_DEVICE_SOC_MASK) ==
1506 ATOMISP_PCI_DEVICE_SOC_MRFLD) {
1507 u32 csi_afe_trim;
1508
1509 /*
1510 * Workaround for imbalance data eye issue which is observed
1511 * on TNG B0.
1512 */
1513 pci_read_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, &csi_afe_trim);
1514 csi_afe_trim &= ~((MRFLD_PCI_CSI_HSRXCLKTRIM_MASK <<
1515 MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) |
1516 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK <<
1517 MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) |
1518 (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK <<
1519 MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT));
1520 csi_afe_trim |= (MRFLD_PCI_CSI1_HSRXCLKTRIM <<
1521 MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) |
1522 (MRFLD_PCI_CSI2_HSRXCLKTRIM <<
1523 MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) |
1524 (MRFLD_PCI_CSI3_HSRXCLKTRIM <<
1525 MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT);
1526 pci_write_config_dword(pdev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, csi_afe_trim);
1527 }
1528
1529 err = atomisp_initialize_modules(isp);
1530 if (err < 0) {
1531 dev_err(&pdev->dev, "atomisp_initialize_modules (%d)\n", err);
1532 goto initialize_modules_fail;
1533 }
1534
1535 err = atomisp_register_entities(isp);
1536 if (err < 0) {
1537 dev_err(&pdev->dev, "atomisp_register_entities failed (%d)\n", err);
1538 goto register_entities_fail;
1539 }
1540
1541 INIT_WORK(&isp->assert_recovery_work, atomisp_assert_recovery_work);
1542
1543 /* save the iunit context only once after all the values are init'ed. */
1544 atomisp_save_iunit_reg(isp);
1545
1546 /*
1547 * The atomisp does not use standard PCI power-management through the
1548 * PCI config space. Instead this driver directly tells the P-Unit to
1549 * disable the ISP over the IOSF. The standard PCI subsystem pm_ops will
1550 * try to access the config space before (resume) / after (suspend) this
1551 * driver has turned the ISP on / off, resulting in the following errors:
1552 *
1553 * "Unable to change power state from D0 to D3hot, device inaccessible"
1554 * "Unable to change power state from D3cold to D0, device inaccessible"
1555 *
1556 * To avoid these errors override the pm_domain so that all the PCI
1557 * subsys suspend / resume handling is skipped.
1558 */
1559 isp->pm_domain.ops.runtime_suspend = atomisp_power_off;
1560 isp->pm_domain.ops.runtime_resume = atomisp_power_on;
1561 isp->pm_domain.ops.suspend = atomisp_suspend;
1562 isp->pm_domain.ops.resume = atomisp_resume;
1563
1564 dev_pm_domain_set(&pdev->dev, &isp->pm_domain);
1565
1566 pm_runtime_put_noidle(&pdev->dev);
1567 pm_runtime_allow(&pdev->dev);
1568
1569 /* Init ISP memory management */
1570 hmm_init();
1571
1572 err = devm_request_threaded_irq(&pdev->dev, pdev->irq,
1573 atomisp_isr, atomisp_isr_thread,
1574 IRQF_SHARED, "isp_irq", isp);
1575 if (err) {
1576 dev_err(&pdev->dev, "Failed to request irq (%d)\n", err);
1577 goto request_irq_fail;
1578 }
1579
1580 /* Load firmware into ISP memory */
1581 err = atomisp_css_load_firmware(isp);
1582 if (err) {
1583 dev_err(&pdev->dev, "Failed to init css.\n");
1584 goto css_init_fail;
1585 }
1586 /* Clear FW image from memory */
1587 release_firmware(isp->firmware);
1588 isp->firmware = NULL;
1589 isp->css_env.isp_css_fw.data = NULL;
1590
1591 err = atomisp_register_device_nodes(isp);
1592 if (err)
1593 goto css_init_fail;
1594
1595 atomisp_drvfs_init(isp);
1596
1597 return 0;
1598
1599 css_init_fail:
1600 devm_free_irq(&pdev->dev, pdev->irq, isp);
1601 request_irq_fail:
1602 hmm_cleanup();
1603 pm_runtime_get_noresume(&pdev->dev);
1604 dev_pm_domain_set(&pdev->dev, NULL);
1605 atomisp_unregister_entities(isp);
1606 register_entities_fail:
1607 atomisp_uninitialize_modules(isp);
1608 initialize_modules_fail:
1609 cpu_latency_qos_remove_request(&isp->pm_qos);
1610 atomisp_msi_irq_uninit(isp);
1611 pci_free_irq_vectors(pdev);
1612 enable_msi_fail:
1613 fw_validation_fail:
1614 release_firmware(isp->firmware);
1615 load_fw_fail:
1616 /*
1617 * Switch off ISP, as keeping it powered on would prevent
1618 * reaching S0ix states.
1619 *
1620 * The following lines have been copied from atomisp suspend path
1621 */
1622
1623 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
1624 irq &= BIT(INTR_IIR);
1625 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
1626
1627 pci_read_config_dword(pdev, PCI_INTERRUPT_CTRL, &irq);
1628 irq &= ~BIT(INTR_IER);
1629 pci_write_config_dword(pdev, PCI_INTERRUPT_CTRL, irq);
1630
1631 atomisp_msi_irq_uninit(isp);
1632
1633 /* Address later when we worry about the ...field chips */
1634 if (IS_ENABLED(CONFIG_PM) && atomisp_mrfld_power(isp, false))
1635 dev_err(&pdev->dev, "Failed to switch off ISP\n");
1636
1637 atomisp_dev_alloc_fail:
1638 pcim_iounmap_regions(pdev, BIT(ATOM_ISP_PCI_BAR));
1639
1640 ioremap_fail:
1641 return err;
1642 }
1643
atomisp_pci_remove(struct pci_dev * pdev)1644 static void atomisp_pci_remove(struct pci_dev *pdev)
1645 {
1646 struct atomisp_device *isp = pci_get_drvdata(pdev);
1647
1648 dev_info(&pdev->dev, "Removing atomisp driver\n");
1649
1650 atomisp_drvfs_exit();
1651
1652 ia_css_unload_firmware();
1653 hmm_cleanup();
1654
1655 pm_runtime_forbid(&pdev->dev);
1656 pm_runtime_get_noresume(&pdev->dev);
1657 dev_pm_domain_set(&pdev->dev, NULL);
1658 cpu_latency_qos_remove_request(&isp->pm_qos);
1659
1660 atomisp_msi_irq_uninit(isp);
1661 atomisp_unregister_entities(isp);
1662
1663 release_firmware(isp->firmware);
1664 }
1665
1666 static const struct pci_device_id atomisp_pci_tbl[] = {
1667 /* Merrifield */
1668 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD)},
1669 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_1179)},
1670 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_MRFLD_117A)},
1671 /* Baytrail */
1672 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_BYT)},
1673 /* Anniedale (Merrifield+ / Moorefield) */
1674 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_ANN)},
1675 /* Cherrytrail */
1676 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, ATOMISP_PCI_DEVICE_SOC_CHT)},
1677 {0,}
1678 };
1679
1680 MODULE_DEVICE_TABLE(pci, atomisp_pci_tbl);
1681
1682
1683 static struct pci_driver atomisp_pci_driver = {
1684 .name = "atomisp-isp2",
1685 .id_table = atomisp_pci_tbl,
1686 .probe = atomisp_pci_probe,
1687 .remove = atomisp_pci_remove,
1688 };
1689
1690 module_pci_driver(atomisp_pci_driver);
1691
1692 MODULE_AUTHOR("Wen Wang <wen.w.wang@intel.com>");
1693 MODULE_AUTHOR("Xiaolin Zhang <xiaolin.zhang@intel.com>");
1694 MODULE_LICENSE("GPL");
1695 MODULE_DESCRIPTION("Intel ATOM Platform ISP Driver");
1696