1 /*
2 * Standalone EHCI USB debug driver
3 *
4 * Hardware interface code based on the respective early console driver in
5 * Linux; see the Linux source for authorship and copyrights.
6 */
7
8 #include <xen/console.h>
9 #include <xen/delay.h>
10 #include <xen/errno.h>
11 #include <xen/pci.h>
12 #include <xen/serial.h>
13 #include <asm/byteorder.h>
14 #include <asm/io.h>
15 #include <asm/fixmap.h>
16 #include <public/physdev.h>
17
18 /* #define DBGP_DEBUG */
19
20 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
21
22 /* Section 2.2 Host Controller Capability Registers */
23 struct ehci_caps {
24 /*
25 * These fields are specified as 8 and 16 bit registers,
26 * but some hosts can't perform 8 or 16 bit PCI accesses.
27 * some hosts treat caplength and hciversion as parts of a 32-bit
28 * register, others treat them as two separate registers, this
29 * affects the memory map for big endian controllers.
30 */
31 u32 hc_capbase;
32 #define HC_LENGTH(p) (0x00ff & (p)) /* bits 7:0 / offset 0x00 */
33 #define HC_VERSION(p) (0xffff & ((p) >> 16)) /* bits 31:16 / offset 0x02 */
34
35 u32 hcs_params; /* HCSPARAMS - offset 0x04 */
36 #define HCS_DEBUG_PORT(p) (((p) >> 20) & 0xf) /* bits 23:20, debug port? */
37 #define HCS_INDICATOR(p) ((p) & (1 << 16)) /* true: has port indicators */
38 #define HCS_N_CC(p) (((p) >> 12) & 0xf) /* bits 15:12, #companion HCs */
39 #define HCS_N_PCC(p) (((p) >> 8) & 0xf) /* bits 11:8, ports per CC */
40 #define HCS_PORTROUTED(p) ((p) & (1 << 7)) /* true: port routing */
41 #define HCS_PPC(p) ((p) & (1 << 4)) /* true: port power control */
42 #define HCS_N_PORTS(p) (((p) >> 0) & 0xf) /* bits 3:0, ports on HC */
43
44 u32 hcc_params; /* HCCPARAMS - offset 0x08 */
45 /* EHCI 1.1 addendum */
46 #define HCC_32FRAME_PERIODIC_LIST(p) ((p) & (1 << 19))
47 #define HCC_PER_PORT_CHANGE_EVENT(p) ((p) & (1 << 18))
48 #define HCC_LPM(p) ((p) & (1 << 17))
49 #define HCC_HW_PREFETCH(p) ((p) & (1 << 16))
50 #define HCC_EXT_CAPS(p) (((p) >> 8) & 0xff) /* for pci extended caps */
51 #define HCC_ISOC_CACHE(p) ((p) & (1 << 7)) /* true: can cache isoc frame */
52 #define HCC_ISOC_THRES(p) (((p) >> 4) & 0x7) /* bits 6:4, uframes cached */
53 #define HCC_CANPARK(p) ((p) & (1 << 2)) /* true: can park on async qh */
54 #define HCC_PGM_FRAMELISTLEN(p) ((p) & (1 << 1)) /* true: periodic_size changes */
55 #define HCC_64BIT_ADDR(p) ((p) & 1) /* true: can use 64-bit addr */
56
57 u8 portroute[8]; /* nibbles for routing - offset 0x0C */
58 };
59
60 /* Section 2.3 Host Controller Operational Registers */
61 struct ehci_regs {
62 /* USBCMD: offset 0x00 */
63 u32 command;
64
65 /* EHCI 1.1 addendum */
66 #define CMD_HIRD (0xf << 24) /* host initiated resume duration */
67 #define CMD_PPCEE (1 << 15) /* per port change event enable */
68 #define CMD_FSP (1 << 14) /* fully synchronized prefetch */
69 #define CMD_ASPE (1 << 13) /* async schedule prefetch enable */
70 #define CMD_PSPE (1 << 12) /* periodic schedule prefetch enable */
71 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
72 #define CMD_PARK (1 << 11) /* enable "park" on async qh */
73 #define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park for */
74 #define CMD_LRESET (1 << 7) /* partial reset (no ports, etc) */
75 #define CMD_IAAD (1 << 6) /* "doorbell" interrupt async advance */
76 #define CMD_ASE (1 << 5) /* async schedule enable */
77 #define CMD_PSE (1 << 4) /* periodic schedule enable */
78 /* 3:2 is periodic frame list size */
79 #define CMD_RESET (1 << 1) /* reset HC not bus */
80 #define CMD_RUN (1 << 0) /* start/stop HC */
81
82 /* USBSTS: offset 0x04 */
83 u32 status;
84 #define STS_PPCE_MASK (0xff << 16) /* Per-Port change event 1-16 */
85 #define STS_ASS (1 << 15) /* Async Schedule Status */
86 #define STS_PSS (1 << 14) /* Periodic Schedule Status */
87 #define STS_RECL (1 << 13) /* Reclamation */
88 #define STS_HALT (1 << 12) /* Not running (any reason) */
89 /* some bits reserved */
90 /* these STS_* flags are also intr_enable bits (USBINTR) */
91 #define STS_IAA (1 << 5) /* Interrupted on async advance */
92 #define STS_FATAL (1 << 4) /* such as some PCI access errors */
93 #define STS_FLR (1 << 3) /* frame list rolled over */
94 #define STS_PCD (1 << 2) /* port change detect */
95 #define STS_ERR (1 << 1) /* "error" completion (overflow, ...) */
96 #define STS_INT (1 << 0) /* "normal" completion (short, ...) */
97
98 /* USBINTR: offset 0x08 */
99 u32 intr_enable;
100
101 /* FRINDEX: offset 0x0C */
102 u32 frame_index; /* current microframe number */
103 /* CTRLDSSEGMENT: offset 0x10 */
104 u32 segment; /* address bits 63:32 if needed */
105 /* PERIODICLISTBASE: offset 0x14 */
106 u32 frame_list; /* points to periodic list */
107 /* ASYNCLISTADDR: offset 0x18 */
108 u32 async_next; /* address of next async queue head */
109
110 u32 reserved[9];
111
112 /* CONFIGFLAG: offset 0x40 */
113 u32 configured_flag;
114 #define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
115
116 /* PORTSC: offset 0x44 */
117 u32 port_status[0]; /* up to N_PORTS */
118 /* EHCI 1.1 addendum */
119 #define PORTSC_SUSPEND_STS_ACK 0
120 #define PORTSC_SUSPEND_STS_NYET 1
121 #define PORTSC_SUSPEND_STS_STALL 2
122 #define PORTSC_SUSPEND_STS_ERR 3
123
124 #define PORT_DEV_ADDR (0x7f << 25) /* device address */
125 #define PORT_SSTS (0x3 << 23) /* suspend status */
126 /* 31:23 reserved */
127 #define PORT_WKOC_E (1 << 22) /* wake on overcurrent (enable) */
128 #define PORT_WKDISC_E (1 << 21) /* wake on disconnect (enable) */
129 #define PORT_WKCONN_E (1 << 20) /* wake on connect (enable) */
130 /* 19:16 for port testing */
131 #define PORT_TEST(x) (((x) & 0xf) << 16) /* Port Test Control */
132 #define PORT_TEST_PKT PORT_TEST(0x4) /* Port Test Control - packet test */
133 #define PORT_TEST_FORCE PORT_TEST(0x5) /* Port Test Control - force enable */
134 #define PORT_LED_OFF (0 << 14)
135 #define PORT_LED_AMBER (1 << 14)
136 #define PORT_LED_GREEN (2 << 14)
137 #define PORT_LED_MASK (3 << 14)
138 #define PORT_OWNER (1 << 13) /* true: companion hc owns this port */
139 #define PORT_POWER (1 << 12) /* true: has power (see PPC) */
140 #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
141 /* 11:10 for detecting lowspeed devices (reset vs release ownership) */
142 /* 9 reserved */
143 #define PORT_LPM (1 << 9) /* LPM transaction */
144 #define PORT_RESET (1 << 8) /* reset port */
145 #define PORT_SUSPEND (1 << 7) /* suspend port */
146 #define PORT_RESUME (1 << 6) /* resume it */
147 #define PORT_OCC (1 << 5) /* over current change */
148 #define PORT_OC (1 << 4) /* over current active */
149 #define PORT_PEC (1 << 3) /* port enable change */
150 #define PORT_PE (1 << 2) /* port enable */
151 #define PORT_CSC (1 << 1) /* connect status change */
152 #define PORT_CONNECT (1 << 0) /* device connected */
153 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
154 };
155
156 /*
157 * Appendix C, Debug port ... intended for use with special "debug devices"
158 * that can help if there's no serial console. (nonstandard enumeration.)
159 */
160 struct ehci_dbg_port {
161 u32 control;
162 #define DBGP_OWNER (1 << 30)
163 #define DBGP_ENABLED (1 << 28)
164 #define DBGP_DONE (1 << 16)
165 #define DBGP_INUSE (1 << 10)
166 #define DBGP_ERRCODE(x) (((x) >> 7) & 0x07)
167 # define DBGP_ERR_BAD 1
168 # define DBGP_ERR_SIGNAL 2
169 #define DBGP_ERROR (1 << 6)
170 #define DBGP_GO (1 << 5)
171 #define DBGP_OUT (1 << 4)
172 #define DBGP_LEN (0xf << 0)
173 #define DBGP_CLAIM (DBGP_OWNER | DBGP_ENABLED | DBGP_INUSE)
174 u32 pids;
175 #define DBGP_PID_GET(x) (((x) >> 16) & 0xff)
176 #define DBGP_PID_SET(data, tok) (((data) << 8) | (tok))
177 u32 data03;
178 u32 data47;
179 u32 address;
180 #define DBGP_EPADDR(dev, ep) (((dev) << 8) | (ep))
181 };
182
183 /* CONTROL REQUEST SUPPORT */
184
185 /*
186 * USB directions
187 *
188 * This bit flag is used in endpoint descriptors' bEndpointAddress field.
189 * It's also one of three fields in control requests bRequestType.
190 */
191 #define USB_DIR_OUT 0 /* to device */
192 #define USB_DIR_IN 0x80 /* to host */
193
194 /*
195 * USB types, the second of three bRequestType fields
196 */
197 #define USB_TYPE_MASK (0x03 << 5)
198 #define USB_TYPE_STANDARD (0x00 << 5)
199 #define USB_TYPE_CLASS (0x01 << 5)
200 #define USB_TYPE_VENDOR (0x02 << 5)
201 #define USB_TYPE_RESERVED (0x03 << 5)
202
203 /*
204 * USB recipients, the third of three bRequestType fields
205 */
206 #define USB_RECIP_MASK 0x1f
207 #define USB_RECIP_DEVICE 0x00
208 #define USB_RECIP_INTERFACE 0x01
209 #define USB_RECIP_ENDPOINT 0x02
210 #define USB_RECIP_OTHER 0x03
211 /* From Wireless USB 1.0 */
212 #define USB_RECIP_PORT 0x04
213 #define USB_RECIP_RPIPE 0x05
214
215 /*
216 * Standard requests, for the bRequest field of a SETUP packet.
217 *
218 * These are qualified by the bRequestType field, so that for example
219 * TYPE_CLASS or TYPE_VENDOR specific feature flags could be retrieved
220 * by a GET_STATUS request.
221 */
222 #define USB_REQ_GET_STATUS 0x00
223 #define USB_REQ_CLEAR_FEATURE 0x01
224 #define USB_REQ_SET_FEATURE 0x03
225 #define USB_REQ_SET_ADDRESS 0x05
226 #define USB_REQ_GET_DESCRIPTOR 0x06
227 #define USB_REQ_SET_DESCRIPTOR 0x07
228 #define USB_REQ_GET_CONFIGURATION 0x08
229 #define USB_REQ_SET_CONFIGURATION 0x09
230 #define USB_REQ_GET_INTERFACE 0x0A
231 #define USB_REQ_SET_INTERFACE 0x0B
232 #define USB_REQ_SYNCH_FRAME 0x0C
233
234 #define USB_DEVICE_DEBUG_MODE 6 /* (special devices only) */
235
236 /**
237 * struct usb_ctrlrequest - SETUP data for a USB device control request
238 * @bRequestType: matches the USB bmRequestType field
239 * @bRequest: matches the USB bRequest field
240 * @wValue: matches the USB wValue field (le16 byte order)
241 * @wIndex: matches the USB wIndex field (le16 byte order)
242 * @wLength: matches the USB wLength field (le16 byte order)
243 *
244 * This structure is used to send control requests to a USB device. It matches
245 * the different fields of the USB 2.0 Spec section 9.3, table 9-2. See the
246 * USB spec for a fuller description of the different fields, and what they are
247 * used for.
248 *
249 * Note that the driver for any interface can issue control requests.
250 * For most devices, interfaces don't coordinate with each other, so
251 * such requests may be made at any time.
252 */
253 struct __packed usb_ctrlrequest {
254 u8 bRequestType;
255 u8 bRequest;
256 __le16 wValue;
257 __le16 wIndex;
258 __le16 wLength;
259 };
260
261 /* USB_DT_DEBUG: for special highspeed devices, replacing serial console */
262
263 #define USB_DT_DEBUG 0x0a
264
265 struct __packed usb_debug_descriptor {
266 u8 bLength;
267 u8 bDescriptorType;
268 /* bulk endpoints with 8 byte maxpacket */
269 u8 bDebugInEndpoint;
270 u8 bDebugOutEndpoint;
271 };
272
273 #define USB_DEBUG_DEVNUM 127
274
275 /*
276 * USB Packet IDs (PIDs)
277 */
278
279 /* token */
280 #define USB_PID_OUT 0xe1
281 #define USB_PID_IN 0x69
282 #define USB_PID_SOF 0xa5
283 #define USB_PID_SETUP 0x2d
284 /* handshake */
285 #define USB_PID_ACK 0xd2
286 #define USB_PID_NAK 0x5a
287 #define USB_PID_STALL 0x1e
288 #define USB_PID_NYET 0x96
289 /* data */
290 #define USB_PID_DATA0 0xc3
291 #define USB_PID_DATA1 0x4b
292 #define USB_PID_DATA2 0x87
293 #define USB_PID_MDATA 0x0f
294 /* Special */
295 #define USB_PID_PREAMBLE 0x3c
296 #define USB_PID_ERR 0x3c
297 #define USB_PID_SPLIT 0x78
298 #define USB_PID_PING 0xb4
299 #define USB_PID_UNDEF_0 0xf0
300
301 #define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320
302 #define PCI_CAP_ID_EHCI_DEBUG 0x0a
303
304 #define HUB_ROOT_RESET_TIME 50 /* times are in msec */
305 #define HUB_SHORT_RESET_TIME 10
306 #define HUB_LONG_RESET_TIME 200
307 #define HUB_RESET_TIMEOUT 500
308
309 #define DBGP_MAX_PACKET 8
310 #define DBGP_LOOPS 1000
311 #define DBGP_TIMEOUT (250 * 1000) /* us */
312 #define DBGP_CHECK_INTERVAL 100 /* us */
313 /* This one can be set arbitrarily - only affects input responsiveness: */
314 #define DBGP_IDLE_INTERVAL 100 /* ms */
315
316 struct ehci_dbgp {
317 struct ehci_dbg_port __iomem *ehci_debug;
318 enum dbgp_state {
319 dbgp_idle,
320 dbgp_out,
321 dbgp_in,
322 dbgp_ctrl,
323 dbgp_unsafe /* cannot use debug device during EHCI reset */
324 } state;
325 unsigned int phys_port;
326 struct {
327 unsigned int endpoint;
328 unsigned int chunk;
329 char buf[DBGP_MAX_PACKET];
330 } out, in;
331 unsigned long timeout;
332 struct timer timer;
333 spinlock_t *lock;
334 bool_t reset_run;
335 u8 bus, slot, func, bar;
336 u16 pci_cr;
337 u32 bar_val;
338 unsigned int cap;
339 struct ehci_regs __iomem *ehci_regs;
340 struct ehci_caps __iomem *ehci_caps;
341 };
342
343 static int ehci_dbgp_external_startup(struct ehci_dbgp *);
344
ehci_dbgp_status(struct ehci_dbgp * dbgp,const char * str)345 static void ehci_dbgp_status(struct ehci_dbgp *dbgp, const char *str)
346 {
347 #ifdef DBGP_DEBUG
348 #define dbgp_printk printk
349 if ( !dbgp->ehci_debug )
350 return;
351 dbgp_printk("dbgp: %s\n", str);
352 dbgp_printk(" debug control: %08x\n", readl(&dbgp->ehci_debug->control));
353 dbgp_printk(" EHCI cmd : %08x\n", readl(&dbgp->ehci_regs->command));
354 dbgp_printk(" EHCI conf flg: %08x\n",
355 readl(&dbgp->ehci_regs->configured_flag));
356 dbgp_printk(" EHCI status : %08x\n", readl(&dbgp->ehci_regs->status));
357 dbgp_printk(" EHCI portsc : %08x\n",
358 readl(&dbgp->ehci_regs->port_status[dbgp->phys_port - 1]));
359 #endif
360 }
361
362 #ifndef DBGP_DEBUG
363 static inline __attribute__ ((format (printf, 1, 2))) void
dbgp_printk(const char * fmt,...)364 dbgp_printk(const char *fmt, ...) { }
365 #endif
366
dbgp_len_update(u32 x,u32 len)367 static inline u32 dbgp_len_update(u32 x, u32 len)
368 {
369 return (x & ~DBGP_LEN) | (len & DBGP_LEN) | DBGP_OUT;
370 }
371
dbgp_pid_write_update(u32 x,u32 tok)372 static inline u32 dbgp_pid_write_update(u32 x, u32 tok)
373 {
374 static u8 data0 = USB_PID_DATA1;
375
376 data0 ^= USB_PID_DATA0 ^ USB_PID_DATA1;
377 return (x & 0xffff0000) | (data0 << 8) | (tok & 0xff);
378 }
379
dbgp_pid_read_update(u32 x,u32 tok)380 static inline u32 dbgp_pid_read_update(u32 x, u32 tok)
381 {
382 return (x & 0xffffff00) | (tok & 0xff);
383 }
384
dbgp_set_data(struct ehci_dbg_port __iomem * ehci_debug,const void * buf,unsigned int size)385 static inline void dbgp_set_data(struct ehci_dbg_port __iomem *ehci_debug,
386 const void *buf, unsigned int size)
387 {
388 const unsigned char *bytes = buf;
389 u32 lo = 0, hi = 0;
390 unsigned int i;
391
392 for ( i = 0; i < 4 && i < size; i++ )
393 lo |= bytes[i] << (8 * i);
394 for ( ; i < 8 && i < size; i++ )
395 hi |= bytes[i] << (8 * (i - 4));
396 writel(lo, &ehci_debug->data03);
397 writel(hi, &ehci_debug->data47);
398 }
399
dbgp_get_data(struct ehci_dbg_port __iomem * ehci_debug,void * buf,int size)400 static inline void dbgp_get_data(struct ehci_dbg_port __iomem *ehci_debug,
401 void *buf, int size)
402 {
403 unsigned char *bytes = buf;
404 u32 lo = readl(&ehci_debug->data03);
405 u32 hi = readl(&ehci_debug->data47);
406 unsigned int i;
407
408 for ( i = 0; i < 4 && i < size; i++ )
409 bytes[i] = (lo >> (8 * i)) & 0xff;
410 for ( ; i < 8 && i < size; i++ )
411 bytes[i] = (hi >> (8 * (i - 4))) & 0xff;
412 }
413
dbgp_issue_command(struct ehci_dbgp * dbgp,u32 ctrl,enum dbgp_state state)414 static void dbgp_issue_command(struct ehci_dbgp *dbgp, u32 ctrl,
415 enum dbgp_state state)
416 {
417 u32 cmd = readl(&dbgp->ehci_regs->command);
418
419 if ( unlikely(!(cmd & CMD_RUN)) )
420 {
421 /*
422 * If the EHCI controller is not in the run state do extended
423 * checks to see if ACPI or some other initialization also
424 * reset the EHCI debug port.
425 */
426 u32 ctrl = readl(&dbgp->ehci_debug->control);
427
428 if ( ctrl & DBGP_ENABLED )
429 {
430 cmd |= CMD_RUN;
431 writel(cmd, &dbgp->ehci_regs->command);
432 dbgp->reset_run = 1;
433 }
434 else if ( dbgp->state != dbgp_unsafe )
435 {
436 dbgp->state = dbgp_unsafe;
437 ehci_dbgp_external_startup(dbgp);
438 }
439 }
440
441 writel(ctrl | DBGP_GO, &dbgp->ehci_debug->control);
442 dbgp->timeout = DBGP_TIMEOUT;
443 if ( dbgp->state != dbgp_unsafe )
444 dbgp->state = state;
445 }
446
dbgp_check_for_completion(struct ehci_dbgp * dbgp,unsigned int interval,u8 * ppid)447 static int dbgp_check_for_completion(struct ehci_dbgp *dbgp,
448 unsigned int interval, u8 *ppid)
449 {
450 u32 ctrl;
451 int ret;
452
453 if ( dbgp->state == dbgp_idle )
454 return 0;
455
456 ctrl = readl(&dbgp->ehci_debug->control) & ~DBGP_GO;
457 if ( !(ctrl & DBGP_DONE) )
458 {
459 if ( dbgp->timeout > interval )
460 dbgp->timeout -= interval;
461 else if ( interval )
462 {
463 /* See the timeout related comment in dbgp_wait_until_done(). */
464 dbgp->state = dbgp_unsafe;
465 dbgp->timeout = 0;
466 }
467 return -DBGP_TIMEOUT;
468 }
469
470 if ( ctrl & DBGP_ERROR )
471 {
472 ret = -DBGP_ERRCODE(ctrl);
473 if ( ret == -DBGP_ERR_BAD && dbgp->timeout > interval )
474 ctrl |= DBGP_GO;
475 }
476 else
477 {
478 u8 pid = DBGP_PID_GET(readl(&dbgp->ehci_debug->pids));
479
480 ret = ctrl & DBGP_LEN;
481 if ( ppid )
482 *ppid = pid;
483 else if ( dbgp->state == dbgp_in )
484 {
485 dbgp_get_data(dbgp->ehci_debug, dbgp->in.buf, ret);
486 dbgp->in.chunk = ret;
487 }
488 else if ( pid == USB_PID_NAK && dbgp->timeout > interval )
489 ctrl |= DBGP_GO;
490 }
491
492 writel(ctrl, &dbgp->ehci_debug->control);
493 if ( ctrl & DBGP_GO )
494 {
495 dbgp->timeout -= interval;
496 return -DBGP_TIMEOUT;
497 }
498
499 if ( unlikely(dbgp->reset_run) )
500 {
501 writel(readl(&dbgp->ehci_regs->command) & ~CMD_RUN,
502 &dbgp->ehci_regs->command);
503 dbgp->reset_run = 0;
504 }
505
506 if ( dbgp->state != dbgp_unsafe )
507 dbgp->state = dbgp_idle;
508
509 return ret;
510 }
511
dbgp_wait_until_complete(struct ehci_dbgp * dbgp,u8 * ppid)512 static int dbgp_wait_until_complete(struct ehci_dbgp *dbgp, u8 *ppid)
513 {
514 unsigned int loop = DBGP_TIMEOUT;
515 int ret;
516
517 do {
518 ret = dbgp_check_for_completion(dbgp, 0, ppid);
519 if ( ret != -DBGP_TIMEOUT )
520 break;
521 udelay(1);
522 } while ( --loop );
523
524 if ( !ppid && !loop )
525 dbgp->state = dbgp_unsafe;
526
527 return ret;
528 }
529
dbgp_mdelay(unsigned int ms)530 static inline void dbgp_mdelay(unsigned int ms)
531 {
532 while ( ms-- )
533 {
534 unsigned int i;
535
536 for ( i = 0; i < 1000; i++ )
537 outb(0x1, 0x80);
538 }
539 }
540
dbgp_breathe(void)541 static void dbgp_breathe(void)
542 {
543 /* Sleep to give the debug port a chance to breathe. */
544 dbgp_mdelay(1);
545 }
546
dbgp_wait_until_done(struct ehci_dbgp * dbgp,u32 ctrl,unsigned int loop)547 static int dbgp_wait_until_done(struct ehci_dbgp *dbgp, u32 ctrl,
548 unsigned int loop)
549 {
550 int ret;
551
552 dbgp->timeout = 0;
553
554 for ( ; ; writel(ctrl | DBGP_GO, &dbgp->ehci_debug->control) )
555 {
556 u8 pid;
557
558 ret = dbgp_wait_until_complete(dbgp, &pid);
559 if ( ret < 0 )
560 {
561 /*
562 * A -DBGP_TIMEOUT failure here means the device has failed,
563 * perhaps because it was unplugged, in which case we do not
564 * want to hang the system so the dbgp will be marked as unsafe
565 * to use. EHCI reset is the only way to recover if you unplug
566 * the dbgp device.
567 */
568 if ( ret == -DBGP_TIMEOUT )
569 dbgp->state = dbgp_unsafe;
570 if ( ret != -DBGP_ERR_BAD || !--loop )
571 break;
572 }
573 else
574 {
575 /*
576 * If the port is getting full or it has dropped data
577 * start pacing ourselves, not necessary but it's friendly.
578 */
579 if ( pid == USB_PID_NAK || pid == USB_PID_NYET )
580 dbgp_breathe();
581
582 /* If we got a NACK, reissue the transmission. */
583 if ( pid != USB_PID_NAK || !--loop )
584 break;
585 }
586 }
587
588 return ret;
589 }
590
dbgp_bulk_write(struct ehci_dbgp * dbgp,unsigned int devnum,unsigned int endpoint,const void * bytes,unsigned int size,u32 * pctrl)591 static int dbgp_bulk_write(struct ehci_dbgp *dbgp,
592 unsigned int devnum, unsigned int endpoint,
593 const void *bytes, unsigned int size, u32 *pctrl)
594 {
595 u32 addr, pids, ctrl;
596
597 if ( size > DBGP_MAX_PACKET )
598 return -EINVAL;
599
600 addr = DBGP_EPADDR(devnum, endpoint);
601 pids = dbgp_pid_write_update(readl(&dbgp->ehci_debug->pids), USB_PID_OUT);
602 ctrl = dbgp_len_update(readl(&dbgp->ehci_debug->control), size);
603 if ( pctrl )
604 *pctrl = ctrl;
605
606 dbgp_set_data(dbgp->ehci_debug, bytes, size);
607 writel(addr, &dbgp->ehci_debug->address);
608 writel(pids, &dbgp->ehci_debug->pids);
609 dbgp_issue_command(dbgp, ctrl, dbgp_out);
610
611 return 0;
612 }
613
dbgp_bulk_read(struct ehci_dbgp * dbgp,unsigned int devnum,unsigned int endpoint,unsigned int size,u32 * pctrl)614 static int dbgp_bulk_read(struct ehci_dbgp *dbgp,
615 unsigned int devnum, unsigned int endpoint,
616 unsigned int size, u32 *pctrl)
617 {
618 u32 addr, pids, ctrl;
619
620 if ( size > DBGP_MAX_PACKET )
621 return -EINVAL;
622
623 addr = DBGP_EPADDR(devnum, endpoint);
624 pids = dbgp_pid_read_update(readl(&dbgp->ehci_debug->pids), USB_PID_IN);
625 ctrl = readl(&dbgp->ehci_debug->control) & ~DBGP_OUT;
626
627 writel(addr, &dbgp->ehci_debug->address);
628 writel(pids, &dbgp->ehci_debug->pids);
629 if ( likely(!pctrl) )
630 dbgp_issue_command(dbgp, ctrl, dbgp_in);
631 else
632 dbgp_issue_command(dbgp, *pctrl = ctrl, dbgp_ctrl);
633
634 return 0;
635 }
636
dbgp_control_msg(struct ehci_dbgp * dbgp,unsigned int devnum,int requesttype,int request,int value,int index,void * data,unsigned int size)637 static int dbgp_control_msg(struct ehci_dbgp *dbgp, unsigned int devnum,
638 int requesttype, int request, int value,
639 int index, void *data, unsigned int size)
640 {
641 u32 addr, pids, ctrl;
642 struct usb_ctrlrequest req;
643 bool_t read = (requesttype & USB_DIR_IN) != 0;
644 int ret;
645
646 if ( size > (read ? DBGP_MAX_PACKET : 0) )
647 return -EINVAL;
648
649 /* Compute the control message */
650 req.bRequestType = requesttype;
651 req.bRequest = request;
652 req.wValue = cpu_to_le16(value);
653 req.wIndex = cpu_to_le16(index);
654 req.wLength = cpu_to_le16(size);
655
656 pids = DBGP_PID_SET(USB_PID_DATA0, USB_PID_SETUP);
657 addr = DBGP_EPADDR(devnum, 0);
658 ctrl = dbgp_len_update(readl(&dbgp->ehci_debug->control), sizeof(req));
659
660 /* Send the setup message */
661 dbgp_set_data(dbgp->ehci_debug, &req, sizeof(req));
662 writel(addr, &dbgp->ehci_debug->address);
663 writel(pids, &dbgp->ehci_debug->pids);
664 dbgp_issue_command(dbgp, ctrl, dbgp_ctrl);
665 ret = dbgp_wait_until_done(dbgp, ctrl, DBGP_LOOPS);
666 if ( ret < 0 )
667 return ret;
668
669 /* Read the result */
670 ret = dbgp_bulk_read(dbgp, devnum, 0, size, &ctrl);
671 if ( !ret )
672 ret = dbgp_wait_until_done(dbgp, ctrl, DBGP_LOOPS);
673 if ( ret > 0 )
674 {
675 if ( size > ret )
676 size = ret;
677 dbgp_get_data(dbgp->ehci_debug, data, size);
678 }
679
680 return ret;
681 }
682
__find_dbgp(u8 bus,u8 slot,u8 func)683 static unsigned int __init __find_dbgp(u8 bus, u8 slot, u8 func)
684 {
685 u32 class = pci_conf_read32(0, bus, slot, func, PCI_CLASS_REVISION);
686
687 if ( (class >> 8) != PCI_CLASS_SERIAL_USB_EHCI )
688 return 0;
689
690 return pci_find_cap_offset(0, bus, slot, func, PCI_CAP_ID_EHCI_DEBUG);
691 }
692
find_dbgp(struct ehci_dbgp * dbgp,unsigned int ehci_num)693 static unsigned int __init find_dbgp(struct ehci_dbgp *dbgp,
694 unsigned int ehci_num)
695 {
696 unsigned int bus, slot, func;
697
698 for ( bus = 0; bus < 256; bus++ )
699 {
700 for ( slot = 0; slot < 32; slot++ )
701 {
702 for ( func = 0; func < 8; func++ )
703 {
704 unsigned int cap;
705
706 if ( !pci_device_detect(0, bus, slot, func) )
707 {
708 if ( !func )
709 break;
710 continue;
711 }
712
713 cap = __find_dbgp(bus, slot, func);
714 if ( !cap || ehci_num-- )
715 {
716 if ( !func && !(pci_conf_read8(0, bus, slot, func,
717 PCI_HEADER_TYPE) & 0x80) )
718 break;
719 continue;
720 }
721
722 dbgp->bus = bus;
723 dbgp->slot = slot;
724 dbgp->func = func;
725 return cap;
726 }
727 }
728 }
729
730 return 0;
731 }
732
ehci_dbgp_startup(struct ehci_dbgp * dbgp)733 static int ehci_dbgp_startup(struct ehci_dbgp *dbgp)
734 {
735 u32 ctrl, cmd, status;
736 unsigned int loop;
737
738 /* Claim ownership, but do not enable yet */
739 ctrl = readl(&dbgp->ehci_debug->control);
740 ctrl |= DBGP_OWNER;
741 ctrl &= ~(DBGP_ENABLED | DBGP_INUSE);
742 writel(ctrl, &dbgp->ehci_debug->control);
743 udelay(1);
744
745 ehci_dbgp_status(dbgp, "EHCI startup");
746 /* Start the EHCI. */
747 cmd = readl(&dbgp->ehci_regs->command);
748 cmd &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | CMD_ASE | CMD_RESET);
749 cmd |= CMD_RUN;
750 writel(cmd, &dbgp->ehci_regs->command);
751
752 /* Ensure everything is routed to the EHCI */
753 writel(FLAG_CF, &dbgp->ehci_regs->configured_flag);
754
755 /* Wait until the controller is no longer halted. */
756 loop = 1000;
757 do {
758 status = readl(&dbgp->ehci_regs->status);
759 if ( !(status & STS_HALT) )
760 break;
761 udelay(1);
762 } while ( --loop );
763
764 if ( !loop )
765 {
766 dbgp_printk("EHCI cannot be started\n");
767 return -ENODEV;
768 }
769 dbgp_printk("EHCI started\n");
770
771 return 0;
772 }
773
ehci_dbgp_controller_reset(struct ehci_dbgp * dbgp)774 static int ehci_dbgp_controller_reset(struct ehci_dbgp *dbgp)
775 {
776 unsigned int loop = 250 * 1000;
777 u32 cmd;
778
779 /* Reset the EHCI controller */
780 cmd = readl(&dbgp->ehci_regs->command);
781 cmd |= CMD_RESET;
782 writel(cmd, &dbgp->ehci_regs->command);
783 do {
784 cmd = readl(&dbgp->ehci_regs->command);
785 } while ( (cmd & CMD_RESET) && --loop );
786
787 if ( !loop )
788 {
789 dbgp_printk("cannot reset EHCI\n");
790 return -1;
791 }
792 ehci_dbgp_status(dbgp, "ehci reset done");
793
794 return 0;
795 }
796
ehci_reset_port(struct ehci_dbgp * dbgp,unsigned int port)797 static int ehci_reset_port(struct ehci_dbgp *dbgp, unsigned int port)
798 {
799 u32 portsc, delay_time, delay;
800
801 ehci_dbgp_status(dbgp, "reset port");
802 /* Reset the USB debug port. */
803 portsc = readl(&dbgp->ehci_regs->port_status[port - 1]);
804 portsc &= ~PORT_PE;
805 portsc |= PORT_RESET;
806 writel(portsc, &dbgp->ehci_regs->port_status[port - 1]);
807
808 delay = HUB_ROOT_RESET_TIME;
809 for ( delay_time = 0; delay_time < HUB_RESET_TIMEOUT;
810 delay_time += delay )
811 {
812 dbgp_mdelay(delay);
813 portsc = readl(&dbgp->ehci_regs->port_status[port - 1]);
814 if (!(portsc & PORT_RESET))
815 break;
816 }
817
818 if ( portsc & PORT_RESET )
819 {
820 /* force reset to complete */
821 unsigned int loop = 100 * 1000;
822
823 writel(portsc & ~(PORT_RWC_BITS | PORT_RESET),
824 &dbgp->ehci_regs->port_status[port - 1]);
825 do {
826 udelay(1);
827 portsc = readl(&dbgp->ehci_regs->port_status[port-1]);
828 } while ( (portsc & PORT_RESET) && --loop );
829 }
830
831 /* Device went away? */
832 if ( !(portsc & PORT_CONNECT) )
833 return -ENOTCONN;
834
835 /* bomb out completely if something weird happened */
836 if ( portsc & PORT_CSC )
837 return -EINVAL;
838
839 /* If we've finished resetting, then break out of the loop */
840 if ( !(portsc & PORT_RESET) && (portsc & PORT_PE) )
841 return 0;
842
843 return -EBUSY;
844 }
845
ehci_wait_for_port(struct ehci_dbgp * dbgp,unsigned int port)846 static int ehci_wait_for_port(struct ehci_dbgp *dbgp, unsigned int port)
847 {
848 u32 status;
849 unsigned int reps;
850
851 for ( reps = 0; reps < 300; reps++ )
852 {
853 status = readl(&dbgp->ehci_regs->status);
854 if ( status & STS_PCD )
855 break;
856 dbgp_mdelay(1);
857 }
858
859 return ehci_reset_port(dbgp, port) == 0 ? 0 : -ENOTCONN;
860 }
861
862 /* Return 0 on success
863 * Return -ENODEV for any general failure
864 * Return -EIO if wait for port fails
865 */
ehci_dbgp_external_startup(struct ehci_dbgp * dbgp)866 static int ehci_dbgp_external_startup(struct ehci_dbgp *dbgp)
867 {
868 unsigned int devnum;
869 struct usb_debug_descriptor dbgp_desc;
870 int ret;
871 u32 ctrl, portsc, cmd;
872 unsigned int dbg_port = dbgp->phys_port;
873 unsigned int tries = 3;
874 unsigned int reset_port_tries = 1;
875 bool_t try_hard_once = 1;
876
877 try_port_reset_again:
878 ret = ehci_dbgp_startup(dbgp);
879 if ( ret )
880 return ret;
881
882 /* Wait for a device to show up in the debug port */
883 ret = ehci_wait_for_port(dbgp, dbg_port);
884 if ( ret < 0 )
885 {
886 portsc = readl(&dbgp->ehci_regs->port_status[dbg_port - 1]);
887 if ( !(portsc & PORT_CONNECT) && try_hard_once )
888 {
889 /*
890 * Last ditch effort to try to force enable the debug device by
891 * using the packet test EHCI command to try and wake it up.
892 */
893 try_hard_once = 0;
894 cmd = readl(&dbgp->ehci_regs->command);
895 cmd &= ~CMD_RUN;
896 writel(cmd, &dbgp->ehci_regs->command);
897 portsc = readl(&dbgp->ehci_regs->port_status[dbg_port - 1]);
898 portsc |= PORT_TEST_PKT;
899 writel(portsc, &dbgp->ehci_regs->port_status[dbg_port - 1]);
900 ehci_dbgp_status(dbgp, "Trying to force debug port online");
901 mdelay(50);
902 ehci_dbgp_controller_reset(dbgp);
903 goto try_port_reset_again;
904 }
905 else if ( reset_port_tries-- )
906 goto try_port_reset_again;
907 dbgp_printk("no device found in debug port\n");
908 return -EIO;
909 }
910 ehci_dbgp_status(dbgp, "wait for port done");
911
912 /* Enable the debug port */
913 ctrl = readl(&dbgp->ehci_debug->control);
914 ctrl |= DBGP_CLAIM;
915 writel(ctrl, &dbgp->ehci_debug->control);
916 ctrl = readl(&dbgp->ehci_debug->control);
917 if ( (ctrl & DBGP_CLAIM) != DBGP_CLAIM )
918 {
919 dbgp_printk("no device in debug port\n");
920 writel(ctrl & ~DBGP_CLAIM, &dbgp->ehci_debug->control);
921 return -ENODEV;
922 }
923 ehci_dbgp_status(dbgp, "debug port enabled");
924
925 /* Completely transfer the debug device to the debug controller */
926 portsc = readl(&dbgp->ehci_regs->port_status[dbg_port - 1]);
927 portsc &= ~PORT_PE;
928 writel(portsc, &dbgp->ehci_regs->port_status[dbg_port - 1]);
929
930 dbgp_mdelay(100);
931
932 try_again:
933 /* Find the debug device and make it device number 127 */
934 for ( devnum = 0; devnum <= 127; devnum++ )
935 {
936 ret = dbgp_control_msg(dbgp, devnum,
937 USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
938 USB_REQ_GET_DESCRIPTOR, (USB_DT_DEBUG << 8), 0,
939 &dbgp_desc, sizeof(dbgp_desc));
940 if ( ret > 0 )
941 break;
942 }
943 if ( devnum > 127 )
944 {
945 dbgp_printk("could not find attached debug device\n");
946 goto err;
947 }
948 dbgp->out.endpoint = dbgp_desc.bDebugOutEndpoint;
949 dbgp->in.endpoint = dbgp_desc.bDebugInEndpoint;
950
951 /* Move the device to 127 if it isn't already there. */
952 if ( devnum != USB_DEBUG_DEVNUM )
953 {
954 ret = dbgp_control_msg(dbgp, devnum,
955 USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
956 USB_REQ_SET_ADDRESS, USB_DEBUG_DEVNUM, 0, NULL, 0);
957 if ( ret < 0 )
958 {
959 dbgp_printk("could not move attached device to %d\n",
960 USB_DEBUG_DEVNUM);
961 goto err;
962 }
963 devnum = USB_DEBUG_DEVNUM;
964 dbgp_printk("debug device renamed to 127\n");
965 }
966
967 /* Enable the debug interface */
968 ret = dbgp_control_msg(dbgp, USB_DEBUG_DEVNUM,
969 USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE,
970 USB_REQ_SET_FEATURE, USB_DEVICE_DEBUG_MODE,
971 0, NULL, 0);
972 if ( ret < 0 )
973 {
974 dbgp_printk("could not enable the debug device\n");
975 goto err;
976 }
977 dbgp_printk("debug interface enabled\n");
978
979 /* Perform a small write to get the even/odd data state in sync. */
980 ret = dbgp_bulk_write(dbgp, USB_DEBUG_DEVNUM, dbgp->out.endpoint,
981 "\n", 1, &ctrl);
982 if ( !ret )
983 ret = dbgp_wait_until_done(dbgp, ctrl, DBGP_LOOPS);
984 if ( ret < 0 )
985 {
986 dbgp_printk("dbgp_bulk_write failed: %d\n", ret);
987 goto err;
988 }
989 dbgp_printk("small write done\n");
990 dbgp->state = dbgp_idle;
991
992 return 0;
993 err:
994 if ( tries-- )
995 goto try_again;
996 return -ENODEV;
997 }
998
999 typedef void (*set_debug_port_t)(struct ehci_dbgp *, unsigned int);
1000
default_set_debug_port(struct ehci_dbgp * dbgp,unsigned int port)1001 static void default_set_debug_port(struct ehci_dbgp *dbgp, unsigned int port)
1002 {
1003 }
1004
1005 static set_debug_port_t __read_mostly set_debug_port = default_set_debug_port;
1006
nvidia_set_debug_port(struct ehci_dbgp * dbgp,unsigned int port)1007 static void nvidia_set_debug_port(struct ehci_dbgp *dbgp, unsigned int port)
1008 {
1009 u32 dword = pci_conf_read32(0, dbgp->bus, dbgp->slot, dbgp->func, 0x74);
1010
1011 dword &= ~(0x0f << 12);
1012 dword |= (port & 0x0f) << 12;
1013 pci_conf_write32(0, dbgp->bus, dbgp->slot, dbgp->func, 0x74, dword);
1014 dbgp_printk("set debug port to %u\n", port);
1015 }
1016
detect_set_debug_port(struct ehci_dbgp * dbgp)1017 static void __init detect_set_debug_port(struct ehci_dbgp *dbgp)
1018 {
1019 if ( pci_conf_read16(0, dbgp->bus, dbgp->slot, dbgp->func,
1020 PCI_VENDOR_ID) == 0x10de )
1021 {
1022 dbgp_printk("using nvidia set_debug_port\n");
1023 set_debug_port = nvidia_set_debug_port;
1024 }
1025 }
1026
1027 /*
1028 * The code in ehci_dbgp_bios_handoff() is derived from the USB PCI
1029 * quirk initialization in Linux.
1030 */
1031 #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
1032 #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
ehci_dbgp_bios_handoff(struct ehci_dbgp * dbgp,u32 hcc_params)1033 static void ehci_dbgp_bios_handoff(struct ehci_dbgp *dbgp, u32 hcc_params)
1034 {
1035 u32 cap;
1036 unsigned int offset = HCC_EXT_CAPS(hcc_params);
1037 int msec;
1038
1039 if ( !offset )
1040 return;
1041
1042 cap = pci_conf_read32(0, dbgp->bus, dbgp->slot, dbgp->func, offset);
1043 dbgp_printk("dbgp: EHCI BIOS state %08x\n", cap);
1044
1045 if ( (cap & 0xff) == 1 && (cap & EHCI_USBLEGSUP_BIOS) )
1046 {
1047 dbgp_printk("dbgp: BIOS handoff\n");
1048 pci_conf_write8(0, dbgp->bus, dbgp->slot, dbgp->func, offset + 3, 1);
1049 }
1050
1051 /* if boot firmware now owns EHCI, spin till it hands it over. */
1052 msec = 1000;
1053 while ( (cap & EHCI_USBLEGSUP_BIOS) && (msec > 0) )
1054 {
1055 mdelay(10);
1056 msec -= 10;
1057 cap = pci_conf_read32(0, dbgp->bus, dbgp->slot, dbgp->func, offset);
1058 }
1059
1060 if ( cap & EHCI_USBLEGSUP_BIOS )
1061 {
1062 /* well, possibly buggy BIOS... try to shut it down,
1063 * and hope nothing goes too wrong */
1064 dbgp_printk("dbgp: BIOS handoff failed: %08x\n", cap);
1065 pci_conf_write8(0, dbgp->bus, dbgp->slot, dbgp->func, offset + 2, 0);
1066 }
1067
1068 /* just in case, always disable EHCI SMIs */
1069 pci_conf_write8(0, dbgp->bus, dbgp->slot, dbgp->func,
1070 offset + EHCI_USBLEGCTLSTS, 0);
1071 }
1072
ehci_dbgp_setup(struct ehci_dbgp * dbgp)1073 static int ehci_dbgp_setup(struct ehci_dbgp *dbgp)
1074 {
1075 u32 ctrl, portsc, hcs_params;
1076 unsigned int i, debug_port, new_debug_port = 0, n_ports;
1077 unsigned int port_map_tried, playtimes = 3;
1078 int ret;
1079
1080 ehci_dbgp_bios_handoff(dbgp, readl(&dbgp->ehci_caps->hcc_params));
1081
1082 try_next_time:
1083 port_map_tried = 0;
1084
1085 try_next_port:
1086
1087 hcs_params = readl(&dbgp->ehci_caps->hcs_params);
1088 debug_port = HCS_DEBUG_PORT(hcs_params);
1089 dbgp->phys_port = debug_port;
1090 n_ports = HCS_N_PORTS(hcs_params);
1091
1092 dbgp_printk("debug_port: %u\n", debug_port);
1093 dbgp_printk("n_ports: %u\n", n_ports);
1094 ehci_dbgp_status(dbgp, "");
1095
1096 if ( n_ports == 0 )
1097 return -1;
1098
1099 for ( i = 1; i <= n_ports; i++ )
1100 {
1101 portsc = readl(&dbgp->ehci_regs->port_status[i-1]);
1102 dbgp_printk("portstatus%d: %08x\n", i, portsc);
1103 }
1104
1105 if ( port_map_tried && (new_debug_port != debug_port) )
1106 {
1107 if ( --playtimes )
1108 {
1109 set_debug_port(dbgp, new_debug_port);
1110 goto try_next_time;
1111 }
1112 return -1;
1113 }
1114
1115 /* Only reset the controller if it is not already in the
1116 * configured state */
1117 if ( readl(&dbgp->ehci_regs->configured_flag) & FLAG_CF )
1118 ehci_dbgp_status(dbgp, "ehci skip - already configured");
1119 else if ( ehci_dbgp_controller_reset(dbgp) != 0 )
1120 return -1;
1121
1122 ret = ehci_dbgp_external_startup(dbgp);
1123 if (ret == -EIO)
1124 goto next_debug_port;
1125
1126 if ( ret < 0 )
1127 {
1128 /* Things didn't work so remove my claim */
1129 ctrl = readl(&dbgp->ehci_debug->control);
1130 ctrl &= ~(DBGP_CLAIM | DBGP_OUT);
1131 writel(ctrl, &dbgp->ehci_debug->control);
1132 return -1;
1133 }
1134
1135 return 0;
1136
1137 next_debug_port:
1138 port_map_tried |= 1 << (debug_port - 1);
1139 new_debug_port = (debug_port % n_ports) + 1;
1140 if ( port_map_tried != ((1 << n_ports) - 1) )
1141 {
1142 set_debug_port(dbgp, new_debug_port);
1143 goto try_next_port;
1144 }
1145 if ( --playtimes )
1146 {
1147 set_debug_port(dbgp, new_debug_port);
1148 goto try_next_time;
1149 }
1150
1151 return -1;
1152 }
1153
_ehci_dbgp_flush(struct ehci_dbgp * dbgp)1154 static inline void _ehci_dbgp_flush(struct ehci_dbgp *dbgp)
1155 {
1156 if ( dbgp_bulk_write(dbgp, USB_DEBUG_DEVNUM, dbgp->out.endpoint,
1157 dbgp->out.buf, dbgp->out.chunk, NULL) )
1158 BUG();
1159 dbgp->out.chunk = 0;
1160 }
1161
ehci_dbgp_flush(struct serial_port * port)1162 static void ehci_dbgp_flush(struct serial_port *port)
1163 {
1164 struct ehci_dbgp *dbgp = port->uart;
1165 s_time_t goal;
1166
1167 if ( !dbgp->out.chunk || !dbgp->ehci_debug || dbgp->state == dbgp_unsafe )
1168 return;
1169
1170 if ( dbgp->state == dbgp_idle || !port->sync )
1171 dbgp_check_for_completion(dbgp, 1, NULL);
1172 else
1173 dbgp_wait_until_complete(dbgp, NULL);
1174
1175 if ( dbgp->state == dbgp_idle )
1176 {
1177 _ehci_dbgp_flush(dbgp);
1178
1179 if ( port->sync )
1180 {
1181 dbgp_wait_until_complete(dbgp, NULL);
1182 return;
1183 }
1184 }
1185
1186 goal = NOW() + MICROSECS(DBGP_CHECK_INTERVAL);
1187 if ( dbgp->timer.expires > goal )
1188 set_timer(&dbgp->timer, goal);
1189 }
1190
ehci_dbgp_putc(struct serial_port * port,char c)1191 static void ehci_dbgp_putc(struct serial_port *port, char c)
1192 {
1193 struct ehci_dbgp *dbgp = port->uart;
1194
1195 if ( unlikely(dbgp->out.chunk >= DBGP_MAX_PACKET) )
1196 return;
1197
1198 dbgp->out.buf[dbgp->out.chunk++] = c;
1199
1200 if ( dbgp->out.chunk == DBGP_MAX_PACKET )
1201 ehci_dbgp_flush(port);
1202 }
1203
ehci_dbgp_tx_ready(struct serial_port * port)1204 static int ehci_dbgp_tx_ready(struct serial_port *port)
1205 {
1206 struct ehci_dbgp *dbgp = port->uart;
1207
1208 if ( unlikely(!dbgp->ehci_debug) || unlikely(dbgp->state == dbgp_unsafe) )
1209 return port->sync || port->tx_log_everything || !port->txbuf;
1210
1211 if ( dbgp->out.chunk == DBGP_MAX_PACKET )
1212 ehci_dbgp_flush(port);
1213 else
1214 dbgp_check_for_completion(dbgp, 1, NULL);
1215
1216 if ( dbgp->state != dbgp_idle && dbgp->out.chunk >= DBGP_MAX_PACKET )
1217 return 0;
1218
1219 return DBGP_MAX_PACKET - dbgp->out.chunk +
1220 (dbgp->state == dbgp_idle) * DBGP_MAX_PACKET;
1221 }
1222
ehci_dbgp_getc(struct serial_port * port,char * pc)1223 static int ehci_dbgp_getc(struct serial_port *port, char *pc)
1224 {
1225 struct ehci_dbgp *dbgp = port->uart;
1226
1227 if ( !dbgp->in.chunk )
1228 return 0;
1229
1230 *pc = *dbgp->in.buf;
1231 if ( --dbgp->in.chunk )
1232 memmove(dbgp->in.buf, dbgp->in.buf + 1, dbgp->in.chunk);
1233
1234 return 1;
1235 }
1236
1237 /* Safe: ehci_dbgp_poll() runs as timer handler, so not reentrant. */
1238 static struct serial_port *poll_port;
1239
_ehci_dbgp_poll(struct cpu_user_regs * regs)1240 static void _ehci_dbgp_poll(struct cpu_user_regs *regs)
1241 {
1242 struct serial_port *port = poll_port;
1243 struct ehci_dbgp *dbgp = port->uart;
1244 unsigned long flags;
1245 unsigned int timeout = MICROSECS(DBGP_CHECK_INTERVAL);
1246 bool_t empty = 0;
1247
1248 if ( !dbgp->ehci_debug )
1249 return;
1250
1251 if ( spin_trylock_irqsave(&port->tx_lock, flags) )
1252 {
1253 if ( dbgp->state != dbgp_unsafe )
1254 dbgp_check_for_completion(dbgp, DBGP_CHECK_INTERVAL, NULL);
1255 if ( dbgp->state == dbgp_idle && dbgp->out.chunk )
1256 _ehci_dbgp_flush(dbgp);
1257 if ( dbgp->state == dbgp_idle || dbgp->out.chunk < DBGP_MAX_PACKET )
1258 empty = 1;
1259 spin_unlock_irqrestore(&port->tx_lock, flags);
1260 }
1261
1262 if ( dbgp->in.chunk )
1263 serial_rx_interrupt(port, regs);
1264
1265 if ( empty )
1266 serial_tx_interrupt(port, regs);
1267
1268 if ( spin_trylock_irqsave(&port->tx_lock, flags) )
1269 {
1270 if ( dbgp->state == dbgp_idle && !dbgp->in.chunk &&
1271 !dbgp->out.chunk && port->txbufp == port->txbufc )
1272 {
1273 if ( dbgp_bulk_read(dbgp, USB_DEBUG_DEVNUM, dbgp->in.endpoint,
1274 DBGP_MAX_PACKET, NULL) )
1275 BUG();
1276 timeout = MILLISECS(DBGP_IDLE_INTERVAL);
1277 }
1278 spin_unlock_irqrestore(&port->tx_lock, flags);
1279 }
1280
1281 set_timer(&dbgp->timer, NOW() + timeout);
1282 }
1283
ehci_dbgp_poll(void * data)1284 static void ehci_dbgp_poll(void *data)
1285 {
1286 poll_port = data;
1287 #ifdef run_in_exception_handler
1288 run_in_exception_handler(_ehci_dbgp_poll);
1289 #else
1290 _ehci_dbgp_poll(guest_cpu_user_regs());
1291 #endif
1292 }
1293
ehci_dbgp_setup_preirq(struct ehci_dbgp * dbgp)1294 static bool_t ehci_dbgp_setup_preirq(struct ehci_dbgp *dbgp)
1295 {
1296 if ( !ehci_dbgp_setup(dbgp) )
1297 return 1;
1298
1299 dbgp_printk("ehci_dbgp_setup failed\n");
1300 dbgp->ehci_debug = NULL;
1301 return 0;
1302 }
1303
ehci_dbgp_init_preirq(struct serial_port * port)1304 static void __init ehci_dbgp_init_preirq(struct serial_port *port)
1305 {
1306 struct ehci_dbgp *dbgp = port->uart;
1307 u32 debug_port, offset;
1308 void __iomem *ehci_bar;
1309
1310 debug_port = pci_conf_read32(0, dbgp->bus, dbgp->slot, dbgp->func,
1311 dbgp->cap);
1312 offset = (debug_port >> 16) & 0xfff;
1313
1314 /* double check if the mem space is enabled */
1315 dbgp->pci_cr = pci_conf_read8(0, dbgp->bus, dbgp->slot, dbgp->func,
1316 PCI_COMMAND);
1317 if ( !(dbgp->pci_cr & PCI_COMMAND_MEMORY) )
1318 {
1319 dbgp->pci_cr |= PCI_COMMAND_MEMORY;
1320 pci_conf_write16(0, dbgp->bus, dbgp->slot, dbgp->func, PCI_COMMAND,
1321 dbgp->pci_cr);
1322 dbgp_printk("MMIO for EHCI enabled\n");
1323 }
1324
1325 /*
1326 * FIXME I don't have the bar size so just guess PAGE_SIZE is more
1327 * than enough. 1k is the biggest that was seen.
1328 */
1329 set_fixmap_nocache(FIX_EHCI_DBGP, dbgp->bar_val);
1330 ehci_bar = fix_to_virt(FIX_EHCI_DBGP);
1331 ehci_bar += dbgp->bar_val & ~PAGE_MASK;
1332 dbgp_printk("ehci_bar: %p\n", ehci_bar);
1333
1334 dbgp->ehci_caps = ehci_bar;
1335 dbgp->ehci_regs = ehci_bar +
1336 HC_LENGTH(readl(&dbgp->ehci_caps->hc_capbase));
1337 dbgp->ehci_debug = ehci_bar + offset;
1338
1339 detect_set_debug_port(dbgp);
1340
1341 if ( ehci_dbgp_setup_preirq(dbgp) )
1342 ehci_dbgp_status(dbgp, "ehci_dbgp_init_preirq complete");
1343
1344 dbgp->lock = &port->tx_lock;
1345 }
1346
ehci_dbgp_setup_postirq(struct ehci_dbgp * dbgp)1347 static void ehci_dbgp_setup_postirq(struct ehci_dbgp *dbgp)
1348 {
1349 set_timer(&dbgp->timer, NOW() + MILLISECS(1));
1350 }
1351
ehci_dbgp_init_postirq(struct serial_port * port)1352 static void __init ehci_dbgp_init_postirq(struct serial_port *port)
1353 {
1354 struct ehci_dbgp *dbgp = port->uart;
1355
1356 if ( !dbgp->ehci_debug )
1357 return;
1358
1359 serial_async_transmit(port);
1360
1361 init_timer(&dbgp->timer, ehci_dbgp_poll, port, 0);
1362
1363 ehci_dbgp_setup_postirq(dbgp);
1364
1365 pci_hide_device(dbgp->bus, PCI_DEVFN(dbgp->slot, dbgp->func));
1366 }
1367
ehci_dbgp_check_release(struct ehci_dbgp * dbgp)1368 static int ehci_dbgp_check_release(struct ehci_dbgp *dbgp)
1369 {
1370 struct ehci_dbg_port __iomem *ehci_debug = dbgp->ehci_debug;
1371 u32 ctrl;
1372 unsigned int i;
1373
1374 if ( !ehci_debug )
1375 return 0;
1376
1377 for ( i = 0; i < DBGP_MAX_PACKET; ++i )
1378 if ( dbgp->out.buf[i] )
1379 return 1;
1380
1381 /*
1382 * This means the console is not initialized, or should get shutdown
1383 * so as to allow for reuse of the USB device, which means it is time
1384 * to shutdown the USB debug port.
1385 */
1386 printk(XENLOG_INFO "Releasing EHCI debug port at %02x:%02x.%u\n",
1387 dbgp->bus, dbgp->slot, dbgp->func);
1388
1389 if ( dbgp->timer.function )
1390 kill_timer(&dbgp->timer);
1391 dbgp->ehci_debug = NULL;
1392
1393 ctrl = readl(&ehci_debug->control);
1394 if ( ctrl & DBGP_ENABLED )
1395 {
1396 ctrl &= ~DBGP_CLAIM;
1397 writel(ctrl, &ehci_debug->control);
1398 }
1399
1400 return 0;
1401 }
1402
ehci_dbgp_endboot(struct serial_port * port)1403 static void __init ehci_dbgp_endboot(struct serial_port *port)
1404 {
1405 ehci_dbgp_check_release(port->uart);
1406 }
1407
ehci_dbgp_suspend(struct serial_port * port)1408 static void ehci_dbgp_suspend(struct serial_port *port)
1409 {
1410 struct ehci_dbgp *dbgp = port->uart;
1411
1412 if ( !dbgp->ehci_debug )
1413 return;
1414
1415 stop_timer(&dbgp->timer);
1416 dbgp->timer.expires = 0;
1417
1418 dbgp->pci_cr = pci_conf_read16(0, dbgp->bus, dbgp->slot, dbgp->func,
1419 PCI_COMMAND);
1420
1421 dbgp->state = dbgp_unsafe;
1422 }
1423
ehci_dbgp_resume(struct serial_port * port)1424 static void ehci_dbgp_resume(struct serial_port *port)
1425 {
1426 struct ehci_dbgp *dbgp = port->uart;
1427
1428 if ( !dbgp->ehci_debug )
1429 return;
1430
1431 pci_conf_write32(0, dbgp->bus, dbgp->slot, dbgp->func, dbgp->bar,
1432 dbgp->bar_val);
1433 pci_conf_write16(0, dbgp->bus, dbgp->slot, dbgp->func,
1434 PCI_COMMAND, dbgp->pci_cr);
1435
1436 ehci_dbgp_setup_preirq(dbgp);
1437 ehci_dbgp_setup_postirq(dbgp);
1438 }
1439
1440 static struct uart_driver __read_mostly ehci_dbgp_driver = {
1441 .init_preirq = ehci_dbgp_init_preirq,
1442 .init_postirq = ehci_dbgp_init_postirq,
1443 .endboot = ehci_dbgp_endboot,
1444 .suspend = ehci_dbgp_suspend,
1445 .resume = ehci_dbgp_resume,
1446 .tx_ready = ehci_dbgp_tx_ready,
1447 .putc = ehci_dbgp_putc,
1448 .flush = ehci_dbgp_flush,
1449 .getc = ehci_dbgp_getc
1450 };
1451
1452 static struct ehci_dbgp ehci_dbgp = { .state = dbgp_unsafe, .phys_port = 1 };
1453
1454 static char __initdata opt_dbgp[30];
1455 string_param("dbgp", opt_dbgp);
1456
ehci_dbgp_init(void)1457 void __init ehci_dbgp_init(void)
1458 {
1459 struct ehci_dbgp *dbgp = &ehci_dbgp;
1460 u32 debug_port, offset, bar_val;
1461 const char *e;
1462
1463 if ( strncmp(opt_dbgp, "ehci", 4) )
1464 return;
1465
1466 if ( isdigit(opt_dbgp[4]) || !opt_dbgp[4] )
1467 {
1468 unsigned int num = 0;
1469
1470 if ( opt_dbgp[4] )
1471 simple_strtoul(opt_dbgp + 4, &e, 10);
1472
1473 dbgp->cap = find_dbgp(dbgp, num);
1474 if ( !dbgp->cap )
1475 return;
1476
1477 dbgp_printk("Found EHCI debug port on %02x:%02x.%u\n",
1478 dbgp->bus, dbgp->slot, dbgp->func);
1479 }
1480 else if ( strncmp(opt_dbgp + 4, "@pci", 4) == 0 )
1481 {
1482 unsigned int bus, slot, func;
1483
1484 e = parse_pci(opt_dbgp + 8, NULL, &bus, &slot, &func);
1485 if ( !e || *e )
1486 return;
1487
1488 dbgp->bus = bus;
1489 dbgp->slot = slot;
1490 dbgp->func = func;
1491
1492 if ( !pci_device_detect(0, bus, slot, func) )
1493 return;
1494
1495 dbgp->cap = __find_dbgp(bus, slot, func);
1496 if ( !dbgp->cap )
1497 return;
1498
1499 dbgp_printk("Using EHCI debug port on %02x:%02x.%u\n",
1500 bus, slot, func);
1501 }
1502 else
1503 return;
1504
1505 debug_port = pci_conf_read32(0, dbgp->bus, dbgp->slot, dbgp->func,
1506 dbgp->cap);
1507 dbgp->bar = (debug_port >> 29) & 0x7;
1508 dbgp->bar = ((dbgp->bar - 1) * 4) + PCI_BASE_ADDRESS_0;
1509 offset = (debug_port >> 16) & 0xfff;
1510 dbgp_printk("bar: %02x offset: %03x\n", dbgp->bar, offset);
1511 if ( dbgp->bar < PCI_BASE_ADDRESS_0 || dbgp->bar > PCI_BASE_ADDRESS_5 )
1512 {
1513 dbgp_printk("unsupported/invalid bar\n");
1514 return;
1515 }
1516
1517 dbgp->bar_val = bar_val = pci_conf_read32(0, dbgp->bus, dbgp->slot,
1518 dbgp->func, dbgp->bar);
1519 dbgp_printk("bar_val: %08x\n", bar_val);
1520 if ( bar_val & ~PCI_BASE_ADDRESS_MEM_MASK )
1521 {
1522 dbgp_printk("only simple 32-bit MMIO BARs supported\n");
1523 return;
1524 }
1525 bar_val &= PCI_BASE_ADDRESS_MEM_MASK;
1526 if ( !bar_val || !(bar_val + (bar_val & -bar_val)) )
1527 {
1528 dbgp_printk("firmware initialization of MMIO BAR required\n");
1529 return;
1530 }
1531
1532 serial_register_uart(SERHND_DBGP, &ehci_dbgp_driver, dbgp);
1533 }
1534
dbgp_op(const struct physdev_dbgp_op * op)1535 int dbgp_op(const struct physdev_dbgp_op *op)
1536 {
1537 if ( !ehci_dbgp.ehci_debug )
1538 return 0;
1539
1540 switch ( op->bus )
1541 {
1542 case PHYSDEVOP_DBGP_BUS_UNKNOWN:
1543 break;
1544 case PHYSDEVOP_DBGP_BUS_PCI:
1545 if ( op->u.pci.seg || ehci_dbgp.bus != op->u.pci.bus ||
1546 PCI_DEVFN(ehci_dbgp.slot, ehci_dbgp.func) != op->u.pci.devfn )
1547 default:
1548 return 0;
1549 break;
1550 }
1551
1552 switch ( op->op )
1553 {
1554 case PHYSDEVOP_DBGP_RESET_PREPARE:
1555 spin_lock_irq(ehci_dbgp.lock);
1556 ehci_dbgp.state = dbgp_unsafe;
1557 dbgp_wait_until_complete(&ehci_dbgp, NULL);
1558 spin_unlock_irq(ehci_dbgp.lock);
1559
1560 return ehci_dbgp_check_release(&ehci_dbgp);
1561
1562 case PHYSDEVOP_DBGP_RESET_DONE:
1563 return ehci_dbgp_external_startup(&ehci_dbgp) ?: 1;
1564 }
1565
1566 return -ENOSYS;
1567 }
1568