1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 /* FILE POLICY AND INTENDED USAGE:
27 * This file implements retrieval and configuration of eDP panel features such
28 * as PSR and ABM and it also manages specs defined eDP panel power sequences.
29 */
30
31 #include "link_edp_panel_control.h"
32 #include "link_dpcd.h"
33 #include "link_dp_capability.h"
34 #include "dm_helpers.h"
35 #include "dal_asic_id.h"
36 #include "dce/dmub_psr.h"
37 #include "abm.h"
38 #define DC_LOGGER_INIT(logger)
39
dp_set_panel_mode(struct dc_link * link,enum dp_panel_mode panel_mode)40 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode)
41 {
42 union dpcd_edp_config edp_config_set;
43 bool panel_mode_edp = false;
44
45 memset(&edp_config_set, '\0', sizeof(union dpcd_edp_config));
46
47 if (panel_mode != DP_PANEL_MODE_DEFAULT) {
48
49 switch (panel_mode) {
50 case DP_PANEL_MODE_EDP:
51 case DP_PANEL_MODE_SPECIAL:
52 panel_mode_edp = true;
53 break;
54
55 default:
56 break;
57 }
58
59 /*set edp panel mode in receiver*/
60 core_link_read_dpcd(
61 link,
62 DP_EDP_CONFIGURATION_SET,
63 &edp_config_set.raw,
64 sizeof(edp_config_set.raw));
65
66 if (edp_config_set.bits.PANEL_MODE_EDP
67 != panel_mode_edp) {
68 enum dc_status result;
69
70 edp_config_set.bits.PANEL_MODE_EDP =
71 panel_mode_edp;
72 result = core_link_write_dpcd(
73 link,
74 DP_EDP_CONFIGURATION_SET,
75 &edp_config_set.raw,
76 sizeof(edp_config_set.raw));
77
78 ASSERT(result == DC_OK);
79 }
80 }
81 DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d "
82 "eDP panel mode enabled: %d \n",
83 link->link_index,
84 link->dpcd_caps.panel_mode_edp,
85 panel_mode_edp);
86 }
87
dp_get_panel_mode(struct dc_link * link)88 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link)
89 {
90 /* We need to explicitly check that connector
91 * is not DP. Some Travis_VGA get reported
92 * by video bios as DP.
93 */
94 if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) {
95
96 switch (link->dpcd_caps.branch_dev_id) {
97 case DP_BRANCH_DEVICE_ID_0022B9:
98 /* alternate scrambler reset is required for Travis
99 * for the case when external chip does not
100 * provide sink device id, alternate scrambler
101 * scheme will be overriden later by querying
102 * Encoder features
103 */
104 if (strncmp(
105 link->dpcd_caps.branch_dev_name,
106 DP_VGA_LVDS_CONVERTER_ID_2,
107 sizeof(
108 link->dpcd_caps.
109 branch_dev_name)) == 0) {
110 return DP_PANEL_MODE_SPECIAL;
111 }
112 break;
113 case DP_BRANCH_DEVICE_ID_00001A:
114 /* alternate scrambler reset is required for Travis
115 * for the case when external chip does not provide
116 * sink device id, alternate scrambler scheme will
117 * be overriden later by querying Encoder feature
118 */
119 if (strncmp(link->dpcd_caps.branch_dev_name,
120 DP_VGA_LVDS_CONVERTER_ID_3,
121 sizeof(
122 link->dpcd_caps.
123 branch_dev_name)) == 0) {
124 return DP_PANEL_MODE_SPECIAL;
125 }
126 break;
127 default:
128 break;
129 }
130 }
131
132 if (link->dpcd_caps.panel_mode_edp &&
133 (link->connector_signal == SIGNAL_TYPE_EDP ||
134 (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
135 link->is_internal_display))) {
136 return DP_PANEL_MODE_EDP;
137 }
138
139 return DP_PANEL_MODE_DEFAULT;
140 }
141
dc_link_set_backlight_level_nits(struct dc_link * link,bool isHDR,uint32_t backlight_millinits,uint32_t transition_time_in_ms)142 bool dc_link_set_backlight_level_nits(struct dc_link *link,
143 bool isHDR,
144 uint32_t backlight_millinits,
145 uint32_t transition_time_in_ms)
146 {
147 struct dpcd_source_backlight_set dpcd_backlight_set;
148 uint8_t backlight_control = isHDR ? 1 : 0;
149
150 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
151 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
152 return false;
153
154 // OLEDs have no PWM, they can only use AUX
155 if (link->dpcd_sink_ext_caps.bits.oled == 1)
156 backlight_control = 1;
157
158 *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits;
159 *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms;
160
161
162 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
163 (uint8_t *)(&dpcd_backlight_set),
164 sizeof(dpcd_backlight_set)) != DC_OK)
165 return false;
166
167 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL,
168 &backlight_control, 1) != DC_OK)
169 return false;
170
171 return true;
172 }
173
dc_link_get_backlight_level_nits(struct dc_link * link,uint32_t * backlight_millinits_avg,uint32_t * backlight_millinits_peak)174 bool dc_link_get_backlight_level_nits(struct dc_link *link,
175 uint32_t *backlight_millinits_avg,
176 uint32_t *backlight_millinits_peak)
177 {
178 union dpcd_source_backlight_get dpcd_backlight_get;
179
180 memset(&dpcd_backlight_get, 0, sizeof(union dpcd_source_backlight_get));
181
182 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
183 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
184 return false;
185
186 if (!core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_CURRENT_PEAK,
187 dpcd_backlight_get.raw,
188 sizeof(union dpcd_source_backlight_get)))
189 return false;
190
191 *backlight_millinits_avg =
192 dpcd_backlight_get.bytes.backlight_millinits_avg;
193 *backlight_millinits_peak =
194 dpcd_backlight_get.bytes.backlight_millinits_peak;
195
196 /* On non-supported panels dpcd_read usually succeeds with 0 returned */
197 if (*backlight_millinits_avg == 0 ||
198 *backlight_millinits_avg > *backlight_millinits_peak)
199 return false;
200
201 return true;
202 }
203
link_backlight_enable_aux(struct dc_link * link,bool enable)204 bool link_backlight_enable_aux(struct dc_link *link, bool enable)
205 {
206 uint8_t backlight_enable = enable ? 1 : 0;
207
208 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
209 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
210 return false;
211
212 if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_ENABLE,
213 &backlight_enable, 1) != DC_OK)
214 return false;
215
216 return true;
217 }
218
219 // we read default from 0x320 because we expect BIOS wrote it there
220 // regular get_backlight_nit reads from panel set at 0x326
read_default_bl_aux(struct dc_link * link,uint32_t * backlight_millinits)221 static bool read_default_bl_aux(struct dc_link *link, uint32_t *backlight_millinits)
222 {
223 if (!link || (link->connector_signal != SIGNAL_TYPE_EDP &&
224 link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT))
225 return false;
226
227 if (!core_link_read_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL,
228 (uint8_t *) backlight_millinits,
229 sizeof(uint32_t)))
230 return false;
231
232 return true;
233 }
234
set_default_brightness_aux(struct dc_link * link)235 bool set_default_brightness_aux(struct dc_link *link)
236 {
237 uint32_t default_backlight;
238
239 if (link && link->dpcd_sink_ext_caps.bits.oled == 1) {
240 if (!read_default_bl_aux(link, &default_backlight))
241 default_backlight = 150000;
242 // if < 5 nits or > 5000, it might be wrong readback
243 if (default_backlight < 5000 || default_backlight > 5000000)
244 default_backlight = 150000; //
245
246 return dc_link_set_backlight_level_nits(link, true,
247 default_backlight, 0);
248 }
249 return false;
250 }
251
link_is_edp_ilr_optimization_required(struct dc_link * link,struct dc_crtc_timing * crtc_timing)252 bool link_is_edp_ilr_optimization_required(struct dc_link *link,
253 struct dc_crtc_timing *crtc_timing)
254 {
255 struct dc_link_settings link_setting;
256 uint8_t link_bw_set;
257 uint8_t link_rate_set;
258 uint32_t req_bw;
259 union lane_count_set lane_count_set = {0};
260
261 ASSERT(link || crtc_timing); // invalid input
262
263 if (link->dpcd_caps.edp_supported_link_rates_count == 0 ||
264 !link->panel_config.ilr.optimize_edp_link_rate)
265 return false;
266
267
268 // Read DPCD 00100h to find if standard link rates are set
269 core_link_read_dpcd(link, DP_LINK_BW_SET,
270 &link_bw_set, sizeof(link_bw_set));
271
272 if (link_bw_set) {
273 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS used link_bw_set\n");
274 return true;
275 }
276
277 // Read DPCD 00115h to find the edp link rate set used
278 core_link_read_dpcd(link, DP_LINK_RATE_SET,
279 &link_rate_set, sizeof(link_rate_set));
280
281 // Read DPCD 00101h to find out the number of lanes currently set
282 core_link_read_dpcd(link, DP_LANE_COUNT_SET,
283 &lane_count_set.raw, sizeof(lane_count_set));
284
285 req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing);
286
287 if (!crtc_timing->flags.DSC)
288 dc_link_decide_edp_link_settings(link, &link_setting, req_bw);
289 else
290 decide_edp_link_settings_with_dsc(link, &link_setting, req_bw, LINK_RATE_UNKNOWN);
291
292 if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate ||
293 lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) {
294 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: Optimization required, VBIOS link_rate_set not optimal\n");
295 return true;
296 }
297
298 DC_LOG_EVENT_LINK_TRAINING("eDP ILR: No optimization required, VBIOS set optimal link_rate_set\n");
299 return false;
300 }
301
dc_link_edp_panel_backlight_power_on(struct dc_link * link,bool wait_for_hpd)302 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, bool wait_for_hpd)
303 {
304 if (link->connector_signal != SIGNAL_TYPE_EDP)
305 return;
306
307 link->dc->hwss.edp_power_control(link, true);
308 if (wait_for_hpd)
309 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
310 if (link->dc->hwss.edp_backlight_control)
311 link->dc->hwss.edp_backlight_control(link, true);
312 }
313
dc_link_wait_for_t12(struct dc_link * link)314 bool dc_link_wait_for_t12(struct dc_link *link)
315 {
316 if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {
317 link->dc->hwss.edp_wait_for_T12(link);
318
319 return true;
320 }
321
322 return false;
323 }
324
link_edp_add_delay_for_T9(struct dc_link * link)325 void link_edp_add_delay_for_T9(struct dc_link *link)
326 {
327 if (link && link->panel_config.pps.extra_delay_backlight_off > 0)
328 udelay(link->panel_config.pps.extra_delay_backlight_off * 1000);
329 }
330
link_edp_receiver_ready_T9(struct dc_link * link)331 bool link_edp_receiver_ready_T9(struct dc_link *link)
332 {
333 unsigned int tries = 0;
334 unsigned char sinkstatus = 0;
335 unsigned char edpRev = 0;
336 enum dc_status result = DC_OK;
337
338 result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));
339
340 /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
341 if (result == DC_OK && edpRev >= DP_EDP_12) {
342 do {
343 sinkstatus = 1;
344 result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus));
345 if (sinkstatus == 0)
346 break;
347 if (result != DC_OK)
348 break;
349 udelay(100); //MAx T9
350 } while (++tries < 50);
351 }
352
353 return result;
354 }
355
link_edp_receiver_ready_T7(struct dc_link * link)356 bool link_edp_receiver_ready_T7(struct dc_link *link)
357 {
358 unsigned char sinkstatus = 0;
359 unsigned char edpRev = 0;
360 enum dc_status result = DC_OK;
361
362 /* use absolute time stamp to constrain max T7*/
363 unsigned long long enter_timestamp = 0;
364 unsigned long long finish_timestamp = 0;
365 unsigned long long time_taken_in_ns = 0;
366
367 result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev));
368
369 if (result == DC_OK && edpRev >= DP_EDP_12) {
370 /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/
371 enter_timestamp = dm_get_timestamp(link->ctx);
372 do {
373 sinkstatus = 0;
374 result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus));
375 if (sinkstatus == 1)
376 break;
377 if (result != DC_OK)
378 break;
379 udelay(25);
380 finish_timestamp = dm_get_timestamp(link->ctx);
381 time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp, enter_timestamp);
382 } while (time_taken_in_ns < 50 * 1000000); //MAx T7 is 50ms
383 }
384
385 if (link && link->panel_config.pps.extra_t7_ms > 0)
386 udelay(link->panel_config.pps.extra_t7_ms * 1000);
387
388 return result;
389 }
390
link_power_alpm_dpcd_enable(struct dc_link * link,bool enable)391 bool link_power_alpm_dpcd_enable(struct dc_link *link, bool enable)
392 {
393 bool ret = false;
394 union dpcd_alpm_configuration alpm_config;
395
396 if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
397 memset(&alpm_config, 0, sizeof(alpm_config));
398
399 alpm_config.bits.ENABLE = (enable ? true : false);
400 ret = dm_helpers_dp_write_dpcd(link->ctx, link,
401 DP_RECEIVER_ALPM_CONFIG, &alpm_config.raw,
402 sizeof(alpm_config.raw));
403 }
404 return ret;
405 }
406
get_pipe_from_link(const struct dc_link * link)407 static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)
408 {
409 int i;
410 struct dc *dc = link->ctx->dc;
411 struct pipe_ctx *pipe_ctx = NULL;
412
413 for (i = 0; i < MAX_PIPES; i++) {
414 if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
415 if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
416 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
417 break;
418 }
419 }
420 }
421
422 return pipe_ctx;
423 }
424
dc_link_set_backlight_level(const struct dc_link * link,uint32_t backlight_pwm_u16_16,uint32_t frame_ramp)425 bool dc_link_set_backlight_level(const struct dc_link *link,
426 uint32_t backlight_pwm_u16_16,
427 uint32_t frame_ramp)
428 {
429 struct dc *dc = link->ctx->dc;
430
431 DC_LOGGER_INIT(link->ctx->logger);
432 DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
433 backlight_pwm_u16_16, backlight_pwm_u16_16);
434
435 if (dc_is_embedded_signal(link->connector_signal)) {
436 struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);
437
438 if (pipe_ctx) {
439 /* Disable brightness ramping when the display is blanked
440 * as it can hang the DMCU
441 */
442 if (pipe_ctx->plane_state == NULL)
443 frame_ramp = 0;
444 } else {
445 return false;
446 }
447
448 dc->hwss.set_backlight_level(
449 pipe_ctx,
450 backlight_pwm_u16_16,
451 frame_ramp);
452 }
453 return true;
454 }
455
dc_link_set_psr_allow_active(struct dc_link * link,const bool * allow_active,bool wait,bool force_static,const unsigned int * power_opts)456 bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active,
457 bool wait, bool force_static, const unsigned int *power_opts)
458 {
459 struct dc *dc = link->ctx->dc;
460 struct dmcu *dmcu = dc->res_pool->dmcu;
461 struct dmub_psr *psr = dc->res_pool->psr;
462 unsigned int panel_inst;
463
464 if (psr == NULL && force_static)
465 return false;
466
467 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
468 return false;
469
470 if ((allow_active != NULL) && (*allow_active == true) && (link->type == dc_connection_none)) {
471 // Don't enter PSR if panel is not connected
472 return false;
473 }
474
475 /* Set power optimization flag */
476 if (power_opts && link->psr_settings.psr_power_opt != *power_opts) {
477 link->psr_settings.psr_power_opt = *power_opts;
478
479 if (psr != NULL && link->psr_settings.psr_feature_enabled && psr->funcs->psr_set_power_opt)
480 psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, panel_inst);
481 }
482
483 if (psr != NULL && link->psr_settings.psr_feature_enabled &&
484 force_static && psr->funcs->psr_force_static)
485 psr->funcs->psr_force_static(psr, panel_inst);
486
487 /* Enable or Disable PSR */
488 if (allow_active && link->psr_settings.psr_allow_active != *allow_active) {
489 link->psr_settings.psr_allow_active = *allow_active;
490
491 if (!link->psr_settings.psr_allow_active)
492 dc_z10_restore(dc);
493
494 if (psr != NULL && link->psr_settings.psr_feature_enabled) {
495 psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst);
496 } else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) &&
497 link->psr_settings.psr_feature_enabled)
498 dmcu->funcs->set_psr_enable(dmcu, link->psr_settings.psr_allow_active, wait);
499 else
500 return false;
501 }
502 return true;
503 }
504
dc_link_get_psr_state(const struct dc_link * link,enum dc_psr_state * state)505 bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
506 {
507 struct dc *dc = link->ctx->dc;
508 struct dmcu *dmcu = dc->res_pool->dmcu;
509 struct dmub_psr *psr = dc->res_pool->psr;
510 unsigned int panel_inst;
511
512 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
513 return false;
514
515 if (psr != NULL && link->psr_settings.psr_feature_enabled)
516 psr->funcs->psr_get_state(psr, state, panel_inst);
517 else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
518 dmcu->funcs->get_psr_state(dmcu, state);
519
520 return true;
521 }
522
523 static inline enum physical_phy_id
transmitter_to_phy_id(struct dc_link * link)524 transmitter_to_phy_id(struct dc_link *link)
525 {
526 struct dc_context *dc_ctx = link->ctx;
527 enum transmitter transmitter_value = link->link_enc->transmitter;
528
529 switch (transmitter_value) {
530 case TRANSMITTER_UNIPHY_A:
531 return PHYLD_0;
532 case TRANSMITTER_UNIPHY_B:
533 return PHYLD_1;
534 case TRANSMITTER_UNIPHY_C:
535 return PHYLD_2;
536 case TRANSMITTER_UNIPHY_D:
537 return PHYLD_3;
538 case TRANSMITTER_UNIPHY_E:
539 return PHYLD_4;
540 case TRANSMITTER_UNIPHY_F:
541 return PHYLD_5;
542 case TRANSMITTER_NUTMEG_CRT:
543 return PHYLD_6;
544 case TRANSMITTER_TRAVIS_CRT:
545 return PHYLD_7;
546 case TRANSMITTER_TRAVIS_LCD:
547 return PHYLD_8;
548 case TRANSMITTER_UNIPHY_G:
549 return PHYLD_9;
550 case TRANSMITTER_COUNT:
551 return PHYLD_COUNT;
552 case TRANSMITTER_UNKNOWN:
553 return PHYLD_UNKNOWN;
554 default:
555 DC_ERROR("Unknown transmitter value %d\n", transmitter_value);
556 return PHYLD_UNKNOWN;
557 }
558 }
559
dc_link_setup_psr(struct dc_link * link,const struct dc_stream_state * stream,struct psr_config * psr_config,struct psr_context * psr_context)560 bool dc_link_setup_psr(struct dc_link *link,
561 const struct dc_stream_state *stream, struct psr_config *psr_config,
562 struct psr_context *psr_context)
563 {
564 struct dc *dc;
565 struct dmcu *dmcu;
566 struct dmub_psr *psr;
567 int i;
568 unsigned int panel_inst;
569 /* updateSinkPsrDpcdConfig*/
570 union dpcd_psr_configuration psr_configuration;
571 union dpcd_sink_active_vtotal_control_mode vtotal_control = {0};
572
573 psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
574
575 if (!link)
576 return false;
577
578 dc = link->ctx->dc;
579 dmcu = dc->res_pool->dmcu;
580 psr = dc->res_pool->psr;
581
582 if (!dmcu && !psr)
583 return false;
584
585 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
586 return false;
587
588
589 memset(&psr_configuration, 0, sizeof(psr_configuration));
590
591 psr_configuration.bits.ENABLE = 1;
592 psr_configuration.bits.CRC_VERIFICATION = 1;
593 psr_configuration.bits.FRAME_CAPTURE_INDICATION =
594 psr_config->psr_frame_capture_indication_req;
595
596 /* Check for PSR v2*/
597 if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
598 /* For PSR v2 selective update.
599 * Indicates whether sink should start capturing
600 * immediately following active scan line,
601 * or starting with the 2nd active scan line.
602 */
603 psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
604 /*For PSR v2, determines whether Sink should generate
605 * IRQ_HPD when CRC mismatch is detected.
606 */
607 psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR = 1;
608 /* For PSR v2, set the bit when the Source device will
609 * be enabling PSR2 operation.
610 */
611 psr_configuration.bits.ENABLE_PSR2 = 1;
612 /* For PSR v2, the Sink device must be able to receive
613 * SU region updates early in the frame time.
614 */
615 psr_configuration.bits.EARLY_TRANSPORT_ENABLE = 1;
616 }
617
618 dm_helpers_dp_write_dpcd(
619 link->ctx,
620 link,
621 368,
622 &psr_configuration.raw,
623 sizeof(psr_configuration.raw));
624
625 if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
626 link_power_alpm_dpcd_enable(link, true);
627 psr_context->su_granularity_required =
628 psr_config->su_granularity_required;
629 psr_context->su_y_granularity =
630 psr_config->su_y_granularity;
631 psr_context->line_time_in_us = psr_config->line_time_in_us;
632
633 /* linux must be able to expose AMD Source DPCD definition
634 * in order to support FreeSync PSR
635 */
636 if (link->psr_settings.psr_vtotal_control_support) {
637 psr_context->rate_control_caps = psr_config->rate_control_caps;
638 vtotal_control.bits.ENABLE = true;
639 core_link_write_dpcd(link, DP_SINK_PSR_ACTIVE_VTOTAL_CONTROL_MODE,
640 &vtotal_control.raw, sizeof(vtotal_control.raw));
641 }
642 }
643
644 psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
645 psr_context->transmitterId = link->link_enc->transmitter;
646 psr_context->engineId = link->link_enc->preferred_engine;
647
648 for (i = 0; i < MAX_PIPES; i++) {
649 if (dc->current_state->res_ctx.pipe_ctx[i].stream
650 == stream) {
651 /* dmcu -1 for all controller id values,
652 * therefore +1 here
653 */
654 psr_context->controllerId =
655 dc->current_state->res_ctx.
656 pipe_ctx[i].stream_res.tg->inst + 1;
657 break;
658 }
659 }
660
661 /* Hardcoded for now. Can be Pcie or Uniphy (or Unknown)*/
662 psr_context->phyType = PHY_TYPE_UNIPHY;
663 /*PhyId is associated with the transmitter id*/
664 psr_context->smuPhyId = transmitter_to_phy_id(link);
665
666 psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
667 psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
668 timing.pix_clk_100hz * 100),
669 stream->timing.v_total),
670 stream->timing.h_total);
671
672 psr_context->psrSupportedDisplayConfig = true;
673 psr_context->psrExitLinkTrainingRequired =
674 psr_config->psr_exit_link_training_required;
675 psr_context->sdpTransmitLineNumDeadline =
676 psr_config->psr_sdp_transmit_line_num_deadline;
677 psr_context->psrFrameCaptureIndicationReq =
678 psr_config->psr_frame_capture_indication_req;
679
680 psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
681
682 psr_context->numberOfControllers =
683 link->dc->res_pool->timing_generator_count;
684
685 psr_context->rfb_update_auto_en = true;
686
687 /* 2 frames before enter PSR. */
688 psr_context->timehyst_frames = 2;
689 /* half a frame
690 * (units in 100 lines, i.e. a value of 1 represents 100 lines)
691 */
692 psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
693 psr_context->aux_repeats = 10;
694
695 psr_context->psr_level.u32all = 0;
696
697 /*skip power down the single pipe since it blocks the cstate*/
698 #if defined(CONFIG_DRM_AMD_DC_DCN)
699 if (link->ctx->asic_id.chip_family >= FAMILY_RV) {
700 switch (link->ctx->asic_id.chip_family) {
701 case FAMILY_YELLOW_CARP:
702 case AMDGPU_FAMILY_GC_10_3_6:
703 case AMDGPU_FAMILY_GC_11_0_1:
704 if (dc->debug.disable_z10 || dc->debug.psr_skip_crtc_disable)
705 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
706 break;
707 default:
708 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
709 break;
710 }
711 }
712 #else
713 if (link->ctx->asic_id.chip_family >= FAMILY_RV)
714 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
715 #endif
716
717 /* SMU will perform additional powerdown sequence.
718 * For unsupported ASICs, set psr_level flag to skip PSR
719 * static screen notification to SMU.
720 * (Always set for DAL2, did not check ASIC)
721 */
722 psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
723 psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;
724
725 /* Complete PSR entry before aborting to prevent intermittent
726 * freezes on certain eDPs
727 */
728 psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
729
730 /* Disable ALPM first for compatible non-ALPM panel now */
731 psr_context->psr_level.bits.DISABLE_ALPM = 0;
732 psr_context->psr_level.bits.ALPM_DEFAULT_PD_MODE = 1;
733
734 /* Controls additional delay after remote frame capture before
735 * continuing power down, default = 0
736 */
737 psr_context->frame_delay = 0;
738
739 psr_context->dsc_slice_height = psr_config->dsc_slice_height;
740
741 if (psr) {
742 link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
743 link, psr_context, panel_inst);
744 link->psr_settings.psr_power_opt = 0;
745 link->psr_settings.psr_allow_active = 0;
746 } else {
747 link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
748 }
749
750 /* psr_enabled == 0 indicates setup_psr did not succeed, but this
751 * should not happen since firmware should be running at this point
752 */
753 if (link->psr_settings.psr_feature_enabled == 0)
754 ASSERT(0);
755
756 return true;
757
758 }
759
link_get_psr_residency(const struct dc_link * link,uint32_t * residency)760 void link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
761 {
762 struct dc *dc = link->ctx->dc;
763 struct dmub_psr *psr = dc->res_pool->psr;
764 unsigned int panel_inst;
765
766 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
767 return;
768
769 // PSR residency measurements only supported on DMCUB
770 if (psr != NULL && link->psr_settings.psr_feature_enabled)
771 psr->funcs->psr_get_residency(psr, residency, panel_inst);
772 else
773 *residency = 0;
774 }
link_set_sink_vtotal_in_psr_active(const struct dc_link * link,uint16_t psr_vtotal_idle,uint16_t psr_vtotal_su)775 bool link_set_sink_vtotal_in_psr_active(const struct dc_link *link, uint16_t psr_vtotal_idle, uint16_t psr_vtotal_su)
776 {
777 struct dc *dc = link->ctx->dc;
778 struct dmub_psr *psr = dc->res_pool->psr;
779
780 if (psr == NULL || !link->psr_settings.psr_feature_enabled || !link->psr_settings.psr_vtotal_control_support)
781 return false;
782
783 psr->funcs->psr_set_sink_vtotal_in_psr_active(psr, psr_vtotal_idle, psr_vtotal_su);
784
785 return true;
786 }
787
get_abm_from_stream_res(const struct dc_link * link)788 static struct abm *get_abm_from_stream_res(const struct dc_link *link)
789 {
790 int i;
791 struct dc *dc = link->ctx->dc;
792 struct abm *abm = NULL;
793
794 for (i = 0; i < MAX_PIPES; i++) {
795 struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
796 struct dc_stream_state *stream = pipe_ctx.stream;
797
798 if (stream && stream->link == link) {
799 abm = pipe_ctx.stream_res.abm;
800 break;
801 }
802 }
803 return abm;
804 }
805
dc_link_get_backlight_level(const struct dc_link * link)806 int dc_link_get_backlight_level(const struct dc_link *link)
807 {
808 struct abm *abm = get_abm_from_stream_res(link);
809 struct panel_cntl *panel_cntl = link->panel_cntl;
810 struct dc *dc = link->ctx->dc;
811 struct dmcu *dmcu = dc->res_pool->dmcu;
812 bool fw_set_brightness = true;
813
814 if (dmcu)
815 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
816
817 if (!fw_set_brightness && panel_cntl->funcs->get_current_backlight)
818 return panel_cntl->funcs->get_current_backlight(panel_cntl);
819 else if (abm != NULL && abm->funcs->get_current_backlight != NULL)
820 return (int) abm->funcs->get_current_backlight(abm);
821 else
822 return DC_ERROR_UNEXPECTED;
823 }
824
dc_link_get_target_backlight_pwm(const struct dc_link * link)825 int dc_link_get_target_backlight_pwm(const struct dc_link *link)
826 {
827 struct abm *abm = get_abm_from_stream_res(link);
828
829 if (abm == NULL || abm->funcs->get_target_backlight == NULL)
830 return DC_ERROR_UNEXPECTED;
831
832 return (int) abm->funcs->get_target_backlight(abm);
833 }
834