1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27
28 #include "dccg.h"
29 #include "clk_mgr_internal.h"
30
31 // For dce12_get_dp_ref_freq_khz
32 #include "dce100/dce_clk_mgr.h"
33 // For dcn20_update_clocks_update_dpp_dto
34 #include "dcn20/dcn20_clk_mgr.h"
35 #include "dcn31/dcn31_clk_mgr.h"
36 #include "dcn315_clk_mgr.h"
37
38 #include "core_types.h"
39 #include "dcn315_smu.h"
40 #include "dm_helpers.h"
41
42 #include "dc_dmub_srv.h"
43
44 #include "logger_types.h"
45 #undef DC_LOGGER
46 #define DC_LOGGER \
47 clk_mgr->base.base.ctx->logger
48
49 #include "link.h"
50
51 #define TO_CLK_MGR_DCN315(clk_mgr)\
52 container_of(clk_mgr, struct clk_mgr_dcn315, base)
53
54 #define UNSUPPORTED_DCFCLK 10000000
55 #define MIN_DPP_DISP_CLK 100000
56
dcn315_get_active_display_cnt_wa(struct dc * dc,struct dc_state * context)57 static int dcn315_get_active_display_cnt_wa(
58 struct dc *dc,
59 struct dc_state *context)
60 {
61 int i, display_count;
62 bool tmds_present = false;
63
64 display_count = 0;
65 for (i = 0; i < context->stream_count; i++) {
66 const struct dc_stream_state *stream = context->streams[i];
67
68 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
69 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
70 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
71 tmds_present = true;
72 }
73
74 for (i = 0; i < dc->link_count; i++) {
75 const struct dc_link *link = dc->links[i];
76
77 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
78 if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
79 link->link_enc->funcs->is_dig_enabled(link->link_enc))
80 display_count++;
81 }
82
83 /* WA for hang on HDMI after display off back back on*/
84 if (display_count == 0 && tmds_present)
85 display_count = 1;
86
87 return display_count;
88 }
89
should_disable_otg(struct pipe_ctx * pipe)90 static bool should_disable_otg(struct pipe_ctx *pipe)
91 {
92 bool ret = true;
93
94 if (pipe->stream->link->link_enc && pipe->stream->link->link_enc->funcs->is_dig_enabled &&
95 pipe->stream->link->link_enc->funcs->is_dig_enabled(pipe->stream->link->link_enc))
96 ret = false;
97 return ret;
98 }
99
dcn315_disable_otg_wa(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool disable)100 static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
101 {
102 struct dc *dc = clk_mgr_base->ctx->dc;
103 int i;
104
105 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
106 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
107
108 if (pipe->top_pipe || pipe->prev_odm_pipe)
109 continue;
110 if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL ||
111 dc_is_virtual_signal(pipe->stream->signal))) {
112
113 /* This w/a should not trigger when we have a dig active */
114 if (should_disable_otg(pipe)) {
115 if (disable) {
116 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
117 reset_sync_context_for_pipe(dc, context, i);
118 } else
119 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
120 }
121 }
122 }
123 }
124
dcn315_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)125 static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,
126 struct dc_state *context,
127 bool safe_to_lower)
128 {
129 union dmub_rb_cmd cmd;
130 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
131 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
132 struct dc *dc = clk_mgr_base->ctx->dc;
133 int display_count;
134 bool update_dppclk = false;
135 bool update_dispclk = false;
136 bool dpp_clock_lowered = false;
137
138 if (dc->work_arounds.skip_clock_update)
139 return;
140
141 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
142 /*
143 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
144 * also if safe to lower is false, we just go in the higher state
145 */
146 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
147 if (safe_to_lower) {
148 /* check that we're not already in lower */
149 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
150 display_count = dcn315_get_active_display_cnt_wa(dc, context);
151 /* if we can go lower, go lower */
152 if (display_count == 0) {
153 union display_idle_optimization_u idle_info = { 0 };
154 idle_info.idle_info.df_request_disabled = 1;
155 idle_info.idle_info.phy_ref_clk_off = 1;
156 idle_info.idle_info.s0i2_rdy = 1;
157 dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
158 /* update power state */
159 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
160 }
161 }
162 } else {
163 /* check that we're not already in D0 */
164 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
165 union display_idle_optimization_u idle_info = { 0 };
166 dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
167 /* update power state */
168 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
169 }
170 }
171
172 /* Lock pstate by requesting unsupported dcfclk if change is unsupported */
173 if (!new_clocks->p_state_change_support)
174 new_clocks->dcfclk_khz = UNSUPPORTED_DCFCLK;
175 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
176 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
177 dcn315_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
178 }
179
180 if (should_set_clock(safe_to_lower,
181 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
182 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
183 dcn315_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
184 }
185
186 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
187 if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
188 if (new_clocks->dppclk_khz < MIN_DPP_DISP_CLK)
189 new_clocks->dppclk_khz = MIN_DPP_DISP_CLK;
190 if (new_clocks->dispclk_khz < MIN_DPP_DISP_CLK)
191 new_clocks->dispclk_khz = MIN_DPP_DISP_CLK;
192 }
193
194 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
195 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
196 dpp_clock_lowered = true;
197 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
198 update_dppclk = true;
199 }
200
201 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
202 /* No need to apply the w/a if we haven't taken over from bios yet */
203 if (clk_mgr_base->clks.dispclk_khz)
204 dcn315_disable_otg_wa(clk_mgr_base, context, true);
205
206 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
207 dcn315_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
208 if (clk_mgr_base->clks.dispclk_khz)
209 dcn315_disable_otg_wa(clk_mgr_base, context, false);
210
211 update_dispclk = true;
212 }
213
214 if (dpp_clock_lowered) {
215 // increase per DPP DTO before lowering global dppclk
216 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
217 dcn315_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
218 } else {
219 // increase global DPPCLK before lowering per DPP DTO
220 if (update_dppclk || update_dispclk)
221 dcn315_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
222 // always update dtos unless clock is lowered and not safe to lower
223 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
224 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
225 }
226
227 // notify DMCUB of latest clocks
228 memset(&cmd, 0, sizeof(cmd));
229 cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
230 cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
231 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
232 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
233 clk_mgr_base->clks.dcfclk_deep_sleep_khz;
234 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
235 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
236
237 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
238 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
239 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
240 }
241
dcn315_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info)242 static void dcn315_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
243 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
244 {
245 return;
246 }
247
248 static struct clk_bw_params dcn315_bw_params = {
249 .vram_type = Ddr4MemType,
250 .num_channels = 2,
251 .clk_table = {
252 .entries = {
253 {
254 .voltage = 0,
255 .dispclk_mhz = 640,
256 .dppclk_mhz = 640,
257 .phyclk_mhz = 810,
258 .phyclk_d18_mhz = 667,
259 .dtbclk_mhz = 600,
260 },
261 {
262 .voltage = 1,
263 .dispclk_mhz = 739,
264 .dppclk_mhz = 739,
265 .phyclk_mhz = 810,
266 .phyclk_d18_mhz = 667,
267 .dtbclk_mhz = 600,
268 },
269 {
270 .voltage = 2,
271 .dispclk_mhz = 960,
272 .dppclk_mhz = 960,
273 .phyclk_mhz = 810,
274 .phyclk_d18_mhz = 667,
275 .dtbclk_mhz = 600,
276 },
277 {
278 .voltage = 3,
279 .dispclk_mhz = 1200,
280 .dppclk_mhz = 1200,
281 .phyclk_mhz = 810,
282 .phyclk_d18_mhz = 667,
283 .dtbclk_mhz = 600,
284 },
285 {
286 .voltage = 4,
287 .dispclk_mhz = 1372,
288 .dppclk_mhz = 1372,
289 .phyclk_mhz = 810,
290 .phyclk_d18_mhz = 667,
291 .dtbclk_mhz = 600,
292 },
293 },
294 .num_entries = 5,
295 },
296
297 };
298
299 static struct wm_table ddr5_wm_table = {
300 .entries = {
301 {
302 .wm_inst = WM_A,
303 .wm_type = WM_TYPE_PSTATE_CHG,
304 .pstate_latency_us = 129.0,
305 .sr_exit_time_us = 11.5,
306 .sr_enter_plus_exit_time_us = 14.5,
307 .valid = true,
308 },
309 {
310 .wm_inst = WM_B,
311 .wm_type = WM_TYPE_PSTATE_CHG,
312 .pstate_latency_us = 129.0,
313 .sr_exit_time_us = 11.5,
314 .sr_enter_plus_exit_time_us = 14.5,
315 .valid = true,
316 },
317 {
318 .wm_inst = WM_C,
319 .wm_type = WM_TYPE_PSTATE_CHG,
320 .pstate_latency_us = 129.0,
321 .sr_exit_time_us = 11.5,
322 .sr_enter_plus_exit_time_us = 14.5,
323 .valid = true,
324 },
325 {
326 .wm_inst = WM_D,
327 .wm_type = WM_TYPE_PSTATE_CHG,
328 .pstate_latency_us = 129.0,
329 .sr_exit_time_us = 11.5,
330 .sr_enter_plus_exit_time_us = 14.5,
331 .valid = true,
332 },
333 }
334 };
335
336 static struct wm_table lpddr5_wm_table = {
337 .entries = {
338 {
339 .wm_inst = WM_A,
340 .wm_type = WM_TYPE_PSTATE_CHG,
341 .pstate_latency_us = 11.65333,
342 .sr_exit_time_us = 11.5,
343 .sr_enter_plus_exit_time_us = 14.5,
344 .valid = true,
345 },
346 {
347 .wm_inst = WM_B,
348 .wm_type = WM_TYPE_PSTATE_CHG,
349 .pstate_latency_us = 11.65333,
350 .sr_exit_time_us = 11.5,
351 .sr_enter_plus_exit_time_us = 14.5,
352 .valid = true,
353 },
354 {
355 .wm_inst = WM_C,
356 .wm_type = WM_TYPE_PSTATE_CHG,
357 .pstate_latency_us = 11.65333,
358 .sr_exit_time_us = 11.5,
359 .sr_enter_plus_exit_time_us = 14.5,
360 .valid = true,
361 },
362 {
363 .wm_inst = WM_D,
364 .wm_type = WM_TYPE_PSTATE_CHG,
365 .pstate_latency_us = 11.65333,
366 .sr_exit_time_us = 11.5,
367 .sr_enter_plus_exit_time_us = 14.5,
368 .valid = true,
369 },
370 }
371 };
372
373 /* Temporary Place holder until we can get them from fuse */
374 static DpmClocks_315_t dummy_clocks = { 0 };
375 static struct dcn315_watermarks dummy_wms = { 0 };
376
dcn315_build_watermark_ranges(struct clk_bw_params * bw_params,struct dcn315_watermarks * table)377 static void dcn315_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn315_watermarks *table)
378 {
379 int i, num_valid_sets;
380
381 num_valid_sets = 0;
382
383 for (i = 0; i < WM_SET_COUNT; i++) {
384 /* skip empty entries, the smu array has no holes*/
385 if (!bw_params->wm_table.entries[i].valid)
386 continue;
387
388 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
389 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
390 /* We will not select WM based on fclk, so leave it as unconstrained */
391 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
392 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
393
394 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
395 if (i == 0)
396 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
397 else {
398 /* add 1 to make it non-overlapping with next lvl */
399 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
400 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
401 }
402 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
403 bw_params->clk_table.entries[i].dcfclk_mhz;
404
405 } else {
406 /* unconstrained for memory retraining */
407 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
408 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
409
410 /* Modify previous watermark range to cover up to max */
411 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
412 }
413 num_valid_sets++;
414 }
415
416 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
417
418 /* modify the min and max to make sure we cover the whole range*/
419 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
420 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
421 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
422 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
423
424 /* This is for writeback only, does not matter currently as no writeback support*/
425 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
426 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
427 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
428 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
429 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
430 }
431
dcn315_notify_wm_ranges(struct clk_mgr * clk_mgr_base)432 static void dcn315_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
433 {
434 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
435 struct clk_mgr_dcn315 *clk_mgr_dcn315 = TO_CLK_MGR_DCN315(clk_mgr);
436 struct dcn315_watermarks *table = clk_mgr_dcn315->smu_wm_set.wm_set;
437
438 if (!clk_mgr->smu_ver)
439 return;
440
441 if (!table || clk_mgr_dcn315->smu_wm_set.mc_address.quad_part == 0)
442 return;
443
444 memset(table, 0, sizeof(*table));
445
446 dcn315_build_watermark_ranges(clk_mgr_base->bw_params, table);
447
448 dcn315_smu_set_dram_addr_high(clk_mgr,
449 clk_mgr_dcn315->smu_wm_set.mc_address.high_part);
450 dcn315_smu_set_dram_addr_low(clk_mgr,
451 clk_mgr_dcn315->smu_wm_set.mc_address.low_part);
452 dcn315_smu_transfer_wm_table_dram_2_smu(clk_mgr);
453 }
454
dcn315_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct dcn315_smu_dpm_clks * smu_dpm_clks)455 static void dcn315_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
456 struct dcn315_smu_dpm_clks *smu_dpm_clks)
457 {
458 DpmClocks_315_t *table = smu_dpm_clks->dpm_clks;
459
460 if (!clk_mgr->smu_ver)
461 return;
462
463 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
464 return;
465
466 memset(table, 0, sizeof(*table));
467
468 dcn315_smu_set_dram_addr_high(clk_mgr,
469 smu_dpm_clks->mc_address.high_part);
470 dcn315_smu_set_dram_addr_low(clk_mgr,
471 smu_dpm_clks->mc_address.low_part);
472 dcn315_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
473 }
474
dcn315_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal * clk_mgr,struct integrated_info * bios_info,const DpmClocks_315_t * clock_table)475 static void dcn315_clk_mgr_helper_populate_bw_params(
476 struct clk_mgr_internal *clk_mgr,
477 struct integrated_info *bios_info,
478 const DpmClocks_315_t *clock_table)
479 {
480 int i;
481 struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
482 uint32_t max_pstate = clock_table->NumDfPstatesEnabled - 1;
483 struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1];
484
485 /* For 315 we want to base clock table on dcfclk, need at least one entry regardless of pmfw table */
486 for (i = 0; i < clock_table->NumDcfClkLevelsEnabled; i++) {
487 int j;
488
489 /* DF table is sorted with clocks decreasing */
490 for (j = clock_table->NumDfPstatesEnabled - 2; j >= 0; j--) {
491 if (clock_table->DfPstateTable[j].Voltage <= clock_table->SocVoltage[i])
492 max_pstate = j;
493 }
494 /* Max DCFCLK should match up with max pstate */
495 if (i == clock_table->NumDcfClkLevelsEnabled - 1)
496 max_pstate = 0;
497
498 /* First search defaults for the clocks we don't read using closest lower or equal default dcfclk */
499 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--)
500 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])
501 break;
502 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz;
503 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz;
504 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz;
505
506 /* Now update clocks we do read */
507 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[max_pstate].FClk;
508 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[max_pstate].MemClk;
509 bw_params->clk_table.entries[i].voltage = clock_table->SocVoltage[i];
510 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
511 bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i];
512 bw_params->clk_table.entries[i].dispclk_mhz = clock_table->DispClocks[i];
513 bw_params->clk_table.entries[i].dppclk_mhz = clock_table->DppClocks[i];
514 bw_params->clk_table.entries[i].wck_ratio = 1;
515 }
516
517 /* Make sure to include at least one entry */
518 if (i == 0) {
519 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[0].FClk;
520 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[0].MemClk;
521 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[0].Voltage;
522 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[0];
523 bw_params->clk_table.entries[i].wck_ratio = 1;
524 i++;
525 }
526 bw_params->clk_table.num_entries = i;
527
528 /* Set any 0 clocks to max default setting. Not an issue for
529 * power since we aren't doing switching in such case anyway
530 */
531 for (i = 0; i < bw_params->clk_table.num_entries; i++) {
532 if (!bw_params->clk_table.entries[i].fclk_mhz) {
533 bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
534 bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz;
535 bw_params->clk_table.entries[i].voltage = def_max.voltage;
536 }
537 if (!bw_params->clk_table.entries[i].dcfclk_mhz)
538 bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz;
539 if (!bw_params->clk_table.entries[i].socclk_mhz)
540 bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz;
541 if (!bw_params->clk_table.entries[i].dispclk_mhz)
542 bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz;
543 if (!bw_params->clk_table.entries[i].dppclk_mhz)
544 bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz;
545 if (!bw_params->clk_table.entries[i].phyclk_mhz)
546 bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
547 if (!bw_params->clk_table.entries[i].phyclk_d18_mhz)
548 bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
549 if (!bw_params->clk_table.entries[i].dtbclk_mhz)
550 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
551 }
552
553 /* Make sure all highest default clocks are included*/
554 ASSERT(bw_params->clk_table.entries[i-1].phyclk_mhz == def_max.phyclk_mhz);
555 ASSERT(bw_params->clk_table.entries[i-1].phyclk_d18_mhz == def_max.phyclk_d18_mhz);
556 ASSERT(bw_params->clk_table.entries[i-1].dtbclk_mhz == def_max.dtbclk_mhz);
557 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
558 bw_params->vram_type = bios_info->memory_type;
559 bw_params->num_channels = bios_info->ma_channel_number;
560 bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
561
562 for (i = 0; i < WM_SET_COUNT; i++) {
563 bw_params->wm_table.entries[i].wm_inst = i;
564
565 if (i >= bw_params->clk_table.num_entries) {
566 bw_params->wm_table.entries[i].valid = false;
567 continue;
568 }
569
570 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
571 bw_params->wm_table.entries[i].valid = true;
572 }
573 }
574
dcn315_enable_pme_wa(struct clk_mgr * clk_mgr_base)575 static void dcn315_enable_pme_wa(struct clk_mgr *clk_mgr_base)
576 {
577 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
578
579 dcn315_smu_enable_pme_wa(clk_mgr);
580 }
581
582 static struct clk_mgr_funcs dcn315_funcs = {
583 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
584 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
585 .update_clocks = dcn315_update_clocks,
586 .init_clocks = dcn31_init_clocks,
587 .enable_pme_wa = dcn315_enable_pme_wa,
588 .are_clock_states_equal = dcn31_are_clock_states_equal,
589 .notify_wm_ranges = dcn315_notify_wm_ranges
590 };
591 extern struct clk_mgr_funcs dcn3_fpga_funcs;
592
dcn315_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_dcn315 * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)593 void dcn315_clk_mgr_construct(
594 struct dc_context *ctx,
595 struct clk_mgr_dcn315 *clk_mgr,
596 struct pp_smu_funcs *pp_smu,
597 struct dccg *dccg)
598 {
599 struct dcn315_smu_dpm_clks smu_dpm_clks = { 0 };
600
601 clk_mgr->base.base.ctx = ctx;
602 clk_mgr->base.base.funcs = &dcn315_funcs;
603
604 clk_mgr->base.pp_smu = pp_smu;
605
606 clk_mgr->base.dccg = dccg;
607 clk_mgr->base.dfs_bypass_disp_clk = 0;
608
609 clk_mgr->base.dprefclk_ss_percentage = 0;
610 clk_mgr->base.dprefclk_ss_divider = 1000;
611 clk_mgr->base.ss_on_dprefclk = false;
612 clk_mgr->base.dfs_ref_freq_khz = 48000;
613
614 clk_mgr->smu_wm_set.wm_set = (struct dcn315_watermarks *)dm_helpers_allocate_gpu_mem(
615 clk_mgr->base.base.ctx,
616 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
617 sizeof(struct dcn315_watermarks),
618 &clk_mgr->smu_wm_set.mc_address.quad_part);
619
620 if (!clk_mgr->smu_wm_set.wm_set) {
621 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
622 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
623 }
624 ASSERT(clk_mgr->smu_wm_set.wm_set);
625
626 smu_dpm_clks.dpm_clks = (DpmClocks_315_t *)dm_helpers_allocate_gpu_mem(
627 clk_mgr->base.base.ctx,
628 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
629 sizeof(DpmClocks_315_t),
630 &smu_dpm_clks.mc_address.quad_part);
631
632 if (smu_dpm_clks.dpm_clks == NULL) {
633 smu_dpm_clks.dpm_clks = &dummy_clocks;
634 smu_dpm_clks.mc_address.quad_part = 0;
635 }
636
637 ASSERT(smu_dpm_clks.dpm_clks);
638
639 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
640 clk_mgr->base.base.funcs = &dcn3_fpga_funcs;
641 } else {
642 struct clk_log_info log_info = {0};
643
644 clk_mgr->base.smu_ver = dcn315_smu_get_smu_version(&clk_mgr->base);
645
646 if (clk_mgr->base.smu_ver > 0)
647 clk_mgr->base.smu_present = true;
648
649 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
650 dcn315_bw_params.wm_table = lpddr5_wm_table;
651 } else {
652 dcn315_bw_params.wm_table = ddr5_wm_table;
653 }
654 /* Saved clocks configured at boot for debug purposes */
655 dcn315_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,
656 &clk_mgr->base.base, &log_info);
657
658 }
659
660 clk_mgr->base.base.dprefclk_khz = 600000;
661 clk_mgr->base.base.dprefclk_khz = dcn315_smu_get_dpref_clk(&clk_mgr->base);
662 clk_mgr->base.base.clks.ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz;
663 dce_clock_read_ss_info(&clk_mgr->base);
664 clk_mgr->base.base.clks.ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);
665
666 clk_mgr->base.base.bw_params = &dcn315_bw_params;
667
668 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
669 int i;
670
671 dcn315_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
672 DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"
673 "NumDispClkLevelsEnabled: %d\n"
674 "NumSocClkLevelsEnabled: %d\n"
675 "VcnClkLevelsEnabled: %d\n"
676 "NumDfPst atesEnabled: %d\n"
677 "MinGfxClk: %d\n"
678 "MaxGfxClk: %d\n",
679 smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
680 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
681 smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
682 smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
683 smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,
684 smu_dpm_clks.dpm_clks->MinGfxClk,
685 smu_dpm_clks.dpm_clks->MaxGfxClk);
686 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
687 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",
688 i,
689 smu_dpm_clks.dpm_clks->DcfClocks[i]);
690 }
691 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {
692 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",
693 i, smu_dpm_clks.dpm_clks->DispClocks[i]);
694 }
695 for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {
696 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",
697 i, smu_dpm_clks.dpm_clks->SocClocks[i]);
698 }
699 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++)
700 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",
701 i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
702
703 for (i = 0; i < NUM_DF_PSTATE_LEVELS; i++) {
704 DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n"
705 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].MemClk= %d\n"
706 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].Voltage = %d\n",
707 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,
708 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,
709 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);
710 }
711
712 if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
713 dcn315_clk_mgr_helper_populate_bw_params(
714 &clk_mgr->base,
715 ctx->dc_bios->integrated_info,
716 smu_dpm_clks.dpm_clks);
717 }
718 }
719
720 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
721 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
722 smu_dpm_clks.dpm_clks);
723 }
724
dcn315_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr_int)725 void dcn315_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
726 {
727 struct clk_mgr_dcn315 *clk_mgr = TO_CLK_MGR_DCN315(clk_mgr_int);
728
729 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
730 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
731 clk_mgr->smu_wm_set.wm_set);
732 }
733