1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27
28 #include "dccg.h"
29 #include "clk_mgr_internal.h"
30
31 // For dce12_get_dp_ref_freq_khz
32 #include "dce100/dce_clk_mgr.h"
33
34 // For dcn20_update_clocks_update_dpp_dto
35 #include "dcn20/dcn20_clk_mgr.h"
36
37
38
39 #include "dcn31_clk_mgr.h"
40
41 #include "reg_helper.h"
42 #include "core_types.h"
43 #include "dcn31_smu.h"
44 #include "dm_helpers.h"
45
46 /* TODO: remove this include once we ported over remaining clk mgr functions*/
47 #include "dcn30/dcn30_clk_mgr.h"
48
49 #include "dc_dmub_srv.h"
50 #include "link.h"
51
52 #include "logger_types.h"
53 #undef DC_LOGGER
54 #define DC_LOGGER \
55 clk_mgr->base.base.ctx->logger
56
57 #include "yellow_carp_offset.h"
58
59 #define regCLK1_CLK_PLL_REQ 0x0237
60 #define regCLK1_CLK_PLL_REQ_BASE_IDX 0
61
62 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
63 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
64 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
65 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
66 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
67 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
68
69 #define REG(reg_name) \
70 (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
71
72 #define TO_CLK_MGR_DCN31(clk_mgr)\
73 container_of(clk_mgr, struct clk_mgr_dcn31, base)
74
dcn31_get_active_display_cnt_wa(struct dc * dc,struct dc_state * context)75 static int dcn31_get_active_display_cnt_wa(
76 struct dc *dc,
77 struct dc_state *context)
78 {
79 int i, display_count;
80 bool tmds_present = false;
81
82 display_count = 0;
83 for (i = 0; i < context->stream_count; i++) {
84 const struct dc_stream_state *stream = context->streams[i];
85
86 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
87 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
88 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
89 tmds_present = true;
90 }
91
92 for (i = 0; i < dc->link_count; i++) {
93 const struct dc_link *link = dc->links[i];
94
95 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
96 if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
97 link->link_enc->funcs->is_dig_enabled(link->link_enc))
98 display_count++;
99 }
100
101 /* WA for hang on HDMI after display off back back on*/
102 if (display_count == 0 && tmds_present)
103 display_count = 1;
104
105 return display_count;
106 }
107
dcn31_disable_otg_wa(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool disable)108 static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
109 {
110 struct dc *dc = clk_mgr_base->ctx->dc;
111 int i;
112
113 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
114 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
115
116 if (pipe->top_pipe || pipe->prev_odm_pipe)
117 continue;
118 if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {
119 if (disable) {
120 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
121 reset_sync_context_for_pipe(dc, context, i);
122 } else
123 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
124 }
125 }
126 }
127
dcn31_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)128 void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
129 struct dc_state *context,
130 bool safe_to_lower)
131 {
132 union dmub_rb_cmd cmd;
133 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
134 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
135 struct dc *dc = clk_mgr_base->ctx->dc;
136 int display_count;
137 bool update_dppclk = false;
138 bool update_dispclk = false;
139 bool dpp_clock_lowered = false;
140
141 if (dc->work_arounds.skip_clock_update)
142 return;
143
144 /*
145 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
146 * also if safe to lower is false, we just go in the higher state
147 */
148 if (safe_to_lower) {
149 if (new_clocks->zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW &&
150 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
151 dcn31_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support);
152 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, true);
153 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
154 }
155
156 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
157 dcn31_smu_set_dtbclk(clk_mgr, false);
158 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
159 }
160 /* check that we're not already in lower */
161 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
162 display_count = dcn31_get_active_display_cnt_wa(dc, context);
163 /* if we can go lower, go lower */
164 if (display_count == 0) {
165 union display_idle_optimization_u idle_info = { 0 };
166 idle_info.idle_info.df_request_disabled = 1;
167 idle_info.idle_info.phy_ref_clk_off = 1;
168 idle_info.idle_info.s0i2_rdy = 1;
169 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
170 /* update power state */
171 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
172 }
173 }
174 } else {
175 if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW &&
176 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
177 dcn31_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW);
178 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, false);
179 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
180 }
181
182 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
183 dcn31_smu_set_dtbclk(clk_mgr, true);
184 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
185 }
186
187 /* check that we're not already in D0 */
188 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
189 union display_idle_optimization_u idle_info = { 0 };
190 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
191 /* update power state */
192 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
193 }
194 }
195
196 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
197 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
198 dcn31_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
199 }
200
201 if (should_set_clock(safe_to_lower,
202 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
203 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
204 dcn31_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
205 }
206
207 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
208 if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
209 if (new_clocks->dppclk_khz < 100000)
210 new_clocks->dppclk_khz = 100000;
211 }
212
213 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
214 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
215 dpp_clock_lowered = true;
216 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
217 update_dppclk = true;
218 }
219
220 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
221 dcn31_disable_otg_wa(clk_mgr_base, context, true);
222
223 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
224 dcn31_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
225 dcn31_disable_otg_wa(clk_mgr_base, context, false);
226
227 update_dispclk = true;
228 }
229
230 if (dpp_clock_lowered) {
231 // increase per DPP DTO before lowering global dppclk
232 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
233 dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
234 } else {
235 // increase global DPPCLK before lowering per DPP DTO
236 if (update_dppclk || update_dispclk)
237 dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
238 // always update dtos unless clock is lowered and not safe to lower
239 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
240 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
241 }
242
243 // notify DMCUB of latest clocks
244 memset(&cmd, 0, sizeof(cmd));
245 cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
246 cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
247 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
248 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
249 clk_mgr_base->clks.dcfclk_deep_sleep_khz;
250 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
251 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
252
253 dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
254 dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
255 dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
256 }
257
get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)258 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
259 {
260 /* get FbMult value */
261 struct fixed31_32 pll_req;
262 unsigned int fbmult_frac_val = 0;
263 unsigned int fbmult_int_val = 0;
264
265 /*
266 * Register value of fbmult is in 8.16 format, we are converting to 31.32
267 * to leverage the fix point operations available in driver
268 */
269
270 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
271 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
272
273 pll_req = dc_fixpt_from_int(fbmult_int_val);
274
275 /*
276 * since fractional part is only 16 bit in register definition but is 32 bit
277 * in our fix point definiton, need to shift left by 16 to obtain correct value
278 */
279 pll_req.value |= fbmult_frac_val << 16;
280
281 /* multiply by REFCLK period */
282 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
283
284 /* integer part is now VCO frequency in kHz */
285 return dc_fixpt_floor(pll_req);
286 }
287
dcn31_enable_pme_wa(struct clk_mgr * clk_mgr_base)288 static void dcn31_enable_pme_wa(struct clk_mgr *clk_mgr_base)
289 {
290 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
291
292 dcn31_smu_enable_pme_wa(clk_mgr);
293 }
294
dcn31_init_clocks(struct clk_mgr * clk_mgr)295 void dcn31_init_clocks(struct clk_mgr *clk_mgr)
296 {
297 uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;
298
299 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
300 // Assumption is that boot state always supports pstate
301 clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk
302 clk_mgr->clks.p_state_change_support = true;
303 clk_mgr->clks.prev_p_state_change_support = true;
304 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
305 clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;
306 }
307
dcn31_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)308 bool dcn31_are_clock_states_equal(struct dc_clocks *a,
309 struct dc_clocks *b)
310 {
311 if (a->dispclk_khz != b->dispclk_khz)
312 return false;
313 else if (a->dppclk_khz != b->dppclk_khz)
314 return false;
315 else if (a->dcfclk_khz != b->dcfclk_khz)
316 return false;
317 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
318 return false;
319 else if (a->zstate_support != b->zstate_support)
320 return false;
321 else if (a->dtbclk_en != b->dtbclk_en)
322 return false;
323
324 return true;
325 }
326
dcn31_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info)327 static void dcn31_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
328 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
329 {
330 return;
331 }
332
333 static struct clk_bw_params dcn31_bw_params = {
334 .vram_type = Ddr4MemType,
335 .num_channels = 1,
336 .clk_table = {
337 .num_entries = 4,
338 },
339
340 };
341
342 static struct wm_table ddr5_wm_table = {
343 .entries = {
344 {
345 .wm_inst = WM_A,
346 .wm_type = WM_TYPE_PSTATE_CHG,
347 .pstate_latency_us = 11.72,
348 .sr_exit_time_us = 9,
349 .sr_enter_plus_exit_time_us = 11,
350 .valid = true,
351 },
352 {
353 .wm_inst = WM_B,
354 .wm_type = WM_TYPE_PSTATE_CHG,
355 .pstate_latency_us = 11.72,
356 .sr_exit_time_us = 9,
357 .sr_enter_plus_exit_time_us = 11,
358 .valid = true,
359 },
360 {
361 .wm_inst = WM_C,
362 .wm_type = WM_TYPE_PSTATE_CHG,
363 .pstate_latency_us = 11.72,
364 .sr_exit_time_us = 9,
365 .sr_enter_plus_exit_time_us = 11,
366 .valid = true,
367 },
368 {
369 .wm_inst = WM_D,
370 .wm_type = WM_TYPE_PSTATE_CHG,
371 .pstate_latency_us = 11.72,
372 .sr_exit_time_us = 9,
373 .sr_enter_plus_exit_time_us = 11,
374 .valid = true,
375 },
376 }
377 };
378
379 static struct wm_table lpddr5_wm_table = {
380 .entries = {
381 {
382 .wm_inst = WM_A,
383 .wm_type = WM_TYPE_PSTATE_CHG,
384 .pstate_latency_us = 11.65333,
385 .sr_exit_time_us = 11.5,
386 .sr_enter_plus_exit_time_us = 14.5,
387 .valid = true,
388 },
389 {
390 .wm_inst = WM_B,
391 .wm_type = WM_TYPE_PSTATE_CHG,
392 .pstate_latency_us = 11.65333,
393 .sr_exit_time_us = 11.5,
394 .sr_enter_plus_exit_time_us = 14.5,
395 .valid = true,
396 },
397 {
398 .wm_inst = WM_C,
399 .wm_type = WM_TYPE_PSTATE_CHG,
400 .pstate_latency_us = 11.65333,
401 .sr_exit_time_us = 11.5,
402 .sr_enter_plus_exit_time_us = 14.5,
403 .valid = true,
404 },
405 {
406 .wm_inst = WM_D,
407 .wm_type = WM_TYPE_PSTATE_CHG,
408 .pstate_latency_us = 11.65333,
409 .sr_exit_time_us = 11.5,
410 .sr_enter_plus_exit_time_us = 14.5,
411 .valid = true,
412 },
413 }
414 };
415
416 static DpmClocks_t dummy_clocks;
417
418 static struct dcn31_watermarks dummy_wms = { 0 };
419
dcn31_build_watermark_ranges(struct clk_bw_params * bw_params,struct dcn31_watermarks * table)420 static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn31_watermarks *table)
421 {
422 int i, num_valid_sets;
423
424 num_valid_sets = 0;
425
426 for (i = 0; i < WM_SET_COUNT; i++) {
427 /* skip empty entries, the smu array has no holes*/
428 if (!bw_params->wm_table.entries[i].valid)
429 continue;
430
431 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
432 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
433 /* We will not select WM based on fclk, so leave it as unconstrained */
434 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
435 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
436
437 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
438 if (i == 0)
439 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
440 else {
441 /* add 1 to make it non-overlapping with next lvl */
442 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
443 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
444 }
445 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
446 bw_params->clk_table.entries[i].dcfclk_mhz;
447
448 } else {
449 /* unconstrained for memory retraining */
450 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
451 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
452
453 /* Modify previous watermark range to cover up to max */
454 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
455 }
456 num_valid_sets++;
457 }
458
459 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
460
461 /* modify the min and max to make sure we cover the whole range*/
462 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
463 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
464 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
465 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
466
467 /* This is for writeback only, does not matter currently as no writeback support*/
468 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
469 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
470 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
471 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
472 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
473 }
474
dcn31_notify_wm_ranges(struct clk_mgr * clk_mgr_base)475 static void dcn31_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
476 {
477 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
478 struct clk_mgr_dcn31 *clk_mgr_dcn31 = TO_CLK_MGR_DCN31(clk_mgr);
479 struct dcn31_watermarks *table = clk_mgr_dcn31->smu_wm_set.wm_set;
480
481 if (!clk_mgr->smu_ver)
482 return;
483
484 if (!table || clk_mgr_dcn31->smu_wm_set.mc_address.quad_part == 0)
485 return;
486
487 memset(table, 0, sizeof(*table));
488
489 dcn31_build_watermark_ranges(clk_mgr_base->bw_params, table);
490
491 dcn31_smu_set_dram_addr_high(clk_mgr,
492 clk_mgr_dcn31->smu_wm_set.mc_address.high_part);
493 dcn31_smu_set_dram_addr_low(clk_mgr,
494 clk_mgr_dcn31->smu_wm_set.mc_address.low_part);
495 dcn31_smu_transfer_wm_table_dram_2_smu(clk_mgr);
496 }
497
dcn31_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct dcn31_smu_dpm_clks * smu_dpm_clks)498 static void dcn31_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
499 struct dcn31_smu_dpm_clks *smu_dpm_clks)
500 {
501 DpmClocks_t *table = smu_dpm_clks->dpm_clks;
502
503 if (!clk_mgr->smu_ver)
504 return;
505
506 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
507 return;
508
509 memset(table, 0, sizeof(*table));
510
511 dcn31_smu_set_dram_addr_high(clk_mgr,
512 smu_dpm_clks->mc_address.high_part);
513 dcn31_smu_set_dram_addr_low(clk_mgr,
514 smu_dpm_clks->mc_address.low_part);
515 dcn31_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
516 }
517
find_max_clk_value(const uint32_t clocks[],uint32_t num_clocks)518 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
519 {
520 uint32_t max = 0;
521 int i;
522
523 for (i = 0; i < num_clocks; ++i) {
524 if (clocks[i] > max)
525 max = clocks[i];
526 }
527
528 return max;
529 }
530
find_clk_for_voltage(const DpmClocks_t * clock_table,const uint32_t clocks[],unsigned int voltage)531 static unsigned int find_clk_for_voltage(
532 const DpmClocks_t *clock_table,
533 const uint32_t clocks[],
534 unsigned int voltage)
535 {
536 int i;
537 int max_voltage = 0;
538 int clock = 0;
539
540 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) {
541 if (clock_table->SocVoltage[i] == voltage) {
542 return clocks[i];
543 } else if (clock_table->SocVoltage[i] >= max_voltage &&
544 clock_table->SocVoltage[i] < voltage) {
545 max_voltage = clock_table->SocVoltage[i];
546 clock = clocks[i];
547 }
548 }
549
550 ASSERT(clock);
551 return clock;
552 }
553
dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal * clk_mgr,struct integrated_info * bios_info,const DpmClocks_t * clock_table)554 static void dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,
555 struct integrated_info *bios_info,
556 const DpmClocks_t *clock_table)
557 {
558 int i, j;
559 struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
560 uint32_t max_dispclk = 0, max_dppclk = 0;
561
562 j = -1;
563
564 ASSERT(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL);
565
566 /* Find lowest DPM, FCLK is filled in reverse order*/
567
568 for (i = NUM_DF_PSTATE_LEVELS - 1; i >= 0; i--) {
569 if (clock_table->DfPstateTable[i].FClk != 0) {
570 j = i;
571 break;
572 }
573 }
574
575 if (j == -1) {
576 /* clock table is all 0s, just use our own hardcode */
577 ASSERT(0);
578 return;
579 }
580
581 bw_params->clk_table.num_entries = j + 1;
582
583 /* dispclk and dppclk can be max at any voltage, same number of levels for both */
584 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
585 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
586 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
587 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled);
588 } else {
589 ASSERT(0);
590 }
591
592 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
593 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;
594 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;
595 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;
596 switch (clock_table->DfPstateTable[j].WckRatio) {
597 case WCK_RATIO_1_2:
598 bw_params->clk_table.entries[i].wck_ratio = 2;
599 break;
600 case WCK_RATIO_1_4:
601 bw_params->clk_table.entries[i].wck_ratio = 4;
602 break;
603 default:
604 bw_params->clk_table.entries[i].wck_ratio = 1;
605 }
606 bw_params->clk_table.entries[i].dcfclk_mhz = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
607 bw_params->clk_table.entries[i].socclk_mhz = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage);
608 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
609 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
610 }
611
612 bw_params->vram_type = bios_info->memory_type;
613
614 bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
615 //bw_params->dram_channel_width_bytes = dc->ctx->asic_id.vram_width;
616 bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4;
617 for (i = 0; i < WM_SET_COUNT; i++) {
618 bw_params->wm_table.entries[i].wm_inst = i;
619
620 if (i >= bw_params->clk_table.num_entries) {
621 bw_params->wm_table.entries[i].valid = false;
622 continue;
623 }
624
625 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
626 bw_params->wm_table.entries[i].valid = true;
627 }
628 }
629
dcn31_set_low_power_state(struct clk_mgr * clk_mgr_base)630 static void dcn31_set_low_power_state(struct clk_mgr *clk_mgr_base)
631 {
632 int display_count;
633 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
634 struct dc *dc = clk_mgr_base->ctx->dc;
635 struct dc_state *context = dc->current_state;
636
637 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
638 display_count = dcn31_get_active_display_cnt_wa(dc, context);
639 /* if we can go lower, go lower */
640 if (display_count == 0) {
641 union display_idle_optimization_u idle_info = { 0 };
642
643 idle_info.idle_info.df_request_disabled = 1;
644 idle_info.idle_info.phy_ref_clk_off = 1;
645 idle_info.idle_info.s0i2_rdy = 1;
646 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
647 /* update power state */
648 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
649 }
650 }
651 }
652
dcn31_get_dtb_ref_freq_khz(struct clk_mgr * clk_mgr_base)653 int dcn31_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base)
654 {
655 return clk_mgr_base->clks.ref_dtbclk_khz;
656 }
657
658 static struct clk_mgr_funcs dcn31_funcs = {
659 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
660 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
661 .update_clocks = dcn31_update_clocks,
662 .init_clocks = dcn31_init_clocks,
663 .enable_pme_wa = dcn31_enable_pme_wa,
664 .are_clock_states_equal = dcn31_are_clock_states_equal,
665 .notify_wm_ranges = dcn31_notify_wm_ranges,
666 .set_low_power_state = dcn31_set_low_power_state
667 };
668 extern struct clk_mgr_funcs dcn3_fpga_funcs;
669
dcn31_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_dcn31 * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)670 void dcn31_clk_mgr_construct(
671 struct dc_context *ctx,
672 struct clk_mgr_dcn31 *clk_mgr,
673 struct pp_smu_funcs *pp_smu,
674 struct dccg *dccg)
675 {
676 struct dcn31_smu_dpm_clks smu_dpm_clks = { 0 };
677
678 clk_mgr->base.base.ctx = ctx;
679 clk_mgr->base.base.funcs = &dcn31_funcs;
680
681 clk_mgr->base.pp_smu = pp_smu;
682
683 clk_mgr->base.dccg = dccg;
684 clk_mgr->base.dfs_bypass_disp_clk = 0;
685
686 clk_mgr->base.dprefclk_ss_percentage = 0;
687 clk_mgr->base.dprefclk_ss_divider = 1000;
688 clk_mgr->base.ss_on_dprefclk = false;
689 clk_mgr->base.dfs_ref_freq_khz = 48000;
690
691 clk_mgr->smu_wm_set.wm_set = (struct dcn31_watermarks *)dm_helpers_allocate_gpu_mem(
692 clk_mgr->base.base.ctx,
693 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
694 sizeof(struct dcn31_watermarks),
695 &clk_mgr->smu_wm_set.mc_address.quad_part);
696
697 if (!clk_mgr->smu_wm_set.wm_set) {
698 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
699 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
700 }
701 ASSERT(clk_mgr->smu_wm_set.wm_set);
702
703 smu_dpm_clks.dpm_clks = (DpmClocks_t *)dm_helpers_allocate_gpu_mem(
704 clk_mgr->base.base.ctx,
705 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
706 sizeof(DpmClocks_t),
707 &smu_dpm_clks.mc_address.quad_part);
708
709 if (smu_dpm_clks.dpm_clks == NULL) {
710 smu_dpm_clks.dpm_clks = &dummy_clocks;
711 smu_dpm_clks.mc_address.quad_part = 0;
712 }
713
714 ASSERT(smu_dpm_clks.dpm_clks);
715
716 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
717 clk_mgr->base.base.funcs = &dcn3_fpga_funcs;
718 } else {
719 struct clk_log_info log_info = {0};
720
721 clk_mgr->base.smu_ver = dcn31_smu_get_smu_version(&clk_mgr->base);
722
723 if (clk_mgr->base.smu_ver)
724 clk_mgr->base.smu_present = true;
725
726 /* TODO: Check we get what we expect during bringup */
727 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
728
729 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
730 dcn31_bw_params.wm_table = lpddr5_wm_table;
731 } else {
732 dcn31_bw_params.wm_table = ddr5_wm_table;
733 }
734 /* Saved clocks configured at boot for debug purposes */
735 dcn31_dump_clk_registers(&clk_mgr->base.base.boot_snapshot,
736 &clk_mgr->base.base, &log_info);
737
738 }
739
740 clk_mgr->base.base.dprefclk_khz = 600000;
741 clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;
742 dce_clock_read_ss_info(&clk_mgr->base);
743 /*if bios enabled SS, driver needs to adjust dtb clock, only enable with correct bios*/
744 //clk_mgr->base.dccg->ref_dtbclk_khz = dce_adjust_dp_ref_freq_for_ss(clk_mgr_internal, clk_mgr->base.base.dprefclk_khz);
745
746 clk_mgr->base.base.bw_params = &dcn31_bw_params;
747
748 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
749 int i;
750
751 dcn31_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
752
753 DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"
754 "NumDispClkLevelsEnabled: %d\n"
755 "NumSocClkLevelsEnabled: %d\n"
756 "VcnClkLevelsEnabled: %d\n"
757 "NumDfPst atesEnabled: %d\n"
758 "MinGfxClk: %d\n"
759 "MaxGfxClk: %d\n",
760 smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
761 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
762 smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
763 smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
764 smu_dpm_clks.dpm_clks->NumDfPstatesEnabled,
765 smu_dpm_clks.dpm_clks->MinGfxClk,
766 smu_dpm_clks.dpm_clks->MaxGfxClk);
767 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
768 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",
769 i,
770 smu_dpm_clks.dpm_clks->DcfClocks[i]);
771 }
772 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {
773 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",
774 i, smu_dpm_clks.dpm_clks->DispClocks[i]);
775 }
776 for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {
777 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",
778 i, smu_dpm_clks.dpm_clks->SocClocks[i]);
779 }
780 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++)
781 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",
782 i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
783
784 for (i = 0; i < NUM_DF_PSTATE_LEVELS; i++) {
785 DC_LOG_SMU("smu_dpm_clks.dpm_clks.DfPstateTable[%d].FClk = %d\n"
786 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].MemClk= %d\n"
787 "smu_dpm_clks.dpm_clks->DfPstateTable[%d].Voltage = %d\n",
788 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].FClk,
789 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].MemClk,
790 i, smu_dpm_clks.dpm_clks->DfPstateTable[i].Voltage);
791 }
792 if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
793 dcn31_clk_mgr_helper_populate_bw_params(
794 &clk_mgr->base,
795 ctx->dc_bios->integrated_info,
796 smu_dpm_clks.dpm_clks);
797 }
798 }
799
800 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
801 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
802 smu_dpm_clks.dpm_clks);
803 }
804
dcn31_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr_int)805 void dcn31_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
806 {
807 struct clk_mgr_dcn31 *clk_mgr = TO_CLK_MGR_DCN31(clk_mgr_int);
808
809 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
810 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
811 clk_mgr->smu_wm_set.wm_set);
812 }
813