1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dccg.h"
27 #include "clk_mgr_internal.h"
28
29 #include "dcn32/dcn32_clk_mgr_smu_msg.h"
30 #include "dcn20/dcn20_clk_mgr.h"
31 #include "dce100/dce_clk_mgr.h"
32 #include "dcn31/dcn31_clk_mgr.h"
33 #include "reg_helper.h"
34 #include "core_types.h"
35 #include "dm_helpers.h"
36 #include "link.h"
37
38 #include "atomfirmware.h"
39 #include "smu13_driver_if.h"
40
41 #include "dcn/dcn_3_2_0_offset.h"
42 #include "dcn/dcn_3_2_0_sh_mask.h"
43
44 #include "dcn32/dcn32_clk_mgr.h"
45 #include "dml/dcn32/dcn32_fpu.h"
46
47 #define DCN_BASE__INST0_SEG1 0x000000C0
48
49 #define mmCLK1_CLK_PLL_REQ 0x16E37
50 #define mmCLK1_CLK0_DFS_CNTL 0x16E69
51 #define mmCLK1_CLK1_DFS_CNTL 0x16E6C
52 #define mmCLK1_CLK2_DFS_CNTL 0x16E6F
53 #define mmCLK1_CLK3_DFS_CNTL 0x16E72
54 #define mmCLK1_CLK4_DFS_CNTL 0x16E75
55
56 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001ffUL
57 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000f000UL
58 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xffff0000UL
59 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x00000000
60 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0x0000000c
61 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x00000010
62
63 #define mmCLK01_CLK0_CLK_PLL_REQ 0x16E37
64 #define mmCLK01_CLK0_CLK0_DFS_CNTL 0x16E64
65 #define mmCLK01_CLK0_CLK1_DFS_CNTL 0x16E67
66 #define mmCLK01_CLK0_CLK2_DFS_CNTL 0x16E6A
67 #define mmCLK01_CLK0_CLK3_DFS_CNTL 0x16E6D
68 #define mmCLK01_CLK0_CLK4_DFS_CNTL 0x16E70
69
70 #define CLK0_CLK_PLL_REQ__FbMult_int_MASK 0x000001ffL
71 #define CLK0_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000f000L
72 #define CLK0_CLK_PLL_REQ__FbMult_frac_MASK 0xffff0000L
73 #define CLK0_CLK_PLL_REQ__FbMult_int__SHIFT 0x00000000
74 #define CLK0_CLK_PLL_REQ__PllSpineDiv__SHIFT 0x0000000c
75 #define CLK0_CLK_PLL_REQ__FbMult_frac__SHIFT 0x00000010
76
77 #undef FN
78 #define FN(reg_name, field_name) \
79 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
80
81 #define REG(reg) \
82 (clk_mgr->regs->reg)
83
84 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
85
86 #define BASE(seg) BASE_INNER(seg)
87
88 #define SR(reg_name)\
89 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
90 reg ## reg_name
91
92 #define CLK_SR_DCN32(reg_name)\
93 .reg_name = mm ## reg_name
94
95 static const struct clk_mgr_registers clk_mgr_regs_dcn32 = {
96 CLK_REG_LIST_DCN32()
97 };
98
99 static const struct clk_mgr_shift clk_mgr_shift_dcn32 = {
100 CLK_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
101 };
102
103 static const struct clk_mgr_mask clk_mgr_mask_dcn32 = {
104 CLK_COMMON_MASK_SH_LIST_DCN32(_MASK)
105 };
106
107
108 #define CLK_SR_DCN321(reg_name, block, inst)\
109 .reg_name = mm ## block ## _ ## reg_name
110
111 static const struct clk_mgr_registers clk_mgr_regs_dcn321 = {
112 CLK_REG_LIST_DCN321()
113 };
114
115 static const struct clk_mgr_shift clk_mgr_shift_dcn321 = {
116 CLK_COMMON_MASK_SH_LIST_DCN321(__SHIFT)
117 };
118
119 static const struct clk_mgr_mask clk_mgr_mask_dcn321 = {
120 CLK_COMMON_MASK_SH_LIST_DCN321(_MASK)
121 };
122
123
124 /* Query SMU for all clock states for a particular clock */
dcn32_init_single_clock(struct clk_mgr_internal * clk_mgr,PPCLK_e clk,unsigned int * entry_0,unsigned int * num_levels)125 static void dcn32_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0,
126 unsigned int *num_levels)
127 {
128 unsigned int i;
129 char *entry_i = (char *)entry_0;
130
131 uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
132
133 if (ret & (1 << 31))
134 /* fine-grained, only min and max */
135 *num_levels = 2;
136 else
137 /* discrete, a number of fixed states */
138 /* will set num_levels to 0 on failure */
139 *num_levels = ret & 0xFF;
140
141 /* if the initial message failed, num_levels will be 0 */
142 for (i = 0; i < *num_levels; i++) {
143 *((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
144 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
145 }
146 }
147
dcn32_build_wm_range_table(struct clk_mgr_internal * clk_mgr)148 static void dcn32_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
149 {
150 DC_FP_START();
151 dcn32_build_wm_range_table_fpu(clk_mgr);
152 DC_FP_END();
153 }
154
dcn32_init_clocks(struct clk_mgr * clk_mgr_base)155 void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
156 {
157 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
158 unsigned int num_levels;
159 struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
160 unsigned int i;
161
162 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
163 clk_mgr_base->clks.p_state_change_support = true;
164 clk_mgr_base->clks.prev_p_state_change_support = true;
165 clk_mgr_base->clks.fclk_prev_p_state_change_support = true;
166 clk_mgr->smu_present = false;
167 clk_mgr->dpm_present = false;
168
169 if (!clk_mgr_base->bw_params)
170 return;
171
172 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))
173 clk_mgr->smu_present = true;
174
175 if (!clk_mgr->smu_present)
176 return;
177
178 dcn30_smu_check_driver_if_version(clk_mgr);
179 dcn30_smu_check_msg_header_version(clk_mgr);
180
181 /* DCFCLK */
182 dcn32_init_single_clock(clk_mgr, PPCLK_DCFCLK,
183 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
184 &num_entries_per_clk->num_dcfclk_levels);
185
186 /* SOCCLK */
187 dcn32_init_single_clock(clk_mgr, PPCLK_SOCCLK,
188 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
189 &num_entries_per_clk->num_socclk_levels);
190
191 /* DTBCLK */
192 if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch)
193 dcn32_init_single_clock(clk_mgr, PPCLK_DTBCLK,
194 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
195 &num_entries_per_clk->num_dtbclk_levels);
196
197 /* DISPCLK */
198 dcn32_init_single_clock(clk_mgr, PPCLK_DISPCLK,
199 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
200 &num_entries_per_clk->num_dispclk_levels);
201 num_levels = num_entries_per_clk->num_dispclk_levels;
202
203 if (num_entries_per_clk->num_dcfclk_levels &&
204 num_entries_per_clk->num_dtbclk_levels &&
205 num_entries_per_clk->num_dispclk_levels)
206 clk_mgr->dpm_present = true;
207
208 if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) {
209 for (i = 0; i < num_levels; i++)
210 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
211 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz))
212 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz
213 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz);
214 }
215 for (i = 0; i < num_levels; i++)
216 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz > 1950)
217 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz = 1950;
218
219 if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) {
220 for (i = 0; i < num_levels; i++)
221 if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
222 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz))
223 clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz
224 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz);
225 }
226
227 /* Get UCLK, update bounding box */
228 clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
229
230 DC_FP_START();
231 /* WM range table */
232 dcn32_build_wm_range_table(clk_mgr);
233 DC_FP_END();
234 }
235
236 /* Since DPPCLK request to PMFW needs to be exact (due to DPP DTO programming),
237 * update DPPCLK to be the exact frequency that will be set after the DPPCLK
238 * divider is updated. This will prevent rounding issues that could cause DPP
239 * refclk and DPP DTO to not match up.
240 */
dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal * clk_mgr,struct dc_clocks * new_clocks)241 static void dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks)
242 {
243 int dpp_divider = 0;
244 int disp_divider = 0;
245
246 if (new_clocks->dppclk_khz) {
247 dpp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
248 * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dppclk_khz;
249 new_clocks->dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;
250 }
251 if (new_clocks->dispclk_khz > 0) {
252 disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
253 * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dispclk_khz;
254 new_clocks->dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider;
255 }
256 }
257
dcn32_update_clocks_update_dentist(struct clk_mgr_internal * clk_mgr,struct dc_state * context,uint32_t old_dispclk_khz)258 static void dcn32_update_clocks_update_dentist(
259 struct clk_mgr_internal *clk_mgr,
260 struct dc_state *context,
261 uint32_t old_dispclk_khz)
262 {
263 uint32_t new_disp_divider = 0;
264 uint32_t old_disp_divider = 0;
265 uint32_t new_dispclk_wdivider = 0;
266 uint32_t old_dispclk_wdivider = 0;
267 uint32_t i;
268
269 if (old_dispclk_khz == 0 || clk_mgr->base.clks.dispclk_khz == 0)
270 return;
271
272 new_disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
273 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz;
274 old_disp_divider = DENTIST_DIVIDER_RANGE_SCALE_FACTOR
275 * clk_mgr->base.dentist_vco_freq_khz / old_dispclk_khz;
276
277 new_dispclk_wdivider = dentist_get_did_from_divider(new_disp_divider);
278 old_dispclk_wdivider = dentist_get_did_from_divider(old_disp_divider);
279
280 /* When changing divider to or from 127, some extra programming is required to prevent corruption */
281 if (old_dispclk_wdivider == 127 && new_dispclk_wdivider != 127) {
282 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
283 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
284 uint32_t fifo_level;
285 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;
286 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
287 int32_t N;
288 int32_t j;
289
290 if (!pipe_ctx->stream)
291 continue;
292 /* Virtual encoders don't have this function */
293 if (!stream_enc->funcs->get_fifo_cal_average_level)
294 continue;
295 fifo_level = stream_enc->funcs->get_fifo_cal_average_level(
296 stream_enc);
297 N = fifo_level / 4;
298 dccg->funcs->set_fifo_errdet_ovr_en(
299 dccg,
300 true);
301 for (j = 0; j < N - 4; j++)
302 dccg->funcs->otg_drop_pixel(
303 dccg,
304 pipe_ctx->stream_res.tg->inst);
305 dccg->funcs->set_fifo_errdet_ovr_en(
306 dccg,
307 false);
308 }
309 } else if (new_dispclk_wdivider == 127 && old_dispclk_wdivider != 127) {
310 /* request clock with 126 divider first */
311 uint32_t temp_disp_divider = dentist_get_divider_from_did(126);
312 uint32_t temp_dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / temp_disp_divider;
313
314 if (clk_mgr->smu_present)
315 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(temp_dispclk_khz));
316
317 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
318 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
319 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg;
320 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
321 uint32_t fifo_level;
322 int32_t N;
323 int32_t j;
324
325 if (!pipe_ctx->stream)
326 continue;
327 /* Virtual encoders don't have this function */
328 if (!stream_enc->funcs->get_fifo_cal_average_level)
329 continue;
330 fifo_level = stream_enc->funcs->get_fifo_cal_average_level(
331 stream_enc);
332 N = fifo_level / 4;
333 dccg->funcs->set_fifo_errdet_ovr_en(dccg, true);
334 for (j = 0; j < 12 - N; j++)
335 dccg->funcs->otg_add_pixel(dccg,
336 pipe_ctx->stream_res.tg->inst);
337 dccg->funcs->set_fifo_errdet_ovr_en(dccg, false);
338 }
339 }
340
341 /* do requested DISPCLK updates*/
342 if (clk_mgr->smu_present)
343 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr->base.clks.dispclk_khz));
344 }
345
dcn32_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)346 static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
347 struct dc_state *context,
348 bool safe_to_lower)
349 {
350 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
351 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
352 struct dc *dc = clk_mgr_base->ctx->dc;
353 int display_count;
354 bool update_dppclk = false;
355 bool update_dispclk = false;
356 bool enter_display_off = false;
357 bool dpp_clock_lowered = false;
358 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
359 bool force_reset = false;
360 bool update_uclk = false, update_fclk = false;
361 bool p_state_change_support;
362 bool fclk_p_state_change_support;
363 int total_plane_count;
364 int old_dispclk_khz = clk_mgr_base->clks.dispclk_khz;
365
366 if (dc->work_arounds.skip_clock_update)
367 return;
368
369 if (clk_mgr_base->clks.dispclk_khz == 0 ||
370 (dc->debug.force_clock_mode & 0x1)) {
371 /* This is from resume or boot up, if forced_clock cfg option used,
372 * we bypass program dispclk and DPPCLK, but need set them for S3.
373 */
374 force_reset = true;
375
376 dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
377
378 /* Force_clock_mode 0x1: force reset the clock even it is the same clock
379 * as long as it is in Passive level.
380 */
381 }
382 display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
383
384 if (display_count == 0)
385 enter_display_off = true;
386
387 if (clk_mgr->smu_present) {
388 if (enter_display_off == safe_to_lower)
389 dcn30_smu_set_num_of_displays(clk_mgr, display_count);
390
391 clk_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support;
392
393 total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
394 fclk_p_state_change_support = new_clocks->fclk_p_state_change_support || (total_plane_count == 0);
395
396 if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) {
397 clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;
398
399 /* To enable FCLK P-state switching, send FCLK_PSTATE_SUPPORTED message to PMFW */
400 if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && clk_mgr_base->clks.fclk_p_state_change_support) {
401 /* Handle the code for sending a message to PMFW that FCLK P-state change is supported */
402 dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_SUPPORTED);
403 }
404 }
405
406 if (dc->debug.force_min_dcfclk_mhz > 0)
407 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
408 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
409
410 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
411 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
412 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
413 }
414
415 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
416 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
417 dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));
418 }
419
420 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
421 /* We don't actually care about socclk, don't notify SMU of hard min */
422 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
423
424 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
425 clk_mgr_base->clks.prev_num_ways = clk_mgr_base->clks.num_ways;
426
427 if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
428 clk_mgr_base->clks.num_ways < new_clocks->num_ways) {
429 clk_mgr_base->clks.num_ways = new_clocks->num_ways;
430 dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
431 }
432
433
434 p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);
435 if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
436 clk_mgr_base->clks.p_state_change_support = p_state_change_support;
437
438 /* to disable P-State switching, set UCLK min = max */
439 if (!clk_mgr_base->clks.p_state_change_support)
440 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
441 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz);
442 }
443
444 /* Always update saved value, even if new value not set due to P-State switching unsupported. Also check safe_to_lower for FCLK */
445 if (safe_to_lower && (clk_mgr_base->clks.fclk_p_state_change_support != clk_mgr_base->clks.fclk_prev_p_state_change_support)) {
446 update_fclk = true;
447 }
448
449 if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 && !clk_mgr_base->clks.fclk_p_state_change_support && update_fclk) {
450 /* Handle code for sending a message to PMFW that FCLK P-state change is not supported */
451 dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_NOTSUPPORTED);
452 }
453
454 /* Always update saved value, even if new value not set due to P-State switching unsupported */
455 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
456 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
457 update_uclk = true;
458 }
459
460 /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
461 if (clk_mgr_base->clks.p_state_change_support &&
462 (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support))
463 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
464
465 if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
466 clk_mgr_base->clks.num_ways > new_clocks->num_ways) {
467 clk_mgr_base->clks.num_ways = new_clocks->num_ways;
468 dcn32_smu_send_cab_for_uclk_message(clk_mgr, clk_mgr_base->clks.num_ways);
469 }
470 }
471
472 dcn32_update_dppclk_dispclk_freq(clk_mgr, new_clocks);
473 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
474 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
475 dpp_clock_lowered = true;
476
477 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
478
479 if (clk_mgr->smu_present && !dpp_clock_lowered)
480 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
481
482 update_dppclk = true;
483 }
484
485 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
486 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
487
488 update_dispclk = true;
489 }
490
491 if (!new_clocks->dtbclk_en) {
492 new_clocks->ref_dtbclk_khz = clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz * 1000;
493 }
494
495 /* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
496 if (!dc->debug.disable_dtb_ref_clk_switch &&
497 should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {
498 /* DCCG requires KHz precision for DTBCLK */
499 clk_mgr_base->clks.ref_dtbclk_khz =
500 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz));
501 }
502
503 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
504 if (dpp_clock_lowered) {
505 /* if clock is being lowered, increase DTO before lowering refclk */
506 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
507 dcn32_update_clocks_update_dentist(clk_mgr, context, old_dispclk_khz);
508 if (clk_mgr->smu_present)
509 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
510 } else {
511 /* if clock is being raised, increase refclk before lowering DTO */
512 if (update_dppclk || update_dispclk)
513 dcn32_update_clocks_update_dentist(clk_mgr, context, old_dispclk_khz);
514 /* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures
515 * that we do not lower dto when it is not safe to lower. We do not need to
516 * compare the current and new dppclk before calling this function.
517 */
518 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
519 }
520 }
521
522 if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
523 /*update dmcu for wait_loop count*/
524 dmcu->funcs->set_psr_wait_loop(dmcu,
525 clk_mgr_base->clks.dispclk_khz / 1000 / 7);
526 }
527
dcn32_get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)528 static uint32_t dcn32_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
529 {
530 struct fixed31_32 pll_req;
531 uint32_t pll_req_reg = 0;
532
533 /* get FbMult value */
534 if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev))
535 pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);
536 else
537 pll_req_reg = REG_READ(CLK1_CLK_PLL_REQ);
538
539 /* set up a fixed-point number
540 * this works because the int part is on the right edge of the register
541 * and the frac part is on the left edge
542 */
543 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
544 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
545
546 /* multiply by REFCLK period */
547 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
548
549 return dc_fixpt_floor(pll_req);
550 }
551
dcn32_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info)552 static void dcn32_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
553 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
554 {
555 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
556 uint32_t dprefclk_did = 0;
557 uint32_t dcfclk_did = 0;
558 uint32_t dtbclk_did = 0;
559 uint32_t dispclk_did = 0;
560 uint32_t dppclk_did = 0;
561 uint32_t target_div = 0;
562
563 if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {
564 /* DFS Slice 0 is used for DISPCLK */
565 dispclk_did = REG_READ(CLK0_CLK0_DFS_CNTL);
566 /* DFS Slice 1 is used for DPPCLK */
567 dppclk_did = REG_READ(CLK0_CLK1_DFS_CNTL);
568 /* DFS Slice 2 is used for DPREFCLK */
569 dprefclk_did = REG_READ(CLK0_CLK2_DFS_CNTL);
570 /* DFS Slice 3 is used for DCFCLK */
571 dcfclk_did = REG_READ(CLK0_CLK3_DFS_CNTL);
572 /* DFS Slice 4 is used for DTBCLK */
573 dtbclk_did = REG_READ(CLK0_CLK4_DFS_CNTL);
574 } else {
575 /* DFS Slice 0 is used for DISPCLK */
576 dispclk_did = REG_READ(CLK1_CLK0_DFS_CNTL);
577 /* DFS Slice 1 is used for DPPCLK */
578 dppclk_did = REG_READ(CLK1_CLK1_DFS_CNTL);
579 /* DFS Slice 2 is used for DPREFCLK */
580 dprefclk_did = REG_READ(CLK1_CLK2_DFS_CNTL);
581 /* DFS Slice 3 is used for DCFCLK */
582 dcfclk_did = REG_READ(CLK1_CLK3_DFS_CNTL);
583 /* DFS Slice 4 is used for DTBCLK */
584 dtbclk_did = REG_READ(CLK1_CLK4_DFS_CNTL);
585 }
586
587 /* Convert DISPCLK DFS Slice DID to divider*/
588 target_div = dentist_get_divider_from_did(dispclk_did);
589 //Get dispclk in khz
590 regs_and_bypass->dispclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
591 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
592
593 /* Convert DISPCLK DFS Slice DID to divider*/
594 target_div = dentist_get_divider_from_did(dppclk_did);
595 //Get dppclk in khz
596 regs_and_bypass->dppclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
597 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
598
599 /* Convert DPREFCLK DFS Slice DID to divider*/
600 target_div = dentist_get_divider_from_did(dprefclk_did);
601 //Get dprefclk in khz
602 regs_and_bypass->dprefclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
603 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
604
605 /* Convert DCFCLK DFS Slice DID to divider*/
606 target_div = dentist_get_divider_from_did(dcfclk_did);
607 //Get dcfclk in khz
608 regs_and_bypass->dcfclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
609 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
610
611 /* Convert DTBCLK DFS Slice DID to divider*/
612 target_div = dentist_get_divider_from_did(dtbclk_did);
613 //Get dtbclk in khz
614 regs_and_bypass->dtbclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
615 * clk_mgr->base.dentist_vco_freq_khz) / target_div;
616 }
617
dcn32_clock_read_ss_info(struct clk_mgr_internal * clk_mgr)618 static void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)
619 {
620 struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
621 int ss_info_num = bp->funcs->get_ss_entry_number(
622 bp, AS_SIGNAL_TYPE_GPU_PLL);
623
624 if (ss_info_num) {
625 struct spread_spectrum_info info = { { 0 } };
626 enum bp_result result = bp->funcs->get_spread_spectrum_info(
627 bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info);
628
629 /* SSInfo.spreadSpectrumPercentage !=0 would be sign
630 * that SS is enabled
631 */
632 if (result == BP_RESULT_OK &&
633 info.spread_spectrum_percentage != 0) {
634 clk_mgr->ss_on_dprefclk = true;
635 clk_mgr->dprefclk_ss_divider = info.spread_percentage_divider;
636
637 if (info.type.CENTER_MODE == 0) {
638 /* Currently for DP Reference clock we
639 * need only SS percentage for
640 * downspread
641 */
642 clk_mgr->dprefclk_ss_percentage =
643 info.spread_spectrum_percentage;
644 }
645 }
646 }
647 }
dcn32_notify_wm_ranges(struct clk_mgr * clk_mgr_base)648 static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
649 {
650 unsigned int i;
651 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
652 WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
653
654 if (!clk_mgr->smu_present)
655 return;
656
657 if (!table)
658 return;
659
660 memset(table, 0, sizeof(*table));
661
662 /* collect valid ranges, place in pmfw table */
663 for (i = 0; i < WM_SET_COUNT; i++)
664 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {
665 table->Watermarks.WatermarkRow[i].WmSetting = i;
666 table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
667 }
668 dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
669 dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);
670 dcn32_smu_transfer_wm_table_dram_2_smu(clk_mgr);
671 }
672
673 /* Set min memclk to minimum, either constrained by the current mode or DPM0 */
dcn32_set_hard_min_memclk(struct clk_mgr * clk_mgr_base,bool current_mode)674 static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
675 {
676 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
677
678 if (!clk_mgr->smu_present)
679 return;
680
681 if (current_mode) {
682 if (clk_mgr_base->clks.p_state_change_support)
683 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
684 khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
685 else
686 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
687 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz);
688 } else {
689 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
690 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
691 }
692 }
693
694 /* Set max memclk to highest DPM value */
dcn32_set_hard_max_memclk(struct clk_mgr * clk_mgr_base)695 static void dcn32_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)
696 {
697 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
698
699 if (!clk_mgr->smu_present)
700 return;
701
702 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
703 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz);
704 }
705
706 /* Get current memclk states, update bounding box */
dcn32_get_memclk_states_from_smu(struct clk_mgr * clk_mgr_base)707 static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
708 {
709 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
710 struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk;
711 unsigned int num_levels;
712
713 if (!clk_mgr->smu_present)
714 return;
715
716 /* Refresh memclk and fclk states */
717 dcn32_init_single_clock(clk_mgr, PPCLK_UCLK,
718 &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
719 &num_entries_per_clk->num_memclk_levels);
720
721 /* memclk must have at least one level */
722 num_entries_per_clk->num_memclk_levels = num_entries_per_clk->num_memclk_levels ? num_entries_per_clk->num_memclk_levels : 1;
723
724 dcn32_init_single_clock(clk_mgr, PPCLK_FCLK,
725 &clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz,
726 &num_entries_per_clk->num_fclk_levels);
727
728 if (num_entries_per_clk->num_memclk_levels >= num_entries_per_clk->num_fclk_levels) {
729 num_levels = num_entries_per_clk->num_memclk_levels;
730 } else {
731 num_levels = num_entries_per_clk->num_fclk_levels;
732 }
733
734 clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
735
736 if (clk_mgr->dpm_present && !num_levels)
737 clk_mgr->dpm_present = false;
738
739 if (!clk_mgr->dpm_present)
740 dcn32_patch_dpm_table(clk_mgr_base->bw_params);
741
742 DC_FP_START();
743 /* Refresh bounding box */
744 clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
745 clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
746 DC_FP_END();
747 }
748
dcn32_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)749 static bool dcn32_are_clock_states_equal(struct dc_clocks *a,
750 struct dc_clocks *b)
751 {
752 if (a->dispclk_khz != b->dispclk_khz)
753 return false;
754 else if (a->dppclk_khz != b->dppclk_khz)
755 return false;
756 else if (a->dcfclk_khz != b->dcfclk_khz)
757 return false;
758 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
759 return false;
760 else if (a->dramclk_khz != b->dramclk_khz)
761 return false;
762 else if (a->p_state_change_support != b->p_state_change_support)
763 return false;
764 else if (a->fclk_p_state_change_support != b->fclk_p_state_change_support)
765 return false;
766
767 return true;
768 }
769
dcn32_enable_pme_wa(struct clk_mgr * clk_mgr_base)770 static void dcn32_enable_pme_wa(struct clk_mgr *clk_mgr_base)
771 {
772 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
773
774 if (!clk_mgr->smu_present)
775 return;
776
777 dcn32_smu_set_pme_workaround(clk_mgr);
778 }
779
dcn32_is_smu_present(struct clk_mgr * clk_mgr_base)780 static bool dcn32_is_smu_present(struct clk_mgr *clk_mgr_base)
781 {
782 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
783 return clk_mgr->smu_present;
784 }
785
786
787 static struct clk_mgr_funcs dcn32_funcs = {
788 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
789 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
790 .update_clocks = dcn32_update_clocks,
791 .dump_clk_registers = dcn32_dump_clk_registers,
792 .init_clocks = dcn32_init_clocks,
793 .notify_wm_ranges = dcn32_notify_wm_ranges,
794 .set_hard_min_memclk = dcn32_set_hard_min_memclk,
795 .set_hard_max_memclk = dcn32_set_hard_max_memclk,
796 .get_memclk_states_from_smu = dcn32_get_memclk_states_from_smu,
797 .are_clock_states_equal = dcn32_are_clock_states_equal,
798 .enable_pme_wa = dcn32_enable_pme_wa,
799 .is_smu_present = dcn32_is_smu_present,
800 };
801
dcn32_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_internal * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)802 void dcn32_clk_mgr_construct(
803 struct dc_context *ctx,
804 struct clk_mgr_internal *clk_mgr,
805 struct pp_smu_funcs *pp_smu,
806 struct dccg *dccg)
807 {
808 clk_mgr->base.ctx = ctx;
809 clk_mgr->base.funcs = &dcn32_funcs;
810 if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {
811 clk_mgr->regs = &clk_mgr_regs_dcn321;
812 clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn321;
813 clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn321;
814 } else {
815 clk_mgr->regs = &clk_mgr_regs_dcn32;
816 clk_mgr->clk_mgr_shift = &clk_mgr_shift_dcn32;
817 clk_mgr->clk_mgr_mask = &clk_mgr_mask_dcn32;
818 }
819
820 clk_mgr->dccg = dccg;
821 clk_mgr->dfs_bypass_disp_clk = 0;
822
823 clk_mgr->dprefclk_ss_percentage = 0;
824 clk_mgr->dprefclk_ss_divider = 1000;
825 clk_mgr->ss_on_dprefclk = false;
826 clk_mgr->dfs_ref_freq_khz = 100000;
827
828 /* Changed from DCN3.2_clock_frequency doc to match
829 * dcn32_dump_clk_registers from 4 * dentist_vco_freq_khz /
830 * dprefclk DID divider
831 */
832 clk_mgr->base.dprefclk_khz = 716666;
833 if (ctx->dc->debug.disable_dtb_ref_clk_switch) {
834 //initialize DTB ref clock value if DPM disabled
835 if (ctx->dce_version == DCN_VERSION_3_21)
836 clk_mgr->base.clks.ref_dtbclk_khz = 477800;
837 else
838 clk_mgr->base.clks.ref_dtbclk_khz = 268750;
839 }
840
841 /* integer part is now VCO frequency in kHz */
842 clk_mgr->base.dentist_vco_freq_khz = dcn32_get_vco_frequency_from_reg(clk_mgr);
843
844 /* in case we don't get a value from the register, use default */
845 if (clk_mgr->base.dentist_vco_freq_khz == 0)
846 clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per HW docs */
847
848 if (ctx->dc->debug.disable_dtb_ref_clk_switch &&
849 clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) {
850 clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk;
851 }
852
853 if (clk_mgr->base.boot_snapshot.dprefclk != 0) {
854 clk_mgr->base.dprefclk_khz = clk_mgr->base.boot_snapshot.dprefclk;
855 }
856 dcn32_clock_read_ss_info(clk_mgr);
857
858 clk_mgr->dfs_bypass_enabled = false;
859
860 clk_mgr->smu_present = false;
861
862 clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);
863
864 /* need physical address of table to give to PMFW */
865 clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,
866 DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),
867 &clk_mgr->wm_range_table_addr);
868 }
869
dcn32_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr)870 void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
871 {
872 kfree(clk_mgr->base.bw_params);
873
874 if (clk_mgr->wm_range_table)
875 dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,
876 clk_mgr->wm_range_table);
877 }
878
879