1 #ifndef __ASM_IO_APIC_H
2 #define __ASM_IO_APIC_H
3
4 #include <asm/types.h>
5 #include <asm/mpspec.h>
6 #include <asm/apicdef.h>
7 #include <asm/fixmap.h>
8 #include <xen/iommu.h>
9
10 /*
11 * Intel IO-APIC support for SMP and UP systems.
12 *
13 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
14 */
15
16 #define IO_APIC_BASE(idx) \
17 ((volatile int *)(__fix_to_virt(FIX_IO_APIC_BASE_0 + idx) \
18 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK)))
19
20 #define IO_APIC_ID(idx) (mp_ioapics[idx].mpc_apicid)
21
22 /* I/O Unit Redirection Table */
23 #define IO_APIC_REDIR_VECTOR_MASK 0x000FF
24 #define IO_APIC_REDIR_DEST_LOGICAL 0x00800
25 #define IO_APIC_REDIR_DEST_PHYSICAL 0x00000
26 #define IO_APIC_REDIR_SEND_PENDING (1 << 12)
27 #define IO_APIC_REDIR_REMOTE_IRR (1 << 14)
28 #define IO_APIC_REDIR_LEVEL_TRIGGER (1 << 15)
29 #define IO_APIC_REDIR_MASKED (1 << 16)
30
31 /*
32 * The structure of the IO-APIC:
33 */
34 union IO_APIC_reg_00 {
35 u32 raw;
36 struct __packed {
37 u32 __reserved_2 : 14,
38 LTS : 1,
39 delivery_type : 1,
40 __reserved_1 : 8,
41 ID : 8;
42 } bits;
43 };
44
45 union IO_APIC_reg_01 {
46 u32 raw;
47 struct __packed {
48 u32 version : 8,
49 __reserved_2 : 7,
50 PRQ : 1,
51 entries : 8,
52 __reserved_1 : 8;
53 } bits;
54 };
55
56 union IO_APIC_reg_02 {
57 u32 raw;
58 struct __packed {
59 u32 __reserved_2 : 24,
60 arbitration : 4,
61 __reserved_1 : 4;
62 } bits;
63 };
64
65 union IO_APIC_reg_03 {
66 u32 raw;
67 struct __packed {
68 u32 boot_DT : 1,
69 __reserved_1 : 31;
70 } bits;
71 };
72
73 /*
74 * # of IO-APICs and # of IRQ routing registers
75 */
76 extern int nr_ioapics;
77 extern int nr_ioapic_entries[MAX_IO_APICS];
78
79 enum ioapic_irq_destination_types {
80 dest_Fixed = 0,
81 dest_LowestPrio = 1,
82 dest_SMI = 2,
83 dest__reserved_1 = 3,
84 dest_NMI = 4,
85 dest_INIT = 5,
86 dest__reserved_2 = 6,
87 dest_ExtINT = 7
88 };
89
90 struct __packed IO_APIC_route_entry {
91 __u32 vector : 8,
92 delivery_mode : 3, /* 000: FIXED
93 * 001: lowest prio
94 * 111: ExtINT
95 */
96 dest_mode : 1, /* 0: physical, 1: logical */
97 delivery_status : 1,
98 polarity : 1,
99 irr : 1,
100 trigger : 1, /* 0: edge, 1: level */
101 mask : 1, /* 0: enabled, 1: disabled */
102 __reserved_2 : 15;
103
104 union { struct { __u32
105 __reserved_1 : 24,
106 physical_dest : 4,
107 __reserved_2 : 4;
108 } physical;
109
110 struct { __u32
111 __reserved_1 : 24,
112 logical_dest : 8;
113 } logical;
114
115 /* used when Interrupt Remapping with EIM is enabled */
116 __u32 dest32;
117 } dest;
118
119 };
120
121 /*
122 * MP-BIOS irq configuration table structures:
123 */
124
125 /* I/O APIC entries */
126 extern struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
127
128 /* Base GSI for this IO APIC */
129 unsigned int io_apic_gsi_base(unsigned int apic);
130
131 /* Only need to remap ioapic RTE (reg: 10~3Fh) */
132 #define ioapic_reg_remapped(reg) (iommu_intremap && ((reg) >= 0x10))
133
__io_apic_read(unsigned int apic,unsigned int reg)134 static inline unsigned int __io_apic_read(unsigned int apic, unsigned int reg)
135 {
136 *IO_APIC_BASE(apic) = reg;
137 return *(IO_APIC_BASE(apic)+4);
138 }
139
io_apic_read(unsigned int apic,unsigned int reg)140 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
141 {
142 if (ioapic_reg_remapped(reg))
143 return iommu_read_apic_from_ire(apic, reg);
144 return __io_apic_read(apic, reg);
145 }
146
__io_apic_write(unsigned int apic,unsigned int reg,unsigned int value)147 static inline void __io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
148 {
149 *IO_APIC_BASE(apic) = reg;
150 *(IO_APIC_BASE(apic)+4) = value;
151 }
152
io_apic_write(unsigned int apic,unsigned int reg,unsigned int value)153 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
154 {
155 if (ioapic_reg_remapped(reg))
156 return iommu_update_ire_from_apic(apic, reg, value);
157 __io_apic_write(apic, reg, value);
158 }
159
160 /*
161 * Re-write a value: to be used for read-modify-write
162 * cycles where the read already set up the index register.
163 */
io_apic_modify(unsigned int apic,unsigned int reg,unsigned int value)164 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
165 {
166 if (ioapic_reg_remapped(reg))
167 return iommu_update_ire_from_apic(apic, reg, value);
168 *(IO_APIC_BASE(apic)+4) = value;
169 }
170
171 /* 1 if "noapic" boot option passed */
172 extern bool skip_ioapic_setup;
173 extern bool ioapic_ack_new;
174 extern bool ioapic_ack_forced;
175
176 extern int io_apic_get_unique_id (int ioapic, int apic_id);
177 extern int io_apic_get_version (int ioapic);
178 extern int io_apic_get_redir_entries (int ioapic);
179 extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low);
180
181 extern void init_ioapic_mappings(void);
182
183 extern void ioapic_suspend(void);
184 extern void ioapic_resume(void);
185
186 extern void dump_ioapic_irq_info(void);
187
188 extern struct IO_APIC_route_entry __ioapic_read_entry(
189 unsigned int apic, unsigned int pin, bool raw);
190 void __ioapic_write_entry(
191 unsigned int apic, unsigned int pin, bool raw,
192 struct IO_APIC_route_entry);
193
194 extern struct IO_APIC_route_entry **alloc_ioapic_entries(void);
195 extern void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries);
196 extern int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
197 extern void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
198 extern int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
199
200 unsigned highest_gsi(void);
201
202 int ioapic_guest_read( unsigned long physbase, unsigned int reg, u32 *pval);
203 int ioapic_guest_write(unsigned long physbase, unsigned int reg, u32 pval);
204
205 #endif
206