1 /*
2  * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef _HARDWARE_STRUCTS_DMA_H
8 #define _HARDWARE_STRUCTS_DMA_H
9 
10 #include "hardware/address_mapped.h"
11 #include "hardware/platform_defs.h"
12 #include "hardware/regs/dma.h"
13 
14 typedef struct {
15     io_rw_32 read_addr;
16     io_rw_32 write_addr;
17     io_rw_32 transfer_count;
18     io_rw_32 ctrl_trig;
19     io_rw_32 al1_ctrl;
20     io_rw_32 al1_read_addr;
21     io_rw_32 al1_write_addr;
22     io_rw_32 al1_transfer_count_trig;
23     io_rw_32 al2_ctrl;
24     io_rw_32 al2_transfer_count;
25     io_rw_32 al2_read_addr;
26     io_rw_32 al2_write_addr_trig;
27     io_rw_32 al3_ctrl;
28     io_rw_32 al3_write_addr;
29     io_rw_32 al3_transfer_count;
30     io_rw_32 al3_read_addr_trig;
31 }  dma_channel_hw_t;
32 
33 typedef struct {
34     dma_channel_hw_t ch[NUM_DMA_CHANNELS];
35     uint32_t _pad0[16 * (16 - NUM_DMA_CHANNELS)];
36     io_ro_32 intr;
37     io_rw_32 inte0;
38     io_rw_32 intf0;
39     io_rw_32 ints0;
40     uint32_t _pad1[1];
41     io_rw_32 inte1;
42     io_rw_32 intf1;
43     io_rw_32 ints1;
44     io_rw_32 timer[4];
45     io_wo_32 multi_channel_trigger;
46     io_rw_32 sniff_ctrl;
47     io_rw_32 sniff_data;
48     uint32_t _pad2[1];
49     io_ro_32 fifo_levels;
50     io_wo_32 abort;
51 } dma_hw_t;
52 
53 typedef struct {
54     struct dma_debug_hw_channel {
55         io_ro_32 ctrdeq;
56         io_ro_32 tcr;
57         uint32_t pad[14];
58     } ch[NUM_DMA_CHANNELS];
59 } dma_debug_hw_t;
60 
61 #define dma_hw ((dma_hw_t *const)DMA_BASE)
62 #define dma_debug_hw ((dma_debug_hw_t *const)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET))
63 
64 #endif
65