1 /*
2  * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef __DAL_LINK_SERVICE_TYPES_H__
27 #define __DAL_LINK_SERVICE_TYPES_H__
28 
29 #include "grph_object_id.h"
30 #include "dal_types.h"
31 #include "irq_types.h"
32 
33 /*struct mst_mgr_callback_object;*/
34 struct ddc;
35 struct irq_manager;
36 
37 enum {
38 	MAX_CONTROLLER_NUM = 6
39 };
40 
41 enum dp_power_state {
42 	DP_POWER_STATE_D0 = 1,
43 	DP_POWER_STATE_D3
44 };
45 
46 enum edp_revision {
47 	/* eDP version 1.1 or lower */
48 	EDP_REVISION_11 = 0x00,
49 	/* eDP version 1.2 */
50 	EDP_REVISION_12 = 0x01,
51 	/* eDP version 1.3 */
52 	EDP_REVISION_13 = 0x02
53 };
54 
55 enum {
56 	LINK_RATE_REF_FREQ_IN_KHZ = 27000, /*27MHz*/
57 	BITS_PER_DP_BYTE = 10,
58 	DATA_EFFICIENCY_8b_10b_x10000 = 8000, /* 80% data efficiency */
59 	DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100 = 97, /* 97% data efficiency when FEC is enabled */
60 	DATA_EFFICIENCY_128b_132b_x10000 = 9646, /* 96.71% data efficiency x 99.75% downspread factor */
61 };
62 
63 enum link_training_result {
64 	LINK_TRAINING_SUCCESS,
65 	LINK_TRAINING_CR_FAIL_LANE0,
66 	LINK_TRAINING_CR_FAIL_LANE1,
67 	LINK_TRAINING_CR_FAIL_LANE23,
68 	/* CR DONE bit is cleared during EQ step */
69 	LINK_TRAINING_EQ_FAIL_CR,
70 	/* CR DONE bit is cleared but LANE0_CR_DONE is set during EQ step */
71 	LINK_TRAINING_EQ_FAIL_CR_PARTIAL,
72 	/* other failure during EQ step */
73 	LINK_TRAINING_EQ_FAIL_EQ,
74 	LINK_TRAINING_LQA_FAIL,
75 	/* one of the CR,EQ or symbol lock is dropped */
76 	LINK_TRAINING_LINK_LOSS,
77 	/* Abort link training (because sink unplugged) */
78 	LINK_TRAINING_ABORT,
79 	DP_128b_132b_LT_FAILED,
80 	DP_128b_132b_MAX_LOOP_COUNT_REACHED,
81 	DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT,
82 	DP_128b_132b_CDS_DONE_TIMEOUT,
83 };
84 
85 enum lttpr_mode {
86 	LTTPR_MODE_UNKNOWN,
87 	LTTPR_MODE_NON_LTTPR,
88 	LTTPR_MODE_TRANSPARENT,
89 	LTTPR_MODE_NON_TRANSPARENT,
90 };
91 
92 struct link_training_settings {
93 	struct dc_link_settings link_settings;
94 
95 	/* TODO: turn lane settings below into mandatory fields
96 	 * as initial lane configuration
97 	 */
98 	enum dc_voltage_swing *voltage_swing;
99 	enum dc_pre_emphasis *pre_emphasis;
100 	enum dc_post_cursor2 *post_cursor2;
101 	bool should_set_fec_ready;
102 	/* TODO - factor lane_settings out because it changes during LT */
103 	union dc_dp_ffe_preset *ffe_preset;
104 
105 	uint16_t cr_pattern_time;
106 	uint16_t eq_pattern_time;
107 	uint16_t cds_pattern_time;
108 	enum dc_dp_training_pattern pattern_for_cr;
109 	enum dc_dp_training_pattern pattern_for_eq;
110 	enum dc_dp_training_pattern pattern_for_cds;
111 
112 	uint32_t eq_wait_time_limit;
113 	uint8_t eq_loop_count_limit;
114 	uint32_t cds_wait_time_limit;
115 
116 	bool enhanced_framing;
117 	enum lttpr_mode lttpr_mode;
118 
119 	/* disallow different lanes to have different lane settings */
120 	bool disallow_per_lane_settings;
121 	/* dpcd lane settings will always use the same hw lane settings
122 	 * even if it doesn't match requested lane adjust */
123 	bool always_match_dpcd_with_hw_lane_settings;
124 
125 	/*****************************************************************
126 	* training states - parameters that can change in link training
127 	*****************************************************************/
128 	/* TODO: Move hw_lane_settings and dpcd_lane_settings
129 	 * along with lane adjust, lane align, offset and all
130 	 * other training states into a new structure called
131 	 * training states, so link_training_settings becomes
132 	 * a constant input pre-decided prior to link training.
133 	 *
134 	 * The goal is to strictly decouple link training settings
135 	 * decision making process from link training states to
136 	 * prevent it from messy code practice of changing training
137 	 * decision on the fly.
138 	 */
139 	struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX];
140 	union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX];
141 };
142 
143 /*TODO: Move this enum test harness*/
144 /* Test patterns*/
145 enum dp_test_pattern {
146 	/* Input data is pass through Scrambler
147 	 * and 8b10b Encoder straight to output*/
148 	DP_TEST_PATTERN_VIDEO_MODE = 0,
149 
150 	/* phy test patterns*/
151 	DP_TEST_PATTERN_PHY_PATTERN_BEGIN,
152 	DP_TEST_PATTERN_D102 = DP_TEST_PATTERN_PHY_PATTERN_BEGIN,
153 	DP_TEST_PATTERN_SYMBOL_ERROR,
154 	DP_TEST_PATTERN_PRBS7,
155 	DP_TEST_PATTERN_80BIT_CUSTOM,
156 	DP_TEST_PATTERN_CP2520_1,
157 	DP_TEST_PATTERN_CP2520_2,
158 	DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE = DP_TEST_PATTERN_CP2520_2,
159 	DP_TEST_PATTERN_CP2520_3,
160 	DP_TEST_PATTERN_128b_132b_TPS1,
161 	DP_TEST_PATTERN_128b_132b_TPS2,
162 	DP_TEST_PATTERN_PRBS9,
163 	DP_TEST_PATTERN_PRBS11,
164 	DP_TEST_PATTERN_PRBS15,
165 	DP_TEST_PATTERN_PRBS23,
166 	DP_TEST_PATTERN_PRBS31,
167 	DP_TEST_PATTERN_264BIT_CUSTOM,
168 	DP_TEST_PATTERN_SQUARE_BEGIN,
169 	DP_TEST_PATTERN_SQUARE = DP_TEST_PATTERN_SQUARE_BEGIN,
170 	DP_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED,
171 	DP_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED,
172 	DP_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED,
173 	DP_TEST_PATTERN_SQUARE_END = DP_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED,
174 
175 	/* Link Training Patterns */
176 	DP_TEST_PATTERN_TRAINING_PATTERN1,
177 	DP_TEST_PATTERN_TRAINING_PATTERN2,
178 	DP_TEST_PATTERN_TRAINING_PATTERN3,
179 	DP_TEST_PATTERN_TRAINING_PATTERN4,
180 	DP_TEST_PATTERN_128b_132b_TPS1_TRAINING_MODE,
181 	DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE,
182 	DP_TEST_PATTERN_PHY_PATTERN_END = DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE,
183 
184 	/* link test patterns*/
185 	DP_TEST_PATTERN_COLOR_SQUARES,
186 	DP_TEST_PATTERN_COLOR_SQUARES_CEA,
187 	DP_TEST_PATTERN_VERTICAL_BARS,
188 	DP_TEST_PATTERN_HORIZONTAL_BARS,
189 	DP_TEST_PATTERN_COLOR_RAMP,
190 
191 	/* audio test patterns*/
192 	DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED,
193 	DP_TEST_PATTERN_AUDIO_SAWTOOTH,
194 
195 	DP_TEST_PATTERN_UNSUPPORTED
196 };
197 
198 enum dp_test_pattern_color_space {
199 	DP_TEST_PATTERN_COLOR_SPACE_RGB,
200 	DP_TEST_PATTERN_COLOR_SPACE_YCBCR601,
201 	DP_TEST_PATTERN_COLOR_SPACE_YCBCR709,
202 	DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED
203 };
204 
205 enum dp_panel_mode {
206 	/* not required */
207 	DP_PANEL_MODE_DEFAULT,
208 	/* standard mode for eDP */
209 	DP_PANEL_MODE_EDP,
210 	/* external chips specific settings */
211 	DP_PANEL_MODE_SPECIAL
212 };
213 
214 enum dpcd_source_sequence {
215 	DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG = 1, /*done in apply_single_controller_ctx_to_hw */
216 	DPCD_SOURCE_SEQ_AFTER_DP_STREAM_ATTR,         /*done in core_link_enable_stream */
217 	DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME,      /*done in core_link_enable_stream/dcn20_enable_stream */
218 	DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_BE,      /*done in perform_link_training_with_retries/dcn20_enable_stream */
219 	DPCD_SOURCE_SEQ_AFTER_ENABLE_LINK_PHY,        /*done in dp_enable_link_phy */
220 	DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN,     /*done in dp_set_hw_test_pattern */
221 	DPCD_SOURCE_SEQ_AFTER_ENABLE_AUDIO_STREAM,    /*done in dce110_enable_audio_stream */
222 	DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM,   /*done in enc1_stream_encoder_dp_unblank */
223 	DPCD_SOURCE_SEQ_AFTER_DISABLE_DP_VID_STREAM,  /*done in enc1_stream_encoder_dp_blank */
224 	DPCD_SOURCE_SEQ_AFTER_FIFO_STEER_RESET,       /*done in enc1_stream_encoder_dp_blank */
225 	DPCD_SOURCE_SEQ_AFTER_DISABLE_AUDIO_STREAM,   /*done in dce110_disable_audio_stream */
226 	DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY,       /*done in dp_disable_link_phy */
227 	DPCD_SOURCE_SEQ_AFTER_DISCONNECT_DIG_FE_BE,   /*done in dce110_disable_stream */
228 };
229 
230 /* DPCD_ADDR_TRAINING_LANEx_SET registers value */
231 union dpcd_training_lane_set {
232 	struct {
233 #if defined(LITTLEENDIAN_CPU)
234 		uint8_t VOLTAGE_SWING_SET:2;
235 		uint8_t MAX_SWING_REACHED:1;
236 		uint8_t PRE_EMPHASIS_SET:2;
237 		uint8_t MAX_PRE_EMPHASIS_REACHED:1;
238 		/* following is reserved in DP 1.1 */
239 		uint8_t POST_CURSOR2_SET:2;
240 #elif defined(BIGENDIAN_CPU)
241 		uint8_t POST_CURSOR2_SET:2;
242 		uint8_t MAX_PRE_EMPHASIS_REACHED:1;
243 		uint8_t PRE_EMPHASIS_SET:2;
244 		uint8_t MAX_SWING_REACHED:1;
245 		uint8_t VOLTAGE_SWING_SET:2;
246 #else
247 	#error ARCH not defined!
248 #endif
249 	} bits;
250 
251 	uint8_t raw;
252 };
253 
254 
255 /* AMD's copy of various payload data for MST. We have two copies of the payload table (one in DRM,
256  * one in DC) since DRM's MST helpers can't be accessed here. This stream allocation table should
257  * _ONLY_ be filled out from DM and then passed to DC, do NOT use these for _any_ kind of atomic
258  * state calculations in DM, or you will break something.
259  */
260 
261 struct drm_dp_mst_port;
262 
263 /* DP MST stream allocation (payload bandwidth number) */
264 struct dc_dp_mst_stream_allocation {
265 	uint8_t vcp_id;
266 	/* number of slots required for the DP stream in
267 	 * transport packet */
268 	uint8_t slot_count;
269 };
270 
271 /* DP MST stream allocation table */
272 struct dc_dp_mst_stream_allocation_table {
273 	/* number of DP video streams */
274 	int stream_count;
275 	/* array of stream allocations */
276 	struct dc_dp_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
277 };
278 
279 #endif /*__DAL_LINK_SERVICE_TYPES_H__*/
280