1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 */ 4 5 #ifndef _DPU_HW_MDSS_H 6 #define _DPU_HW_MDSS_H 7 8 #include <linux/kernel.h> 9 #include <linux/err.h> 10 11 #include "msm_drv.h" 12 13 #define DPU_DBG_NAME "dpu" 14 15 #define DPU_NONE 0 16 17 #ifndef DPU_CSC_MATRIX_COEFF_SIZE 18 #define DPU_CSC_MATRIX_COEFF_SIZE 9 19 #endif 20 21 #ifndef DPU_CSC_CLAMP_SIZE 22 #define DPU_CSC_CLAMP_SIZE 6 23 #endif 24 25 #ifndef DPU_CSC_BIAS_SIZE 26 #define DPU_CSC_BIAS_SIZE 3 27 #endif 28 29 #ifndef DPU_MAX_PLANES 30 #define DPU_MAX_PLANES 4 31 #endif 32 33 #define PIPES_PER_STAGE 2 34 #ifndef DPU_MAX_DE_CURVES 35 #define DPU_MAX_DE_CURVES 3 36 #endif 37 38 enum dpu_format_flags { 39 DPU_FORMAT_FLAG_YUV_BIT, 40 DPU_FORMAT_FLAG_DX_BIT, 41 DPU_FORMAT_FLAG_COMPRESSED_BIT, 42 DPU_FORMAT_FLAG_BIT_MAX, 43 }; 44 45 #define DPU_FORMAT_FLAG_YUV BIT(DPU_FORMAT_FLAG_YUV_BIT) 46 #define DPU_FORMAT_FLAG_DX BIT(DPU_FORMAT_FLAG_DX_BIT) 47 #define DPU_FORMAT_FLAG_COMPRESSED BIT(DPU_FORMAT_FLAG_COMPRESSED_BIT) 48 #define DPU_FORMAT_IS_YUV(X) \ 49 (test_bit(DPU_FORMAT_FLAG_YUV_BIT, (X)->flag)) 50 #define DPU_FORMAT_IS_DX(X) \ 51 (test_bit(DPU_FORMAT_FLAG_DX_BIT, (X)->flag)) 52 #define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == DPU_FETCH_LINEAR) 53 #define DPU_FORMAT_IS_TILE(X) \ 54 (((X)->fetch_mode == DPU_FETCH_UBWC) && \ 55 !test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag)) 56 #define DPU_FORMAT_IS_UBWC(X) \ 57 (((X)->fetch_mode == DPU_FETCH_UBWC) && \ 58 test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag)) 59 60 #define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0) 61 #define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0) 62 #define DPU_BLEND_FG_ALPHA_FG_PIXEL (2 << 0) 63 #define DPU_BLEND_FG_ALPHA_BG_PIXEL (3 << 0) 64 #define DPU_BLEND_FG_INV_ALPHA (1 << 2) 65 #define DPU_BLEND_FG_MOD_ALPHA (1 << 3) 66 #define DPU_BLEND_FG_INV_MOD_ALPHA (1 << 4) 67 #define DPU_BLEND_FG_TRANSP_EN (1 << 5) 68 #define DPU_BLEND_BG_ALPHA_FG_CONST (0 << 8) 69 #define DPU_BLEND_BG_ALPHA_BG_CONST (1 << 8) 70 #define DPU_BLEND_BG_ALPHA_FG_PIXEL (2 << 8) 71 #define DPU_BLEND_BG_ALPHA_BG_PIXEL (3 << 8) 72 #define DPU_BLEND_BG_INV_ALPHA (1 << 10) 73 #define DPU_BLEND_BG_MOD_ALPHA (1 << 11) 74 #define DPU_BLEND_BG_INV_MOD_ALPHA (1 << 12) 75 #define DPU_BLEND_BG_TRANSP_EN (1 << 13) 76 77 #define DPU_VSYNC0_SOURCE_GPIO 0 78 #define DPU_VSYNC1_SOURCE_GPIO 1 79 #define DPU_VSYNC2_SOURCE_GPIO 2 80 #define DPU_VSYNC_SOURCE_INTF_0 3 81 #define DPU_VSYNC_SOURCE_INTF_1 4 82 #define DPU_VSYNC_SOURCE_INTF_2 5 83 #define DPU_VSYNC_SOURCE_INTF_3 6 84 #define DPU_VSYNC_SOURCE_WD_TIMER_4 11 85 #define DPU_VSYNC_SOURCE_WD_TIMER_3 12 86 #define DPU_VSYNC_SOURCE_WD_TIMER_2 13 87 #define DPU_VSYNC_SOURCE_WD_TIMER_1 14 88 #define DPU_VSYNC_SOURCE_WD_TIMER_0 15 89 90 enum dpu_hw_blk_type { 91 DPU_HW_BLK_TOP = 0, 92 DPU_HW_BLK_SSPP, 93 DPU_HW_BLK_LM, 94 DPU_HW_BLK_CTL, 95 DPU_HW_BLK_PINGPONG, 96 DPU_HW_BLK_INTF, 97 DPU_HW_BLK_WB, 98 DPU_HW_BLK_DSPP, 99 DPU_HW_BLK_MERGE_3D, 100 DPU_HW_BLK_DSC, 101 DPU_HW_BLK_MAX, 102 }; 103 104 enum dpu_mdp { 105 MDP_TOP = 0x1, 106 MDP_MAX, 107 }; 108 109 enum dpu_sspp { 110 SSPP_NONE, 111 SSPP_VIG0, 112 SSPP_VIG1, 113 SSPP_VIG2, 114 SSPP_VIG3, 115 SSPP_RGB0, 116 SSPP_RGB1, 117 SSPP_RGB2, 118 SSPP_RGB3, 119 SSPP_DMA0, 120 SSPP_DMA1, 121 SSPP_DMA2, 122 SSPP_DMA3, 123 SSPP_DMA4, 124 SSPP_DMA5, 125 SSPP_CURSOR0, 126 SSPP_CURSOR1, 127 SSPP_MAX 128 }; 129 130 enum dpu_sspp_type { 131 SSPP_TYPE_VIG, 132 SSPP_TYPE_RGB, 133 SSPP_TYPE_DMA, 134 SSPP_TYPE_CURSOR, 135 SSPP_TYPE_MAX 136 }; 137 138 enum dpu_lm { 139 LM_0 = 1, 140 LM_1, 141 LM_2, 142 LM_3, 143 LM_4, 144 LM_5, 145 LM_6, 146 LM_MAX 147 }; 148 149 enum dpu_stage { 150 DPU_STAGE_BASE = 0, 151 DPU_STAGE_0, 152 DPU_STAGE_1, 153 DPU_STAGE_2, 154 DPU_STAGE_3, 155 DPU_STAGE_4, 156 DPU_STAGE_5, 157 DPU_STAGE_6, 158 DPU_STAGE_7, 159 DPU_STAGE_8, 160 DPU_STAGE_9, 161 DPU_STAGE_10, 162 DPU_STAGE_MAX 163 }; 164 enum dpu_dspp { 165 DSPP_0 = 1, 166 DSPP_1, 167 DSPP_2, 168 DSPP_3, 169 DSPP_MAX 170 }; 171 172 enum dpu_ctl { 173 CTL_0 = 1, 174 CTL_1, 175 CTL_2, 176 CTL_3, 177 CTL_4, 178 CTL_5, 179 CTL_MAX 180 }; 181 182 enum dpu_dsc { 183 DSC_NONE = 0, 184 DSC_0, 185 DSC_1, 186 DSC_2, 187 DSC_3, 188 DSC_4, 189 DSC_5, 190 DSC_MAX 191 }; 192 193 enum dpu_pingpong { 194 PINGPONG_0 = 1, 195 PINGPONG_1, 196 PINGPONG_2, 197 PINGPONG_3, 198 PINGPONG_4, 199 PINGPONG_5, 200 PINGPONG_6, 201 PINGPONG_7, 202 PINGPONG_S0, 203 PINGPONG_MAX 204 }; 205 206 enum dpu_merge_3d { 207 MERGE_3D_0 = 1, 208 MERGE_3D_1, 209 MERGE_3D_2, 210 MERGE_3D_3, 211 MERGE_3D_MAX 212 }; 213 214 enum dpu_intf { 215 INTF_0 = 1, 216 INTF_1, 217 INTF_2, 218 INTF_3, 219 INTF_4, 220 INTF_5, 221 INTF_6, 222 INTF_7, 223 INTF_8, 224 INTF_MAX 225 }; 226 227 /* 228 * Historically these values correspond to the values written to the 229 * DISP_INTF_SEL register, which had to programmed manually. On newer MDP 230 * generations this register is NOP, but we keep the values for historical 231 * reasons. 232 */ 233 enum dpu_intf_type { 234 INTF_NONE = 0x0, 235 INTF_DSI = 0x1, 236 INTF_HDMI = 0x3, 237 INTF_LCDC = 0x5, 238 /* old eDP found on 8x74 and 8x84 */ 239 INTF_EDP = 0x9, 240 /* both DP and eDP, handled by the new DP driver */ 241 INTF_DP = 0xa, 242 243 /* virtual interfaces */ 244 INTF_WB = 0x100, 245 }; 246 247 enum dpu_intf_mode { 248 INTF_MODE_NONE = 0, 249 INTF_MODE_CMD, 250 INTF_MODE_VIDEO, 251 INTF_MODE_WB_BLOCK, 252 INTF_MODE_WB_LINE, 253 INTF_MODE_MAX 254 }; 255 256 enum dpu_wb { 257 WB_0 = 1, 258 WB_1, 259 WB_2, 260 WB_3, 261 WB_MAX 262 }; 263 264 enum dpu_cwb { 265 CWB_0 = 0x1, 266 CWB_1, 267 CWB_2, 268 CWB_3, 269 CWB_MAX 270 }; 271 272 enum dpu_wd_timer { 273 WD_TIMER_0 = 0x1, 274 WD_TIMER_1, 275 WD_TIMER_2, 276 WD_TIMER_3, 277 WD_TIMER_4, 278 WD_TIMER_5, 279 WD_TIMER_MAX 280 }; 281 282 enum dpu_vbif { 283 VBIF_RT, 284 VBIF_NRT, 285 VBIF_MAX, 286 }; 287 288 /** 289 * DPU HW,Component order color map 290 */ 291 enum { 292 C0_G_Y = 0, 293 C1_B_Cb = 1, 294 C2_R_Cr = 2, 295 C3_ALPHA = 3 296 }; 297 298 /** 299 * enum dpu_plane_type - defines how the color component pixel packing 300 * @DPU_PLANE_INTERLEAVED : Color components in single plane 301 * @DPU_PLANE_PLANAR : Color component in separate planes 302 * @DPU_PLANE_PSEUDO_PLANAR : Chroma components interleaved in separate plane 303 */ 304 enum dpu_plane_type { 305 DPU_PLANE_INTERLEAVED, 306 DPU_PLANE_PLANAR, 307 DPU_PLANE_PSEUDO_PLANAR, 308 }; 309 310 /** 311 * enum dpu_chroma_samp_type - chroma sub-samplng type 312 * @DPU_CHROMA_RGB : No chroma subsampling 313 * @DPU_CHROMA_H2V1 : Chroma pixels are horizontally subsampled 314 * @DPU_CHROMA_H1V2 : Chroma pixels are vertically subsampled 315 * @DPU_CHROMA_420 : 420 subsampling 316 */ 317 enum dpu_chroma_samp_type { 318 DPU_CHROMA_RGB, 319 DPU_CHROMA_H2V1, 320 DPU_CHROMA_H1V2, 321 DPU_CHROMA_420 322 }; 323 324 /** 325 * dpu_fetch_type - Defines How DPU HW fetches data 326 * @DPU_FETCH_LINEAR : fetch is line by line 327 * @DPU_FETCH_TILE : fetches data in Z order from a tile 328 * @DPU_FETCH_UBWC : fetch and decompress data 329 */ 330 enum dpu_fetch_type { 331 DPU_FETCH_LINEAR, 332 DPU_FETCH_TILE, 333 DPU_FETCH_UBWC 334 }; 335 336 /** 337 * Value of enum chosen to fit the number of bits 338 * expected by the HW programming. 339 */ 340 enum { 341 COLOR_ALPHA_1BIT = 0, 342 COLOR_ALPHA_4BIT = 1, 343 COLOR_4BIT = 0, 344 COLOR_5BIT = 1, /* No 5-bit Alpha */ 345 COLOR_6BIT = 2, /* 6-Bit Alpha also = 2 */ 346 COLOR_8BIT = 3, /* 8-Bit Alpha also = 3 */ 347 }; 348 349 /** 350 * enum dpu_3d_blend_mode 351 * Desribes how the 3d data is blended 352 * @BLEND_3D_NONE : 3d blending not enabled 353 * @BLEND_3D_FRAME_INT : Frame interleaving 354 * @BLEND_3D_H_ROW_INT : Horizontal row interleaving 355 * @BLEND_3D_V_ROW_INT : vertical row interleaving 356 * @BLEND_3D_COL_INT : column interleaving 357 * @BLEND_3D_MAX : 358 */ 359 enum dpu_3d_blend_mode { 360 BLEND_3D_NONE = 0, 361 BLEND_3D_FRAME_INT, 362 BLEND_3D_H_ROW_INT, 363 BLEND_3D_V_ROW_INT, 364 BLEND_3D_COL_INT, 365 BLEND_3D_MAX 366 }; 367 368 /** struct dpu_format - defines the format configuration which 369 * allows DPU HW to correctly fetch and decode the format 370 * @base: base msm_format structure containing fourcc code 371 * @fetch_planes: how the color components are packed in pixel format 372 * @element: element color ordering 373 * @bits: element bit widths 374 * @chroma_sample: chroma sub-samplng type 375 * @unpack_align_msb: unpack aligned, 0 to LSB, 1 to MSB 376 * @unpack_tight: 0 for loose, 1 for tight 377 * @unpack_count: 0 = 1 component, 1 = 2 component 378 * @bpp: bytes per pixel 379 * @alpha_enable: whether the format has an alpha channel 380 * @num_planes: number of planes (including meta data planes) 381 * @fetch_mode: linear, tiled, or ubwc hw fetch behavior 382 * @flag: usage bit flags 383 * @tile_width: format tile width 384 * @tile_height: format tile height 385 */ 386 struct dpu_format { 387 struct msm_format base; 388 enum dpu_plane_type fetch_planes; 389 u8 element[DPU_MAX_PLANES]; 390 u8 bits[DPU_MAX_PLANES]; 391 enum dpu_chroma_samp_type chroma_sample; 392 u8 unpack_align_msb; 393 u8 unpack_tight; 394 u8 unpack_count; 395 u8 bpp; 396 u8 alpha_enable; 397 u8 num_planes; 398 enum dpu_fetch_type fetch_mode; 399 DECLARE_BITMAP(flag, DPU_FORMAT_FLAG_BIT_MAX); 400 u16 tile_width; 401 u16 tile_height; 402 }; 403 #define to_dpu_format(x) container_of(x, struct dpu_format, base) 404 405 /** 406 * struct dpu_hw_fmt_layout - format information of the source pixel data 407 * @format: pixel format parameters 408 * @num_planes: number of planes (including meta data planes) 409 * @width: image width 410 * @height: image height 411 * @total_size: total size in bytes 412 * @plane_addr: address of each plane 413 * @plane_size: length of each plane 414 * @plane_pitch: pitch of each plane 415 */ 416 struct dpu_hw_fmt_layout { 417 const struct dpu_format *format; 418 uint32_t num_planes; 419 uint32_t width; 420 uint32_t height; 421 uint32_t total_size; 422 uint32_t plane_addr[DPU_MAX_PLANES]; 423 uint32_t plane_size[DPU_MAX_PLANES]; 424 uint32_t plane_pitch[DPU_MAX_PLANES]; 425 }; 426 427 struct dpu_csc_cfg { 428 /* matrix coefficients in S15.16 format */ 429 uint32_t csc_mv[DPU_CSC_MATRIX_COEFF_SIZE]; 430 uint32_t csc_pre_bv[DPU_CSC_BIAS_SIZE]; 431 uint32_t csc_post_bv[DPU_CSC_BIAS_SIZE]; 432 uint32_t csc_pre_lv[DPU_CSC_CLAMP_SIZE]; 433 uint32_t csc_post_lv[DPU_CSC_CLAMP_SIZE]; 434 }; 435 436 /** 437 * struct dpu_mdss_color - mdss color description 438 * color 0 : green 439 * color 1 : blue 440 * color 2 : red 441 * color 3 : alpha 442 */ 443 struct dpu_mdss_color { 444 u32 color_0; 445 u32 color_1; 446 u32 color_2; 447 u32 color_3; 448 }; 449 450 /* 451 * Define bit masks for h/w logging. 452 */ 453 #define DPU_DBG_MASK_NONE (1 << 0) 454 #define DPU_DBG_MASK_INTF (1 << 1) 455 #define DPU_DBG_MASK_LM (1 << 2) 456 #define DPU_DBG_MASK_CTL (1 << 3) 457 #define DPU_DBG_MASK_PINGPONG (1 << 4) 458 #define DPU_DBG_MASK_SSPP (1 << 5) 459 #define DPU_DBG_MASK_WB (1 << 6) 460 #define DPU_DBG_MASK_TOP (1 << 7) 461 #define DPU_DBG_MASK_VBIF (1 << 8) 462 #define DPU_DBG_MASK_ROT (1 << 9) 463 #define DPU_DBG_MASK_DSPP (1 << 10) 464 #define DPU_DBG_MASK_DSC (1 << 11) 465 466 #endif /* _DPU_HW_MDSS_H */ 467