1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_DP_TYPES_H 27 #define DC_DP_TYPES_H 28 29 #include "os_types.h" 30 #include "dc_ddc_types.h" 31 32 enum dc_lane_count { 33 LANE_COUNT_UNKNOWN = 0, 34 LANE_COUNT_ONE = 1, 35 LANE_COUNT_TWO = 2, 36 LANE_COUNT_FOUR = 4, 37 LANE_COUNT_EIGHT = 8, 38 LANE_COUNT_DP_MAX = LANE_COUNT_FOUR 39 }; 40 41 /* This is actually a reference clock (27MHz) multiplier 42 * 162MBps bandwidth for 1.62GHz like rate, 43 * 270MBps for 2.70GHz, 44 * 324MBps for 3.24Ghz, 45 * 540MBps for 5.40GHz 46 * 810MBps for 8.10GHz 47 */ 48 enum dc_link_rate { 49 LINK_RATE_UNKNOWN = 0, 50 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane 51 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane 52 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane 53 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane 54 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2)- 3.24 Gbps/Lane 55 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane 56 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2)- 5.40 Gbps/Lane 57 LINK_RATE_HIGH3 = 0x1E, // Rate_8 (HBR3)- 8.10 Gbps/Lane 58 /* Starting from DP2.0 link rate enum directly represents actual 59 * link rate value in unit of 10 mbps 60 */ 61 LINK_RATE_UHBR10 = 1000, // UHBR10 - 10.0 Gbps/Lane 62 LINK_RATE_UHBR13_5 = 1350, // UHBR13.5 - 13.5 Gbps/Lane 63 LINK_RATE_UHBR20 = 2000, // UHBR10 - 20.0 Gbps/Lane 64 }; 65 66 enum dc_link_spread { 67 LINK_SPREAD_DISABLED = 0x00, 68 /* 0.5 % downspread 30 kHz */ 69 LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10, 70 /* 0.5 % downspread 33 kHz */ 71 LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11 72 }; 73 74 enum dc_voltage_swing { 75 VOLTAGE_SWING_LEVEL0 = 0, /* direct HW translation! */ 76 VOLTAGE_SWING_LEVEL1, 77 VOLTAGE_SWING_LEVEL2, 78 VOLTAGE_SWING_LEVEL3, 79 VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3 80 }; 81 82 enum dc_pre_emphasis { 83 PRE_EMPHASIS_DISABLED = 0, /* direct HW translation! */ 84 PRE_EMPHASIS_LEVEL1, 85 PRE_EMPHASIS_LEVEL2, 86 PRE_EMPHASIS_LEVEL3, 87 PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3 88 }; 89 /* Post Cursor 2 is optional for transmitter 90 * and it applies only to the main link operating at HBR2 91 */ 92 enum dc_post_cursor2 { 93 POST_CURSOR2_DISABLED = 0, /* direct HW translation! */ 94 POST_CURSOR2_LEVEL1, 95 POST_CURSOR2_LEVEL2, 96 POST_CURSOR2_LEVEL3, 97 POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3, 98 }; 99 100 enum dc_dp_ffe_preset_level { 101 DP_FFE_PRESET_LEVEL0 = 0, 102 DP_FFE_PRESET_LEVEL1, 103 DP_FFE_PRESET_LEVEL2, 104 DP_FFE_PRESET_LEVEL3, 105 DP_FFE_PRESET_LEVEL4, 106 DP_FFE_PRESET_LEVEL5, 107 DP_FFE_PRESET_LEVEL6, 108 DP_FFE_PRESET_LEVEL7, 109 DP_FFE_PRESET_LEVEL8, 110 DP_FFE_PRESET_LEVEL9, 111 DP_FFE_PRESET_LEVEL10, 112 DP_FFE_PRESET_LEVEL11, 113 DP_FFE_PRESET_LEVEL12, 114 DP_FFE_PRESET_LEVEL13, 115 DP_FFE_PRESET_LEVEL14, 116 DP_FFE_PRESET_LEVEL15, 117 DP_FFE_PRESET_MAX_LEVEL = DP_FFE_PRESET_LEVEL15, 118 }; 119 120 enum dc_dp_training_pattern { 121 DP_TRAINING_PATTERN_SEQUENCE_1 = 0, 122 DP_TRAINING_PATTERN_SEQUENCE_2, 123 DP_TRAINING_PATTERN_SEQUENCE_3, 124 DP_TRAINING_PATTERN_SEQUENCE_4, 125 DP_TRAINING_PATTERN_VIDEOIDLE, 126 DP_128b_132b_TPS1, 127 DP_128b_132b_TPS2, 128 DP_128b_132b_TPS2_CDS, 129 }; 130 131 enum dp_link_encoding { 132 DP_UNKNOWN_ENCODING = 0, 133 DP_8b_10b_ENCODING = 1, 134 DP_128b_132b_ENCODING = 2, 135 }; 136 137 enum dp_test_link_rate { 138 DP_TEST_LINK_RATE_RBR = 0x06, 139 DP_TEST_LINK_RATE_HBR = 0x0A, 140 DP_TEST_LINK_RATE_HBR2 = 0x14, 141 DP_TEST_LINK_RATE_HBR3 = 0x1E, 142 DP_TEST_LINK_RATE_UHBR10 = 0x01, 143 DP_TEST_LINK_RATE_UHBR20 = 0x02, 144 DP_TEST_LINK_RATE_UHBR13_5 = 0x03, 145 }; 146 147 struct dc_link_settings { 148 enum dc_lane_count lane_count; 149 enum dc_link_rate link_rate; 150 enum dc_link_spread link_spread; 151 bool use_link_rate_set; 152 uint8_t link_rate_set; 153 }; 154 155 union dc_dp_ffe_preset { 156 struct { 157 uint8_t level : 4; 158 uint8_t reserved : 1; 159 uint8_t no_preshoot : 1; 160 uint8_t no_deemphasis : 1; 161 uint8_t method2 : 1; 162 } settings; 163 uint8_t raw; 164 }; 165 166 struct dc_lane_settings { 167 enum dc_voltage_swing VOLTAGE_SWING; 168 enum dc_pre_emphasis PRE_EMPHASIS; 169 enum dc_post_cursor2 POST_CURSOR2; 170 union dc_dp_ffe_preset FFE_PRESET; 171 }; 172 173 struct dc_link_training_overrides { 174 enum dc_voltage_swing *voltage_swing; 175 enum dc_pre_emphasis *pre_emphasis; 176 enum dc_post_cursor2 *post_cursor2; 177 union dc_dp_ffe_preset *ffe_preset; 178 179 uint16_t *cr_pattern_time; 180 uint16_t *eq_pattern_time; 181 enum dc_dp_training_pattern *pattern_for_cr; 182 enum dc_dp_training_pattern *pattern_for_eq; 183 184 enum dc_link_spread *downspread; 185 bool *alternate_scrambler_reset; 186 bool *enhanced_framing; 187 bool *mst_enable; 188 bool *fec_enable; 189 }; 190 191 union payload_table_update_status { 192 struct { 193 uint8_t VC_PAYLOAD_TABLE_UPDATED:1; 194 uint8_t ACT_HANDLED:1; 195 } bits; 196 uint8_t raw; 197 }; 198 199 union dpcd_rev { 200 struct { 201 uint8_t MINOR:4; 202 uint8_t MAJOR:4; 203 } bits; 204 uint8_t raw; 205 }; 206 207 union max_lane_count { 208 struct { 209 uint8_t MAX_LANE_COUNT:5; 210 uint8_t POST_LT_ADJ_REQ_SUPPORTED:1; 211 uint8_t TPS3_SUPPORTED:1; 212 uint8_t ENHANCED_FRAME_CAP:1; 213 } bits; 214 uint8_t raw; 215 }; 216 217 union max_down_spread { 218 struct { 219 uint8_t MAX_DOWN_SPREAD:1; 220 uint8_t RESERVED:5; 221 uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1; 222 uint8_t TPS4_SUPPORTED:1; 223 } bits; 224 uint8_t raw; 225 }; 226 227 union mstm_cap { 228 struct { 229 uint8_t MST_CAP:1; 230 uint8_t RESERVED:7; 231 } bits; 232 uint8_t raw; 233 }; 234 235 union lane_count_set { 236 struct { 237 uint8_t LANE_COUNT_SET:5; 238 uint8_t POST_LT_ADJ_REQ_GRANTED:1; 239 uint8_t RESERVED:1; 240 uint8_t ENHANCED_FRAMING:1; 241 } bits; 242 uint8_t raw; 243 }; 244 245 union lane_status { 246 struct { 247 uint8_t CR_DONE_0:1; 248 uint8_t CHANNEL_EQ_DONE_0:1; 249 uint8_t SYMBOL_LOCKED_0:1; 250 uint8_t RESERVED0:1; 251 uint8_t CR_DONE_1:1; 252 uint8_t CHANNEL_EQ_DONE_1:1; 253 uint8_t SYMBOL_LOCKED_1:1; 254 uint8_t RESERVED_1:1; 255 } bits; 256 uint8_t raw; 257 }; 258 259 union device_service_irq { 260 struct { 261 uint8_t REMOTE_CONTROL_CMD_PENDING:1; 262 uint8_t AUTOMATED_TEST:1; 263 uint8_t CP_IRQ:1; 264 uint8_t MCCS_IRQ:1; 265 uint8_t DOWN_REP_MSG_RDY:1; 266 uint8_t UP_REQ_MSG_RDY:1; 267 uint8_t SINK_SPECIFIC:1; 268 uint8_t reserved:1; 269 } bits; 270 uint8_t raw; 271 }; 272 273 union sink_count { 274 struct { 275 uint8_t SINK_COUNT:6; 276 uint8_t CPREADY:1; 277 uint8_t RESERVED:1; 278 } bits; 279 uint8_t raw; 280 }; 281 282 union lane_align_status_updated { 283 struct { 284 uint8_t INTERLANE_ALIGN_DONE:1; 285 uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1; 286 uint8_t EQ_INTERLANE_ALIGN_DONE_128b_132b:1; 287 uint8_t CDS_INTERLANE_ALIGN_DONE_128b_132b:1; 288 uint8_t LT_FAILED_128b_132b:1; 289 uint8_t RESERVED:1; 290 uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1; 291 uint8_t LINK_STATUS_UPDATED:1; 292 } bits; 293 uint8_t raw; 294 }; 295 296 union lane_adjust { 297 struct { 298 uint8_t VOLTAGE_SWING_LANE:2; 299 uint8_t PRE_EMPHASIS_LANE:2; 300 uint8_t RESERVED:4; 301 } bits; 302 struct { 303 uint8_t PRESET_VALUE :4; 304 uint8_t RESERVED :4; 305 } tx_ffe; 306 uint8_t raw; 307 }; 308 309 union dpcd_training_pattern { 310 struct { 311 uint8_t TRAINING_PATTERN_SET:4; 312 uint8_t RECOVERED_CLOCK_OUT_EN:1; 313 uint8_t SCRAMBLING_DISABLE:1; 314 uint8_t SYMBOL_ERROR_COUNT_SEL:2; 315 } v1_4; 316 struct { 317 uint8_t TRAINING_PATTERN_SET:2; 318 uint8_t LINK_QUAL_PATTERN_SET:2; 319 uint8_t RESERVED:4; 320 } v1_3; 321 uint8_t raw; 322 }; 323 324 /* Training Lane is used to configure downstream DP device's voltage swing 325 and pre-emphasis levels*/ 326 /* The DPCD addresses are from 0x103 to 0x106*/ 327 union dpcd_training_lane { 328 struct { 329 uint8_t VOLTAGE_SWING_SET:2; 330 uint8_t MAX_SWING_REACHED:1; 331 uint8_t PRE_EMPHASIS_SET:2; 332 uint8_t MAX_PRE_EMPHASIS_REACHED:1; 333 uint8_t RESERVED:2; 334 } bits; 335 struct { 336 uint8_t PRESET_VALUE :4; 337 uint8_t RESERVED :4; 338 } tx_ffe; 339 uint8_t raw; 340 }; 341 342 /* TMDS-converter related */ 343 union dwnstream_port_caps_byte0 { 344 struct { 345 uint8_t DWN_STRM_PORTX_TYPE:3; 346 uint8_t DWN_STRM_PORTX_HPD:1; 347 uint8_t RESERVERD:4; 348 } bits; 349 uint8_t raw; 350 }; 351 352 /* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/ 353 enum dpcd_downstream_port_detailed_type { 354 DOWN_STREAM_DETAILED_DP = 0, 355 DOWN_STREAM_DETAILED_VGA, 356 DOWN_STREAM_DETAILED_DVI, 357 DOWN_STREAM_DETAILED_HDMI, 358 DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/ 359 DOWN_STREAM_DETAILED_DP_PLUS_PLUS 360 }; 361 362 union dwnstream_port_caps_byte2 { 363 struct { 364 uint8_t MAX_BITS_PER_COLOR_COMPONENT:2; 365 uint8_t MAX_ENCODED_LINK_BW_SUPPORT:3; 366 uint8_t SOURCE_CONTROL_MODE_SUPPORT:1; 367 uint8_t CONCURRENT_LINK_BRING_UP_SEQ_SUPPORT:1; 368 uint8_t RESERVED:1; 369 } bits; 370 uint8_t raw; 371 }; 372 373 union dp_downstream_port_present { 374 uint8_t byte; 375 struct { 376 uint8_t PORT_PRESENT:1; 377 uint8_t PORT_TYPE:2; 378 uint8_t FMT_CONVERSION:1; 379 uint8_t DETAILED_CAPS:1; 380 uint8_t RESERVED:3; 381 } fields; 382 }; 383 384 union dwnstream_port_caps_byte3_dvi { 385 struct { 386 uint8_t RESERVED1:1; 387 uint8_t DUAL_LINK:1; 388 uint8_t HIGH_COLOR_DEPTH:1; 389 uint8_t RESERVED2:5; 390 } bits; 391 uint8_t raw; 392 }; 393 394 union dwnstream_port_caps_byte3_hdmi { 395 struct { 396 uint8_t FRAME_SEQ_TO_FRAME_PACK:1; 397 uint8_t YCrCr422_PASS_THROUGH:1; 398 uint8_t YCrCr420_PASS_THROUGH:1; 399 uint8_t YCrCr422_CONVERSION:1; 400 uint8_t YCrCr420_CONVERSION:1; 401 uint8_t RESERVED:3; 402 } bits; 403 uint8_t raw; 404 }; 405 406 union hdmi_sink_encoded_link_bw_support { 407 struct { 408 uint8_t HDMI_SINK_ENCODED_LINK_BW_SUPPORT:3; 409 uint8_t RESERVED:5; 410 } bits; 411 uint8_t raw; 412 }; 413 414 union hdmi_encoded_link_bw { 415 struct { 416 uint8_t FRL_MODE:1; // Bit 0 417 uint8_t BW_9Gbps:1; 418 uint8_t BW_18Gbps:1; 419 uint8_t BW_24Gbps:1; 420 uint8_t BW_32Gbps:1; 421 uint8_t BW_40Gbps:1; 422 uint8_t BW_48Gbps:1; 423 uint8_t RESERVED:1; // Bit 7 424 } bits; 425 uint8_t raw; 426 }; 427 428 /*4-byte structure for detailed capabilities of a down-stream port 429 (DP-to-TMDS converter).*/ 430 union dwnstream_portxcaps { 431 struct { 432 union dwnstream_port_caps_byte0 byte0; 433 unsigned char max_TMDS_clock; //byte1 434 union dwnstream_port_caps_byte2 byte2; 435 436 union { 437 union dwnstream_port_caps_byte3_dvi byteDVI; 438 union dwnstream_port_caps_byte3_hdmi byteHDMI; 439 } byte3; 440 } bytes; 441 442 unsigned char raw[4]; 443 }; 444 445 union downstream_port { 446 struct { 447 unsigned char present:1; 448 unsigned char type:2; 449 unsigned char format_conv:1; 450 unsigned char detailed_caps:1; 451 unsigned char reserved:3; 452 } bits; 453 unsigned char raw; 454 }; 455 456 457 union sink_status { 458 struct { 459 uint8_t RX_PORT0_STATUS:1; 460 uint8_t RX_PORT1_STATUS:1; 461 uint8_t RESERVED:6; 462 } bits; 463 uint8_t raw; 464 }; 465 466 /*6-byte structure corresponding to 6 registers (200h-205h) 467 read during handling of HPD-IRQ*/ 468 union hpd_irq_data { 469 struct { 470 union sink_count sink_cnt;/* 200h */ 471 union device_service_irq device_service_irq;/* 201h */ 472 union lane_status lane01_status;/* 202h */ 473 union lane_status lane23_status;/* 203h */ 474 union lane_align_status_updated lane_status_updated;/* 204h */ 475 union sink_status sink_status; 476 } bytes; 477 uint8_t raw[6]; 478 }; 479 480 union down_stream_port_count { 481 struct { 482 uint8_t DOWN_STR_PORT_COUNT:4; 483 uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/ 484 /*Bit 6 = MSA_TIMING_PAR_IGNORED 485 0 = Sink device requires the MSA timing parameters 486 1 = Sink device is capable of rendering incoming video 487 stream without MSA timing parameters*/ 488 uint8_t IGNORE_MSA_TIMING_PARAM:1; 489 /*Bit 7 = OUI Support 490 0 = OUI not supported 491 1 = OUI supported 492 (OUI and Device Identification mandatory for DP 1.2)*/ 493 uint8_t OUI_SUPPORT:1; 494 } bits; 495 uint8_t raw; 496 }; 497 498 union down_spread_ctrl { 499 struct { 500 uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/ 501 /* Bits 4 = SPREAD_AMP. Spreading amplitude 502 0 = Main link signal is not downspread 503 1 = Main link signal is downspread <= 0.5% 504 with frequency in the range of 30kHz ~ 33kHz*/ 505 uint8_t SPREAD_AMP:1; 506 uint8_t RESERVED2:1;/*Bit 5 = RESERVED. Read all 0s*/ 507 /* Bit 6 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE. 508 0 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE is not enabled by the Source device (default) 509 1 = FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE is enabled by Source device */ 510 uint8_t FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE:1; 511 /*Bit 7 = MSA_TIMING_PAR_IGNORE_EN 512 0 = Source device will send valid data for the MSA Timing Params 513 1 = Source device may send invalid data for these MSA Timing Params*/ 514 uint8_t IGNORE_MSA_TIMING_PARAM:1; 515 } bits; 516 uint8_t raw; 517 }; 518 519 union dpcd_edp_config { 520 struct { 521 uint8_t PANEL_MODE_EDP:1; 522 uint8_t FRAMING_CHANGE_ENABLE:1; 523 uint8_t RESERVED:5; 524 uint8_t PANEL_SELF_TEST_ENABLE:1; 525 } bits; 526 uint8_t raw; 527 }; 528 529 struct dp_device_vendor_id { 530 uint8_t ieee_oui[3];/*24-bit IEEE OUI*/ 531 uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/ 532 }; 533 534 struct dp_sink_hw_fw_revision { 535 uint8_t ieee_hw_rev; 536 uint8_t ieee_fw_rev[2]; 537 }; 538 539 struct dpcd_vendor_signature { 540 bool is_valid; 541 542 union dpcd_ieee_vendor_signature { 543 struct { 544 uint8_t ieee_oui[3];/*24-bit IEEE OUI*/ 545 uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/ 546 uint8_t ieee_hw_rev; 547 uint8_t ieee_fw_rev[2]; 548 }; 549 uint8_t raw[12]; 550 } data; 551 }; 552 553 struct dpcd_amd_signature { 554 uint8_t AMD_IEEE_TxSignature_byte1; 555 uint8_t AMD_IEEE_TxSignature_byte2; 556 uint8_t AMD_IEEE_TxSignature_byte3; 557 }; 558 559 struct dpcd_amd_device_id { 560 uint8_t device_id_byte1; 561 uint8_t device_id_byte2; 562 uint8_t zero[4]; 563 uint8_t dce_version; 564 uint8_t dal_version_byte1; 565 uint8_t dal_version_byte2; 566 }; 567 568 struct dpcd_source_backlight_set { 569 struct { 570 uint8_t byte0; 571 uint8_t byte1; 572 uint8_t byte2; 573 uint8_t byte3; 574 } backlight_level_millinits; 575 576 struct { 577 uint8_t byte0; 578 uint8_t byte1; 579 } backlight_transition_time_ms; 580 }; 581 582 union dpcd_source_backlight_get { 583 struct { 584 uint32_t backlight_millinits_peak; /* 326h */ 585 uint32_t backlight_millinits_avg; /* 32Ah */ 586 } bytes; 587 uint8_t raw[8]; 588 }; 589 590 /*DPCD register of DP receiver capability field bits-*/ 591 union edp_configuration_cap { 592 struct { 593 uint8_t ALT_SCRAMBLER_RESET:1; 594 uint8_t FRAMING_CHANGE:1; 595 uint8_t RESERVED:1; 596 uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1; 597 uint8_t RESERVED2:4; 598 } bits; 599 uint8_t raw; 600 }; 601 602 union dprx_feature { 603 struct { 604 uint8_t GTC_CAP:1; // bit 0: DP 1.3+ 605 uint8_t SST_SPLIT_SDP_CAP:1; // bit 1: DP 1.4 606 uint8_t AV_SYNC_CAP:1; // bit 2: DP 1.3+ 607 uint8_t VSC_SDP_COLORIMETRY_SUPPORTED:1; // bit 3: DP 1.3+ 608 uint8_t VSC_EXT_VESA_SDP_SUPPORTED:1; // bit 4: DP 1.4 609 uint8_t VSC_EXT_VESA_SDP_CHAINING_SUPPORTED:1; // bit 5: DP 1.4 610 uint8_t VSC_EXT_CEA_SDP_SUPPORTED:1; // bit 6: DP 1.4 611 uint8_t VSC_EXT_CEA_SDP_CHAINING_SUPPORTED:1; // bit 7: DP 1.4 612 } bits; 613 uint8_t raw; 614 }; 615 616 union training_aux_rd_interval { 617 struct { 618 uint8_t TRAINIG_AUX_RD_INTERVAL:7; 619 uint8_t EXT_RECEIVER_CAP_FIELD_PRESENT:1; 620 } bits; 621 uint8_t raw; 622 }; 623 624 /* Automated test structures */ 625 union test_request { 626 struct { 627 uint8_t LINK_TRAINING :1; 628 uint8_t LINK_TEST_PATTRN :1; 629 uint8_t EDID_READ :1; 630 uint8_t PHY_TEST_PATTERN :1; 631 uint8_t PHY_TEST_CHANNEL_CODING_TYPE :2; 632 uint8_t AUDIO_TEST_PATTERN :1; 633 uint8_t TEST_AUDIO_DISABLED_VIDEO :1; 634 } bits; 635 uint8_t raw; 636 }; 637 638 union test_response { 639 struct { 640 uint8_t ACK :1; 641 uint8_t NO_ACK :1; 642 uint8_t EDID_CHECKSUM_WRITE:1; 643 uint8_t RESERVED :5; 644 } bits; 645 uint8_t raw; 646 }; 647 648 union phy_test_pattern { 649 struct { 650 /* This field is 7 bits for DP2.0 */ 651 uint8_t PATTERN :7; 652 uint8_t RESERVED :1; 653 } bits; 654 uint8_t raw; 655 }; 656 657 /* States of Compliance Test Specification (CTS DP1.2). */ 658 union compliance_test_state { 659 struct { 660 unsigned char STEREO_3D_RUNNING : 1; 661 unsigned char RESERVED : 7; 662 } bits; 663 unsigned char raw; 664 }; 665 666 union link_test_pattern { 667 struct { 668 /* dpcd_link_test_patterns */ 669 unsigned char PATTERN :2; 670 unsigned char RESERVED:6; 671 } bits; 672 unsigned char raw; 673 }; 674 675 union test_misc { 676 struct dpcd_test_misc_bits { 677 unsigned char SYNC_CLOCK :1; 678 /* dpcd_test_color_format */ 679 unsigned char CLR_FORMAT :2; 680 /* dpcd_test_dyn_range */ 681 unsigned char DYN_RANGE :1; 682 unsigned char YCBCR_COEFS :1; 683 /* dpcd_test_bit_depth */ 684 unsigned char BPC :3; 685 } bits; 686 unsigned char raw; 687 }; 688 689 union audio_test_mode { 690 struct { 691 unsigned char sampling_rate :4; 692 unsigned char channel_count :4; 693 } bits; 694 unsigned char raw; 695 }; 696 697 union audio_test_pattern_period { 698 struct { 699 unsigned char pattern_period :4; 700 unsigned char reserved :4; 701 } bits; 702 unsigned char raw; 703 }; 704 705 struct audio_test_pattern_type { 706 unsigned char value; 707 }; 708 709 struct dp_audio_test_data_flags { 710 uint8_t test_requested :1; 711 uint8_t disable_video :1; 712 }; 713 714 struct dp_audio_test_data { 715 716 struct dp_audio_test_data_flags flags; 717 uint8_t sampling_rate; 718 uint8_t channel_count; 719 uint8_t pattern_type; 720 uint8_t pattern_period[8]; 721 }; 722 723 /* FEC capability DPCD register field bits-*/ 724 union dpcd_fec_capability { 725 struct { 726 uint8_t FEC_CAPABLE:1; 727 uint8_t UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; 728 uint8_t CORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; 729 uint8_t BIT_ERROR_COUNT_CAPABLE:1; 730 uint8_t PARITY_BLOCK_ERROR_COUNT_CAPABLE:1; 731 uint8_t ARITY_BIT_ERROR_COUNT_CAPABLE:1; 732 uint8_t FEC_RUNNING_INDICATOR_SUPPORTED:1; 733 uint8_t FEC_ERROR_REPORTING_POLICY_SUPPORTED:1; 734 } bits; 735 uint8_t raw; 736 }; 737 738 /* DSC capability DPCD register field bits-*/ 739 struct dpcd_dsc_support { 740 uint8_t DSC_SUPPORT :1; 741 uint8_t DSC_PASSTHROUGH_SUPPORT :1; 742 uint8_t RESERVED :6; 743 }; 744 745 struct dpcd_dsc_algorithm_revision { 746 uint8_t DSC_VERSION_MAJOR :4; 747 uint8_t DSC_VERSION_MINOR :4; 748 }; 749 750 struct dpcd_dsc_rc_buffer_block_size { 751 uint8_t RC_BLOCK_BUFFER_SIZE :2; 752 uint8_t RESERVED :6; 753 }; 754 755 struct dpcd_dsc_slice_capability1 { 756 uint8_t ONE_SLICE_PER_DP_DSC_SINK_DEVICE :1; 757 uint8_t TWO_SLICES_PER_DP_DSC_SINK_DEVICE :1; 758 uint8_t RESERVED :1; 759 uint8_t FOUR_SLICES_PER_DP_DSC_SINK_DEVICE :1; 760 uint8_t SIX_SLICES_PER_DP_DSC_SINK_DEVICE :1; 761 uint8_t EIGHT_SLICES_PER_DP_DSC_SINK_DEVICE :1; 762 uint8_t TEN_SLICES_PER_DP_DSC_SINK_DEVICE :1; 763 uint8_t TWELVE_SLICES_PER_DP_DSC_SINK_DEVICE :1; 764 }; 765 766 struct dpcd_dsc_line_buffer_bit_depth { 767 uint8_t LINE_BUFFER_BIT_DEPTH :4; 768 uint8_t RESERVED :4; 769 }; 770 771 struct dpcd_dsc_block_prediction_support { 772 uint8_t BLOCK_PREDICTION_SUPPORT:1; 773 uint8_t RESERVED :7; 774 }; 775 776 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor { 777 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_LOW :7; 778 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_HIGH :7; 779 uint8_t RESERVED :2; 780 }; 781 782 struct dpcd_dsc_decoder_color_format_capabilities { 783 uint8_t RGB_SUPPORT :1; 784 uint8_t Y_CB_CR_444_SUPPORT :1; 785 uint8_t Y_CB_CR_SIMPLE_422_SUPPORT :1; 786 uint8_t Y_CB_CR_NATIVE_422_SUPPORT :1; 787 uint8_t Y_CB_CR_NATIVE_420_SUPPORT :1; 788 uint8_t RESERVED :3; 789 }; 790 791 struct dpcd_dsc_decoder_color_depth_capabilities { 792 uint8_t RESERVED0 :1; 793 uint8_t EIGHT_BITS_PER_COLOR_SUPPORT :1; 794 uint8_t TEN_BITS_PER_COLOR_SUPPORT :1; 795 uint8_t TWELVE_BITS_PER_COLOR_SUPPORT :1; 796 uint8_t RESERVED1 :4; 797 }; 798 799 struct dpcd_peak_dsc_throughput_dsc_sink { 800 uint8_t THROUGHPUT_MODE_0:4; 801 uint8_t THROUGHPUT_MODE_1:4; 802 }; 803 804 struct dpcd_dsc_slice_capabilities_2 { 805 uint8_t SIXTEEN_SLICES_PER_DSC_SINK_DEVICE :1; 806 uint8_t TWENTY_SLICES_PER_DSC_SINK_DEVICE :1; 807 uint8_t TWENTYFOUR_SLICES_PER_DSC_SINK_DEVICE :1; 808 uint8_t RESERVED :5; 809 }; 810 811 struct dpcd_bits_per_pixel_increment{ 812 uint8_t INCREMENT_OF_BITS_PER_PIXEL_SUPPORTED :3; 813 uint8_t RESERVED :5; 814 }; 815 union dpcd_dsc_basic_capabilities { 816 struct { 817 struct dpcd_dsc_support dsc_support; 818 struct dpcd_dsc_algorithm_revision dsc_algorithm_revision; 819 struct dpcd_dsc_rc_buffer_block_size dsc_rc_buffer_block_size; 820 uint8_t dsc_rc_buffer_size; 821 struct dpcd_dsc_slice_capability1 dsc_slice_capabilities_1; 822 struct dpcd_dsc_line_buffer_bit_depth dsc_line_buffer_bit_depth; 823 struct dpcd_dsc_block_prediction_support dsc_block_prediction_support; 824 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor maximum_bits_per_pixel_supported_by_the_decompressor; 825 struct dpcd_dsc_decoder_color_format_capabilities dsc_decoder_color_format_capabilities; 826 struct dpcd_dsc_decoder_color_depth_capabilities dsc_decoder_color_depth_capabilities; 827 struct dpcd_peak_dsc_throughput_dsc_sink peak_dsc_throughput_dsc_sink; 828 uint8_t dsc_maximum_slice_width; 829 struct dpcd_dsc_slice_capabilities_2 dsc_slice_capabilities_2; 830 uint8_t reserved; 831 struct dpcd_bits_per_pixel_increment bits_per_pixel_increment; 832 } fields; 833 uint8_t raw[16]; 834 }; 835 836 union dpcd_dsc_branch_decoder_capabilities { 837 struct { 838 uint8_t BRANCH_OVERALL_THROUGHPUT_0; 839 uint8_t BRANCH_OVERALL_THROUGHPUT_1; 840 uint8_t BRANCH_MAX_LINE_WIDTH; 841 } fields; 842 uint8_t raw[3]; 843 }; 844 845 struct dpcd_dsc_capabilities { 846 union dpcd_dsc_basic_capabilities dsc_basic_caps; 847 union dpcd_dsc_branch_decoder_capabilities dsc_branch_decoder_caps; 848 }; 849 850 /* These parameters are from PSR capabilities reported by Sink DPCD */ 851 struct psr_caps { 852 unsigned char psr_version; 853 unsigned int psr_rfb_setup_time; 854 bool psr_exit_link_training_required; 855 unsigned char edp_revision; 856 unsigned char support_ver; 857 bool su_granularity_required; 858 bool y_coordinate_required; 859 uint8_t su_y_granularity; 860 bool alpm_cap; 861 bool standby_support; 862 uint8_t rate_control_caps; 863 unsigned int psr_power_opt_flag; 864 }; 865 866 union dpcd_dprx_feature_enumeration_list_cont_1 { 867 struct { 868 uint8_t ADAPTIVE_SYNC_SDP_SUPPORT:1; 869 uint8_t AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED: 1; 870 uint8_t RESERVED0: 2; 871 uint8_t VSC_EXT_SDP_VER1_SUPPORT: 1; 872 uint8_t RESERVED1: 3; 873 } bits; 874 uint8_t raw; 875 }; 876 877 struct adaptive_sync_caps { 878 union dpcd_dprx_feature_enumeration_list_cont_1 dp_adap_sync_caps; 879 }; 880 881 /* Length of router topology ID read from DPCD in bytes. */ 882 #define DPCD_USB4_TOPOLOGY_ID_LEN 5 883 884 /* DPCD[0xE000D] DP_TUNNELING_CAPABILITIES SUPPORT register. */ 885 union dp_tun_cap_support { 886 struct { 887 uint8_t dp_tunneling :1; 888 uint8_t rsvd :5; 889 uint8_t panel_replay_tun_opt :1; 890 uint8_t dpia_bw_alloc :1; 891 } bits; 892 uint8_t raw; 893 }; 894 895 /* DPCD[0xE000E] DP_IN_ADAPTER_INFO register. */ 896 union dpia_info { 897 struct { 898 uint8_t dpia_num :5; 899 uint8_t rsvd :3; 900 } bits; 901 uint8_t raw; 902 }; 903 904 /* DP Tunneling over USB4 */ 905 struct dpcd_usb4_dp_tunneling_info { 906 union dp_tun_cap_support dp_tun_cap; 907 union dpia_info dpia_info; 908 uint8_t usb4_driver_id; 909 uint8_t usb4_topology_id[DPCD_USB4_TOPOLOGY_ID_LEN]; 910 }; 911 912 #ifndef DP_MAIN_LINK_CHANNEL_CODING_CAP 913 #define DP_MAIN_LINK_CHANNEL_CODING_CAP 0x006 914 #endif 915 #ifndef DP_SINK_VIDEO_FALLBACK_FORMATS 916 #define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 917 #endif 918 #ifndef DP_FEC_CAPABILITY_1 919 #define DP_FEC_CAPABILITY_1 0x091 920 #endif 921 #ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT 922 #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 923 #endif 924 #ifndef DP_LINK_SQUARE_PATTERN 925 #define DP_LINK_SQUARE_PATTERN 0x10F 926 #endif 927 #ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX 928 #define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX 0x110 929 #endif 930 #ifndef DP_DSC_CONFIGURATION 931 #define DP_DSC_CONFIGURATION 0x161 932 #endif 933 #ifndef DP_PHY_SQUARE_PATTERN 934 #define DP_PHY_SQUARE_PATTERN 0x249 935 #endif 936 #ifndef DP_128b_132b_SUPPORTED_LINK_RATES 937 #define DP_128b_132b_SUPPORTED_LINK_RATES 0x2215 938 #endif 939 #ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL 940 #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL 0x2216 941 #endif 942 #ifndef DP_LINK_SQUARE_PATTERN 943 #define DP_LINK_SQUARE_PATTERN 0x10F 944 #endif 945 #ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX 946 #define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX 0x2217 947 #endif 948 #ifndef DP_TEST_264BIT_CUSTOM_PATTERN_7_0 949 #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0X2230 950 #endif 951 #ifndef DP_TEST_264BIT_CUSTOM_PATTERN_263_256 952 #define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0X2250 953 #endif 954 #ifndef DP_DSC_SUPPORT_AND_DECODER_COUNT 955 #define DP_DSC_SUPPORT_AND_DECODER_COUNT 0x2260 956 #endif 957 #ifndef DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 958 #define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 959 #endif 960 #ifndef DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK 961 #define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) 962 #endif 963 #ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK 964 #define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) 965 #endif 966 #ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 967 #define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 968 #endif 969 #ifndef DP_DSC_DECODER_COUNT_MASK 970 #define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) 971 #endif 972 #ifndef DP_DSC_DECODER_COUNT_SHIFT 973 #define DP_DSC_DECODER_COUNT_SHIFT 5 974 #endif 975 #ifndef DP_MAIN_LINK_CHANNEL_CODING_SET 976 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 977 #endif 978 #ifndef DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 979 #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006 980 #endif 981 #ifndef DP_PHY_REPEATER_128b_132b_RATES 982 #define DP_PHY_REPEATER_128b_132b_RATES 0xF0007 983 #endif 984 #ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 985 #define DP_128b_132b_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xF0022 986 #endif 987 #ifndef DP_INTRA_HOP_AUX_REPLY_INDICATION 988 #define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) 989 /* TODO - Use DRM header to replace above once available */ 990 #endif // DP_INTRA_HOP_AUX_REPLY_INDICATION 991 992 #ifndef DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 993 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50 994 #endif 995 union dp_main_line_channel_coding_cap { 996 struct { 997 uint8_t DP_8b_10b_SUPPORTED :1; 998 uint8_t DP_128b_132b_SUPPORTED :1; 999 uint8_t RESERVED :6; 1000 } bits; 1001 uint8_t raw; 1002 }; 1003 1004 union dp_main_link_channel_coding_lttpr_cap { 1005 struct { 1006 uint8_t DP_128b_132b_SUPPORTED :1; 1007 uint8_t RESERVED :7; 1008 } bits; 1009 uint8_t raw; 1010 }; 1011 1012 union dp_128b_132b_supported_link_rates { 1013 struct { 1014 uint8_t UHBR10 :1; 1015 uint8_t UHBR20 :1; 1016 uint8_t UHBR13_5:1; 1017 uint8_t RESERVED:5; 1018 } bits; 1019 uint8_t raw; 1020 }; 1021 1022 union dp_128b_132b_supported_lttpr_link_rates { 1023 struct { 1024 uint8_t UHBR10 :1; 1025 uint8_t UHBR20 :1; 1026 uint8_t UHBR13_5:1; 1027 uint8_t RESERVED:5; 1028 } bits; 1029 uint8_t raw; 1030 }; 1031 1032 union dp_sink_video_fallback_formats { 1033 struct { 1034 uint8_t dp_1024x768_60Hz_24bpp_support :1; 1035 uint8_t dp_1280x720_60Hz_24bpp_support :1; 1036 uint8_t dp_1920x1080_60Hz_24bpp_support :1; 1037 uint8_t RESERVED :5; 1038 } bits; 1039 uint8_t raw; 1040 }; 1041 1042 union dp_fec_capability1 { 1043 struct { 1044 uint8_t AGGREGATED_ERROR_COUNTERS_CAPABLE :1; 1045 uint8_t RESERVED :7; 1046 } bits; 1047 uint8_t raw; 1048 }; 1049 1050 union dp_cable_id { 1051 struct { 1052 uint8_t UHBR10_20_CAPABILITY :2; 1053 uint8_t UHBR13_5_CAPABILITY :1; 1054 uint8_t CABLE_TYPE :3; 1055 uint8_t RESERVED :2; 1056 } bits; 1057 uint8_t raw; 1058 }; 1059 1060 struct dp_color_depth_caps { 1061 uint8_t support_6bpc :1; 1062 uint8_t support_8bpc :1; 1063 uint8_t support_10bpc :1; 1064 uint8_t support_12bpc :1; 1065 uint8_t support_16bpc :1; 1066 uint8_t RESERVED :3; 1067 }; 1068 1069 struct dp_encoding_format_caps { 1070 uint8_t support_rgb :1; 1071 uint8_t support_ycbcr444:1; 1072 uint8_t support_ycbcr422:1; 1073 uint8_t support_ycbcr420:1; 1074 uint8_t RESERVED :4; 1075 }; 1076 1077 union dp_dfp_cap_ext { 1078 struct { 1079 uint8_t supported; 1080 uint8_t max_pixel_rate_in_mps[2]; 1081 uint8_t max_video_h_active_width[2]; 1082 uint8_t max_video_v_active_height[2]; 1083 struct dp_encoding_format_caps encoding_format_caps; 1084 struct dp_color_depth_caps rgb_color_depth_caps; 1085 struct dp_color_depth_caps ycbcr444_color_depth_caps; 1086 struct dp_color_depth_caps ycbcr422_color_depth_caps; 1087 struct dp_color_depth_caps ycbcr420_color_depth_caps; 1088 } fields; 1089 uint8_t raw[12]; 1090 }; 1091 1092 union dp_128b_132b_training_aux_rd_interval { 1093 struct { 1094 uint8_t VALUE :7; 1095 uint8_t UNIT :1; 1096 } bits; 1097 uint8_t raw; 1098 }; 1099 1100 union edp_alpm_caps { 1101 struct { 1102 uint8_t AUX_WAKE_ALPM_CAP :1; 1103 uint8_t PM_STATE_2A_SUPPORT :1; 1104 uint8_t AUX_LESS_ALPM_CAP :1; 1105 uint8_t RESERVED :5; 1106 } bits; 1107 uint8_t raw; 1108 }; 1109 1110 union edp_psr_dpcd_caps { 1111 struct { 1112 uint8_t LINK_TRAINING_ON_EXIT_NOT_REQUIRED :1; 1113 uint8_t PSR_SETUP_TIME :3; 1114 uint8_t Y_COORDINATE_REQUIRED :1; 1115 uint8_t SU_GRANULARITY_REQUIRED :1; 1116 uint8_t FRAME_SYNC_IS_NOT_NEEDED_FOR_SU :1; 1117 uint8_t RESERVED :1; 1118 } bits; 1119 uint8_t raw; 1120 }; 1121 1122 struct edp_psr_info { 1123 uint8_t psr_version; 1124 union edp_psr_dpcd_caps psr_dpcd_caps; 1125 uint8_t psr2_su_y_granularity_cap; 1126 uint8_t force_psrsu_cap; 1127 }; 1128 1129 struct dprx_states { 1130 bool cable_id_written; 1131 }; 1132 1133 enum dpcd_downstream_port_max_bpc { 1134 DOWN_STREAM_MAX_8BPC = 0, 1135 DOWN_STREAM_MAX_10BPC, 1136 DOWN_STREAM_MAX_12BPC, 1137 DOWN_STREAM_MAX_16BPC 1138 }; 1139 1140 enum link_training_offset { 1141 DPRX = 0, 1142 LTTPR_PHY_REPEATER1 = 1, 1143 LTTPR_PHY_REPEATER2 = 2, 1144 LTTPR_PHY_REPEATER3 = 3, 1145 LTTPR_PHY_REPEATER4 = 4, 1146 LTTPR_PHY_REPEATER5 = 5, 1147 LTTPR_PHY_REPEATER6 = 6, 1148 LTTPR_PHY_REPEATER7 = 7, 1149 LTTPR_PHY_REPEATER8 = 8 1150 }; 1151 1152 #define MAX_REPEATER_CNT 8 1153 1154 struct dc_lttpr_caps { 1155 union dpcd_rev revision; 1156 uint8_t mode; 1157 uint8_t max_lane_count; 1158 uint8_t max_link_rate; 1159 uint8_t phy_repeater_cnt; 1160 uint8_t max_ext_timeout; 1161 union dp_main_link_channel_coding_lttpr_cap main_link_channel_coding; 1162 union dp_128b_132b_supported_lttpr_link_rates supported_128b_132b_rates; 1163 uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1]; 1164 }; 1165 1166 struct dc_dongle_dfp_cap_ext { 1167 bool supported; 1168 uint16_t max_pixel_rate_in_mps; 1169 uint16_t max_video_h_active_width; 1170 uint16_t max_video_v_active_height; 1171 struct dp_encoding_format_caps encoding_format_caps; 1172 struct dp_color_depth_caps rgb_color_depth_caps; 1173 struct dp_color_depth_caps ycbcr444_color_depth_caps; 1174 struct dp_color_depth_caps ycbcr422_color_depth_caps; 1175 struct dp_color_depth_caps ycbcr420_color_depth_caps; 1176 }; 1177 1178 struct dc_dongle_caps { 1179 /* dongle type (DP converter, CV smart dongle) */ 1180 enum display_dongle_type dongle_type; 1181 bool extendedCapValid; 1182 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1183 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1184 bool is_dp_hdmi_s3d_converter; 1185 bool is_dp_hdmi_ycbcr422_pass_through; 1186 bool is_dp_hdmi_ycbcr420_pass_through; 1187 bool is_dp_hdmi_ycbcr422_converter; 1188 bool is_dp_hdmi_ycbcr420_converter; 1189 uint32_t dp_hdmi_max_bpc; 1190 uint32_t dp_hdmi_max_pixel_clk_in_khz; 1191 uint32_t dp_hdmi_frl_max_link_bw_in_kbps; 1192 struct dc_dongle_dfp_cap_ext dfp_cap_ext; 1193 }; 1194 1195 struct dpcd_caps { 1196 union dpcd_rev dpcd_rev; 1197 union max_lane_count max_ln_count; 1198 union max_down_spread max_down_spread; 1199 union dprx_feature dprx_feature; 1200 1201 /* valid only for eDP v1.4 or higher*/ 1202 uint8_t edp_supported_link_rates_count; 1203 enum dc_link_rate edp_supported_link_rates[8]; 1204 1205 /* dongle type (DP converter, CV smart dongle) */ 1206 enum display_dongle_type dongle_type; 1207 bool is_dongle_type_one; 1208 /* branch device or sink device */ 1209 bool is_branch_dev; 1210 /* Dongle's downstream count. */ 1211 union sink_count sink_count; 1212 bool is_mst_capable; 1213 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1214 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1215 struct dc_dongle_caps dongle_caps; 1216 1217 uint32_t sink_dev_id; 1218 int8_t sink_dev_id_str[6]; 1219 int8_t sink_hw_revision; 1220 int8_t sink_fw_revision[2]; 1221 1222 uint32_t branch_dev_id; 1223 int8_t branch_dev_name[6]; 1224 int8_t branch_hw_revision; 1225 int8_t branch_fw_revision[2]; 1226 1227 bool allow_invalid_MSA_timing_param; 1228 bool panel_mode_edp; 1229 bool dpcd_display_control_capable; 1230 bool ext_receiver_cap_field_present; 1231 bool set_power_state_capable_edp; 1232 bool dynamic_backlight_capable_edp; 1233 union dpcd_fec_capability fec_cap; 1234 struct dpcd_dsc_capabilities dsc_caps; 1235 struct dc_lttpr_caps lttpr_caps; 1236 struct adaptive_sync_caps adaptive_sync_caps; 1237 struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; 1238 1239 union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; 1240 union dp_main_line_channel_coding_cap channel_coding_cap; 1241 union dp_sink_video_fallback_formats fallback_formats; 1242 union dp_fec_capability1 fec_cap1; 1243 union dp_cable_id cable_id; 1244 uint8_t edp_rev; 1245 union edp_alpm_caps alpm_caps; 1246 struct edp_psr_info psr_info; 1247 }; 1248 1249 union dpcd_sink_ext_caps { 1250 struct { 1251 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1252 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1253 */ 1254 uint8_t sdr_aux_backlight_control : 1; 1255 uint8_t hdr_aux_backlight_control : 1; 1256 uint8_t reserved_1 : 2; 1257 uint8_t oled : 1; 1258 uint8_t reserved_2 : 1; 1259 uint8_t miniled : 1; 1260 uint8_t reserved : 1; 1261 } bits; 1262 uint8_t raw; 1263 }; 1264 #endif /* DC_DP_TYPES_H */ 1265