1 #ifndef __X86_CPUID_H__
2 #define __X86_CPUID_H__
3
4 #include <asm/cpufeatureset.h>
5 #include <asm/percpu.h>
6
7 #define FEATURESET_1d 0 /* 0x00000001.edx */
8 #define FEATURESET_1c 1 /* 0x00000001.ecx */
9 #define FEATURESET_e1d 2 /* 0x80000001.edx */
10 #define FEATURESET_e1c 3 /* 0x80000001.ecx */
11 #define FEATURESET_Da1 4 /* 0x0000000d:1.eax */
12 #define FEATURESET_7b0 5 /* 0x00000007:0.ebx */
13 #define FEATURESET_7c0 6 /* 0x00000007:0.ecx */
14 #define FEATURESET_e7d 7 /* 0x80000007.edx */
15 #define FEATURESET_e8b 8 /* 0x80000008.ebx */
16 #define FEATURESET_7d0 9 /* 0x00000007:0.edx */
17
18 #ifndef __ASSEMBLY__
19 #include <xen/types.h>
20 #include <xen/kernel.h>
21 #include <asm/x86_emulate.h>
22 #include <public/sysctl.h>
23
24 extern const uint32_t known_features[FSCAPINTS];
25 extern const uint32_t special_features[FSCAPINTS];
26
27 void init_guest_cpuid(void);
28
29 const uint32_t *lookup_deep_deps(uint32_t feature);
30
31 /*
32 * Expected levelling capabilities (given cpuid vendor/family information),
33 * and levelling capabilities actually available (given MSR probing).
34 */
35 #define LCAP_faulting XEN_SYSCTL_CPU_LEVELCAP_faulting
36 #define LCAP_1cd (XEN_SYSCTL_CPU_LEVELCAP_ecx | \
37 XEN_SYSCTL_CPU_LEVELCAP_edx)
38 #define LCAP_e1cd (XEN_SYSCTL_CPU_LEVELCAP_extd_ecx | \
39 XEN_SYSCTL_CPU_LEVELCAP_extd_edx)
40 #define LCAP_Da1 XEN_SYSCTL_CPU_LEVELCAP_xsave_eax
41 #define LCAP_6c XEN_SYSCTL_CPU_LEVELCAP_thermal_ecx
42 #define LCAP_7ab0 (XEN_SYSCTL_CPU_LEVELCAP_l7s0_eax | \
43 XEN_SYSCTL_CPU_LEVELCAP_l7s0_ebx)
44 extern unsigned int expected_levelling_cap, levelling_caps;
45
46 struct cpuidmasks
47 {
48 uint64_t _1cd;
49 uint64_t e1cd;
50 uint64_t Da1;
51 uint64_t _6c;
52 uint64_t _7ab0;
53 };
54
55 /* Per CPU shadows of masking MSR values, for lazy context switching. */
56 DECLARE_PER_CPU(struct cpuidmasks, cpuidmasks);
57
58 /* Default masking MSR values, calculated at boot. */
59 extern struct cpuidmasks cpuidmask_defaults;
60
61 #define CPUID_GUEST_NR_BASIC (0xdu + 1)
62 #define CPUID_GUEST_NR_FEAT (0u + 1)
63 #define CPUID_GUEST_NR_CACHE (5u + 1)
64 #define CPUID_GUEST_NR_XSTATE (62u + 1)
65 #define CPUID_GUEST_NR_EXTD_INTEL (0x8u + 1)
66 #define CPUID_GUEST_NR_EXTD_AMD (0x1cu + 1)
67 #define CPUID_GUEST_NR_EXTD MAX(CPUID_GUEST_NR_EXTD_INTEL, \
68 CPUID_GUEST_NR_EXTD_AMD)
69
70 struct cpuid_policy
71 {
72 #define DECL_BITFIELD(word) _DECL_BITFIELD(FEATURESET_ ## word)
73 #define _DECL_BITFIELD(x) __DECL_BITFIELD(x)
74 #define __DECL_BITFIELD(x) CPUID_BITFIELD_ ## x
75
76 /* Basic leaves: 0x000000xx */
77 union {
78 struct cpuid_leaf raw[CPUID_GUEST_NR_BASIC];
79 struct {
80 /* Leaf 0x0 - Max and vendor. */
81 uint32_t max_leaf, vendor_ebx, vendor_ecx, vendor_edx;
82
83 /* Leaf 0x1 - Family/model/stepping and features. */
84 uint32_t raw_fms;
85 uint8_t :8, /* Brand ID. */
86 clflush_size, /* Number of 8-byte blocks per cache line. */
87 lppp, /* Logical processors per package. */
88 apic_id; /* Initial APIC ID. */
89 union {
90 uint32_t _1c;
91 struct { DECL_BITFIELD(1c); };
92 };
93 union {
94 uint32_t _1d;
95 struct { DECL_BITFIELD(1d); };
96 };
97
98 /* Leaf 0x2 - TLB/Cache/Prefetch. */
99 uint8_t l2_nr_queries; /* Documented as fixed to 1. */
100 uint8_t l2_desc[15];
101
102 uint64_t :64, :64; /* Leaf 0x3 - PSN. */
103 uint64_t :64, :64; /* Leaf 0x4 - Structured Cache. */
104 uint64_t :64, :64; /* Leaf 0x5 - MONITOR. */
105 uint64_t :64, :64; /* Leaf 0x6 - Therm/Perf. */
106 uint64_t :64, :64; /* Leaf 0x7 - Structured Features. */
107 uint64_t :64, :64; /* Leaf 0x8 - rsvd */
108 uint64_t :64, :64; /* Leaf 0x9 - DCA */
109
110 /* Leaf 0xa - Intel PMU. */
111 uint8_t pmu_version;
112 };
113 } basic;
114
115 /* Structured cache leaf: 0x00000004[xx] */
116 union {
117 struct cpuid_leaf raw[CPUID_GUEST_NR_CACHE];
118 struct cpuid_cache_leaf {
119 uint32_t type:5,
120 :27, :32, :32, :32;
121 } subleaf[CPUID_GUEST_NR_CACHE];
122 } cache;
123
124 /* Structured feature leaf: 0x00000007[xx] */
125 union {
126 struct cpuid_leaf raw[CPUID_GUEST_NR_FEAT];
127 struct {
128 /* Subleaf 0. */
129 uint32_t max_subleaf;
130 union {
131 uint32_t _7b0;
132 struct { DECL_BITFIELD(7b0); };
133 };
134 union {
135 uint32_t _7c0;
136 struct { DECL_BITFIELD(7c0); };
137 };
138 union {
139 uint32_t _7d0;
140 struct { DECL_BITFIELD(7d0); };
141 };
142 };
143 } feat;
144
145 /* Xstate feature leaf: 0x0000000D[xx] */
146 union {
147 struct cpuid_leaf raw[CPUID_GUEST_NR_XSTATE];
148
149 struct {
150 /* Subleaf 0. */
151 uint32_t xcr0_low, /* b */:32, max_size, xcr0_high;
152
153 /* Subleaf 1. */
154 union {
155 uint32_t Da1;
156 struct { DECL_BITFIELD(Da1); };
157 };
158 uint32_t /* b */:32, xss_low, xss_high;
159 };
160
161 /* Per-component common state. Valid for i >= 2. */
162 struct {
163 uint32_t size, offset;
164 bool xss:1, align:1;
165 uint32_t _res_d;
166 } comp[CPUID_GUEST_NR_XSTATE];
167 } xstate;
168
169 /* Extended leaves: 0x800000xx */
170 union {
171 struct cpuid_leaf raw[CPUID_GUEST_NR_EXTD];
172 struct {
173 /* Leaf 0x80000000 - Max and vendor. */
174 uint32_t max_leaf, vendor_ebx, vendor_ecx, vendor_edx;
175
176 /* Leaf 0x80000001 - Family/model/stepping and features. */
177 uint32_t raw_fms, /* b */:32;
178 union {
179 uint32_t e1c;
180 struct { DECL_BITFIELD(e1c); };
181 };
182 union {
183 uint32_t e1d;
184 struct { DECL_BITFIELD(e1d); };
185 };
186
187 uint64_t :64, :64; /* Brand string. */
188 uint64_t :64, :64; /* Brand string. */
189 uint64_t :64, :64; /* Brand string. */
190 uint64_t :64, :64; /* L1 cache/TLB. */
191 uint64_t :64, :64; /* L2/3 cache/TLB. */
192
193 /* Leaf 0x80000007 - Advanced Power Management. */
194 uint32_t /* a */:32, /* b */:32, /* c */:32;
195 union {
196 uint32_t e7d;
197 struct { DECL_BITFIELD(e7d); };
198 };
199
200 /* Leaf 0x80000008 - Misc addr/feature info. */
201 uint8_t maxphysaddr, maxlinaddr, :8, :8;
202 union {
203 uint32_t e8b;
204 struct { DECL_BITFIELD(e8b); };
205 };
206 uint32_t /* c */:32, /* d */:32;
207 };
208 } extd;
209
210 #undef __DECL_BITFIELD
211 #undef _DECL_BITFIELD
212 #undef DECL_BITFIELD
213
214 /* Toolstack selected Hypervisor max_leaf (if non-zero). */
215 uint8_t hv_limit, hv2_limit;
216
217 /* Value calculated from raw data above. */
218 uint8_t x86_vendor;
219 };
220
221 /* Fill in a featureset bitmap from a CPUID policy. */
cpuid_policy_to_featureset(const struct cpuid_policy * p,uint32_t fs[FSCAPINTS])222 static inline void cpuid_policy_to_featureset(
223 const struct cpuid_policy *p, uint32_t fs[FSCAPINTS])
224 {
225 fs[FEATURESET_1d] = p->basic._1d;
226 fs[FEATURESET_1c] = p->basic._1c;
227 fs[FEATURESET_e1d] = p->extd.e1d;
228 fs[FEATURESET_e1c] = p->extd.e1c;
229 fs[FEATURESET_Da1] = p->xstate.Da1;
230 fs[FEATURESET_7b0] = p->feat._7b0;
231 fs[FEATURESET_7c0] = p->feat._7c0;
232 fs[FEATURESET_e7d] = p->extd.e7d;
233 fs[FEATURESET_e8b] = p->extd.e8b;
234 fs[FEATURESET_7d0] = p->feat._7d0;
235 }
236
237 /* Fill in a CPUID policy from a featureset bitmap. */
cpuid_featureset_to_policy(const uint32_t fs[FSCAPINTS],struct cpuid_policy * p)238 static inline void cpuid_featureset_to_policy(
239 const uint32_t fs[FSCAPINTS], struct cpuid_policy *p)
240 {
241 p->basic._1d = fs[FEATURESET_1d];
242 p->basic._1c = fs[FEATURESET_1c];
243 p->extd.e1d = fs[FEATURESET_e1d];
244 p->extd.e1c = fs[FEATURESET_e1c];
245 p->xstate.Da1 = fs[FEATURESET_Da1];
246 p->feat._7b0 = fs[FEATURESET_7b0];
247 p->feat._7c0 = fs[FEATURESET_7c0];
248 p->extd.e7d = fs[FEATURESET_e7d];
249 p->extd.e8b = fs[FEATURESET_e8b];
250 p->feat._7d0 = fs[FEATURESET_7d0];
251 }
252
253 extern struct cpuid_policy raw_cpuid_policy, host_cpuid_policy,
254 pv_max_cpuid_policy, hvm_max_cpuid_policy;
255
256 /* Allocate and initialise a CPUID policy suitable for the domain. */
257 int init_domain_cpuid_policy(struct domain *d);
258
259 /* Clamp the CPUID policy to reality. */
260 void recalculate_cpuid_policy(struct domain *d);
261
262 void guest_cpuid(const struct vcpu *v, uint32_t leaf,
263 uint32_t subleaf, struct cpuid_leaf *res);
264
265 #endif /* __ASSEMBLY__ */
266 #endif /* !__X86_CPUID_H__ */
267
268 /*
269 * Local variables:
270 * mode: C
271 * c-file-style: "BSD"
272 * c-basic-offset: 4
273 * tab-width: 4
274 * indent-tabs-mode: nil
275 * End:
276 */
277