1 // SPDX-License-Identifier: GPL-2.0-only
2 /****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2018 Solarflare Communications Inc.
5 * Copyright 2019-2022 Xilinx Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation, incorporated herein by reference.
10 */
11
12 #include "ef100_nic.h"
13 #include "efx_common.h"
14 #include "efx_channels.h"
15 #include "io.h"
16 #include "selftest.h"
17 #include "ef100_regs.h"
18 #include "mcdi.h"
19 #include "mcdi_pcol.h"
20 #include "mcdi_port_common.h"
21 #include "mcdi_functions.h"
22 #include "mcdi_filters.h"
23 #include "ef100_rx.h"
24 #include "ef100_tx.h"
25 #include "ef100_sriov.h"
26 #include "ef100_netdev.h"
27 #include "tc.h"
28 #include "mae.h"
29 #include "rx_common.h"
30
31 #define EF100_MAX_VIS 4096
32 #define EF100_NUM_MCDI_BUFFERS 1
33 #define MCDI_BUF_LEN (8 + MCDI_CTL_SDU_LEN_MAX)
34
35 #define EF100_RESET_PORT ((ETH_RESET_MAC | ETH_RESET_PHY) << ETH_RESET_SHARED_SHIFT)
36
37 /* MCDI
38 */
ef100_mcdi_buf(struct efx_nic * efx,u8 bufid,dma_addr_t * dma_addr)39 static u8 *ef100_mcdi_buf(struct efx_nic *efx, u8 bufid, dma_addr_t *dma_addr)
40 {
41 struct ef100_nic_data *nic_data = efx->nic_data;
42
43 if (dma_addr)
44 *dma_addr = nic_data->mcdi_buf.dma_addr +
45 bufid * ALIGN(MCDI_BUF_LEN, 256);
46 return nic_data->mcdi_buf.addr + bufid * ALIGN(MCDI_BUF_LEN, 256);
47 }
48
ef100_get_warm_boot_count(struct efx_nic * efx)49 static int ef100_get_warm_boot_count(struct efx_nic *efx)
50 {
51 efx_dword_t reg;
52
53 efx_readd(efx, ®, efx_reg(efx, ER_GZ_MC_SFT_STATUS));
54
55 if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) == 0xffffffff) {
56 netif_err(efx, hw, efx->net_dev, "Hardware unavailable\n");
57 efx->state = STATE_DISABLED;
58 return -ENETDOWN;
59 } else {
60 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
61 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
62 }
63 }
64
ef100_mcdi_request(struct efx_nic * efx,const efx_dword_t * hdr,size_t hdr_len,const efx_dword_t * sdu,size_t sdu_len)65 static void ef100_mcdi_request(struct efx_nic *efx,
66 const efx_dword_t *hdr, size_t hdr_len,
67 const efx_dword_t *sdu, size_t sdu_len)
68 {
69 dma_addr_t dma_addr;
70 u8 *pdu = ef100_mcdi_buf(efx, 0, &dma_addr);
71
72 memcpy(pdu, hdr, hdr_len);
73 memcpy(pdu + hdr_len, sdu, sdu_len);
74 wmb();
75
76 /* The hardware provides 'low' and 'high' (doorbell) registers
77 * for passing the 64-bit address of an MCDI request to
78 * firmware. However the dwords are swapped by firmware. The
79 * least significant bits of the doorbell are then 0 for all
80 * MCDI requests due to alignment.
81 */
82 _efx_writed(efx, cpu_to_le32((u64)dma_addr >> 32), efx_reg(efx, ER_GZ_MC_DB_LWRD));
83 _efx_writed(efx, cpu_to_le32((u32)dma_addr), efx_reg(efx, ER_GZ_MC_DB_HWRD));
84 }
85
ef100_mcdi_poll_response(struct efx_nic * efx)86 static bool ef100_mcdi_poll_response(struct efx_nic *efx)
87 {
88 const efx_dword_t hdr =
89 *(const efx_dword_t *)(ef100_mcdi_buf(efx, 0, NULL));
90
91 rmb();
92 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
93 }
94
ef100_mcdi_read_response(struct efx_nic * efx,efx_dword_t * outbuf,size_t offset,size_t outlen)95 static void ef100_mcdi_read_response(struct efx_nic *efx,
96 efx_dword_t *outbuf, size_t offset,
97 size_t outlen)
98 {
99 const u8 *pdu = ef100_mcdi_buf(efx, 0, NULL);
100
101 memcpy(outbuf, pdu + offset, outlen);
102 }
103
ef100_mcdi_poll_reboot(struct efx_nic * efx)104 static int ef100_mcdi_poll_reboot(struct efx_nic *efx)
105 {
106 struct ef100_nic_data *nic_data = efx->nic_data;
107 int rc;
108
109 rc = ef100_get_warm_boot_count(efx);
110 if (rc < 0) {
111 /* The firmware is presumably in the process of
112 * rebooting. However, we are supposed to report each
113 * reboot just once, so we must only do that once we
114 * can read and store the updated warm boot count.
115 */
116 return 0;
117 }
118
119 if (rc == nic_data->warm_boot_count)
120 return 0;
121
122 nic_data->warm_boot_count = rc;
123
124 return -EIO;
125 }
126
ef100_mcdi_reboot_detected(struct efx_nic * efx)127 static void ef100_mcdi_reboot_detected(struct efx_nic *efx)
128 {
129 }
130
131 /* MCDI calls
132 */
ef100_get_mac_address(struct efx_nic * efx,u8 * mac_address,int client_handle,bool empty_ok)133 int ef100_get_mac_address(struct efx_nic *efx, u8 *mac_address,
134 int client_handle, bool empty_ok)
135 {
136 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LEN(1));
137 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_LEN);
138 size_t outlen;
139 int rc;
140
141 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
142 MCDI_SET_DWORD(inbuf, GET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE,
143 client_handle);
144
145 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLIENT_MAC_ADDRESSES, inbuf,
146 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
147 if (rc)
148 return rc;
149
150 if (outlen >= MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LEN(1)) {
151 ether_addr_copy(mac_address,
152 MCDI_PTR(outbuf, GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS));
153 } else if (empty_ok) {
154 pci_warn(efx->pci_dev,
155 "No MAC address provisioned for client ID %#x.\n",
156 client_handle);
157 eth_zero_addr(mac_address);
158 } else {
159 return -ENOENT;
160 }
161 return 0;
162 }
163
efx_ef100_init_datapath_caps(struct efx_nic * efx)164 int efx_ef100_init_datapath_caps(struct efx_nic *efx)
165 {
166 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V7_OUT_LEN);
167 struct ef100_nic_data *nic_data = efx->nic_data;
168 u8 vi_window_mode;
169 size_t outlen;
170 int rc;
171
172 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
173
174 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
175 outbuf, sizeof(outbuf), &outlen);
176 if (rc)
177 return rc;
178 if (outlen < MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) {
179 netif_err(efx, drv, efx->net_dev,
180 "unable to read datapath firmware capabilities\n");
181 return -EIO;
182 }
183
184 nic_data->datapath_caps = MCDI_DWORD(outbuf,
185 GET_CAPABILITIES_OUT_FLAGS1);
186 nic_data->datapath_caps2 = MCDI_DWORD(outbuf,
187 GET_CAPABILITIES_V2_OUT_FLAGS2);
188 if (outlen < MC_CMD_GET_CAPABILITIES_V7_OUT_LEN)
189 nic_data->datapath_caps3 = 0;
190 else
191 nic_data->datapath_caps3 = MCDI_DWORD(outbuf,
192 GET_CAPABILITIES_V7_OUT_FLAGS3);
193
194 vi_window_mode = MCDI_BYTE(outbuf,
195 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE);
196 rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode);
197 if (rc)
198 return rc;
199
200 if (efx_ef100_has_cap(nic_data->datapath_caps2, TX_TSO_V3)) {
201 struct net_device *net_dev = efx->net_dev;
202 netdev_features_t tso = NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_PARTIAL |
203 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM |
204 NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM;
205
206 net_dev->features |= tso;
207 net_dev->hw_features |= tso;
208 net_dev->hw_enc_features |= tso;
209 /* EF100 HW can only offload outer checksums if they are UDP,
210 * so for GRE_CSUM we have to use GSO_PARTIAL.
211 */
212 net_dev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
213 }
214 efx->num_mac_stats = MCDI_WORD(outbuf,
215 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS);
216 netif_dbg(efx, probe, efx->net_dev,
217 "firmware reports num_mac_stats = %u\n",
218 efx->num_mac_stats);
219 return 0;
220 }
221
222 /* Event handling
223 */
ef100_ev_probe(struct efx_channel * channel)224 static int ef100_ev_probe(struct efx_channel *channel)
225 {
226 /* Allocate an extra descriptor for the QMDA status completion entry */
227 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
228 (channel->eventq_mask + 2) *
229 sizeof(efx_qword_t),
230 GFP_KERNEL);
231 }
232
ef100_ev_init(struct efx_channel * channel)233 static int ef100_ev_init(struct efx_channel *channel)
234 {
235 struct ef100_nic_data *nic_data = channel->efx->nic_data;
236
237 /* initial phase is 0 */
238 clear_bit(channel->channel, nic_data->evq_phases);
239
240 return efx_mcdi_ev_init(channel, false, false);
241 }
242
ef100_ev_read_ack(struct efx_channel * channel)243 static void ef100_ev_read_ack(struct efx_channel *channel)
244 {
245 efx_dword_t evq_prime;
246
247 EFX_POPULATE_DWORD_2(evq_prime,
248 ERF_GZ_EVQ_ID, channel->channel,
249 ERF_GZ_IDX, channel->eventq_read_ptr &
250 channel->eventq_mask);
251
252 efx_writed(channel->efx, &evq_prime,
253 efx_reg(channel->efx, ER_GZ_EVQ_INT_PRIME));
254 }
255
ef100_ev_process(struct efx_channel * channel,int quota)256 static int ef100_ev_process(struct efx_channel *channel, int quota)
257 {
258 struct efx_nic *efx = channel->efx;
259 struct ef100_nic_data *nic_data;
260 bool evq_phase, old_evq_phase;
261 unsigned int read_ptr;
262 efx_qword_t *p_event;
263 int spent = 0;
264 bool ev_phase;
265 int ev_type;
266
267 if (unlikely(!channel->enabled))
268 return 0;
269
270 nic_data = efx->nic_data;
271 evq_phase = test_bit(channel->channel, nic_data->evq_phases);
272 old_evq_phase = evq_phase;
273 read_ptr = channel->eventq_read_ptr;
274 BUILD_BUG_ON(ESF_GZ_EV_RXPKTS_PHASE_LBN != ESF_GZ_EV_TXCMPL_PHASE_LBN);
275
276 while (spent < quota) {
277 p_event = efx_event(channel, read_ptr);
278
279 ev_phase = !!EFX_QWORD_FIELD(*p_event, ESF_GZ_EV_RXPKTS_PHASE);
280 if (ev_phase != evq_phase)
281 break;
282
283 netif_vdbg(efx, drv, efx->net_dev,
284 "processing event on %d " EFX_QWORD_FMT "\n",
285 channel->channel, EFX_QWORD_VAL(*p_event));
286
287 ev_type = EFX_QWORD_FIELD(*p_event, ESF_GZ_E_TYPE);
288
289 switch (ev_type) {
290 case ESE_GZ_EF100_EV_RX_PKTS:
291 efx_ef100_ev_rx(channel, p_event);
292 ++spent;
293 break;
294 case ESE_GZ_EF100_EV_MCDI:
295 efx_mcdi_process_event(channel, p_event);
296 break;
297 case ESE_GZ_EF100_EV_TX_COMPLETION:
298 ef100_ev_tx(channel, p_event);
299 break;
300 case ESE_GZ_EF100_EV_DRIVER:
301 netif_info(efx, drv, efx->net_dev,
302 "Driver initiated event " EFX_QWORD_FMT "\n",
303 EFX_QWORD_VAL(*p_event));
304 break;
305 default:
306 netif_info(efx, drv, efx->net_dev,
307 "Unhandled event " EFX_QWORD_FMT "\n",
308 EFX_QWORD_VAL(*p_event));
309 }
310
311 ++read_ptr;
312 if ((read_ptr & channel->eventq_mask) == 0)
313 evq_phase = !evq_phase;
314 }
315
316 channel->eventq_read_ptr = read_ptr;
317 if (evq_phase != old_evq_phase)
318 change_bit(channel->channel, nic_data->evq_phases);
319
320 return spent;
321 }
322
ef100_msi_interrupt(int irq,void * dev_id)323 static irqreturn_t ef100_msi_interrupt(int irq, void *dev_id)
324 {
325 struct efx_msi_context *context = dev_id;
326 struct efx_nic *efx = context->efx;
327
328 netif_vdbg(efx, intr, efx->net_dev,
329 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
330
331 if (likely(READ_ONCE(efx->irq_soft_enabled))) {
332 /* Note test interrupts */
333 if (context->index == efx->irq_level)
334 efx->last_irq_cpu = raw_smp_processor_id();
335
336 /* Schedule processing of the channel */
337 efx_schedule_channel_irq(efx->channel[context->index]);
338 }
339
340 return IRQ_HANDLED;
341 }
342
ef100_phy_probe(struct efx_nic * efx)343 int ef100_phy_probe(struct efx_nic *efx)
344 {
345 struct efx_mcdi_phy_data *phy_data;
346 int rc;
347
348 /* Probe for the PHY */
349 efx->phy_data = kzalloc(sizeof(struct efx_mcdi_phy_data), GFP_KERNEL);
350 if (!efx->phy_data)
351 return -ENOMEM;
352
353 rc = efx_mcdi_get_phy_cfg(efx, efx->phy_data);
354 if (rc)
355 return rc;
356
357 /* Populate driver and ethtool settings */
358 phy_data = efx->phy_data;
359 mcdi_to_ethtool_linkset(phy_data->media, phy_data->supported_cap,
360 efx->link_advertising);
361 efx->fec_config = mcdi_fec_caps_to_ethtool(phy_data->supported_cap,
362 false);
363
364 /* Default to Autonegotiated flow control if the PHY supports it */
365 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
366 if (phy_data->supported_cap & (1 << MC_CMD_PHY_CAP_AN_LBN))
367 efx->wanted_fc |= EFX_FC_AUTO;
368 efx_link_set_wanted_fc(efx, efx->wanted_fc);
369
370 /* Push settings to the PHY. Failure is not fatal, the user can try to
371 * fix it using ethtool.
372 */
373 rc = efx_mcdi_port_reconfigure(efx);
374 if (rc && rc != -EPERM)
375 netif_warn(efx, drv, efx->net_dev,
376 "could not initialise PHY settings\n");
377
378 return 0;
379 }
380
ef100_filter_table_probe(struct efx_nic * efx)381 int ef100_filter_table_probe(struct efx_nic *efx)
382 {
383 return efx_mcdi_filter_table_probe(efx, true);
384 }
385
ef100_filter_table_up(struct efx_nic * efx)386 static int ef100_filter_table_up(struct efx_nic *efx)
387 {
388 int rc;
389
390 down_write(&efx->filter_sem);
391 rc = efx_mcdi_filter_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
392 if (rc)
393 goto fail_unspec;
394
395 rc = efx_mcdi_filter_add_vlan(efx, 0);
396 if (rc)
397 goto fail_vlan0;
398 /* Drop the lock: we've finished altering table existence, and
399 * filter insertion will need to take the lock for read.
400 */
401 up_write(&efx->filter_sem);
402 if (IS_ENABLED(CONFIG_SFC_SRIOV))
403 rc = efx_tc_insert_rep_filters(efx);
404
405 /* Rep filter failure is nonfatal */
406 if (rc)
407 netif_warn(efx, drv, efx->net_dev,
408 "Failed to insert representor filters, rc %d\n",
409 rc);
410 return 0;
411
412 fail_vlan0:
413 efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC);
414 fail_unspec:
415 efx_mcdi_filter_table_down(efx);
416 up_write(&efx->filter_sem);
417 return rc;
418 }
419
ef100_filter_table_down(struct efx_nic * efx)420 static void ef100_filter_table_down(struct efx_nic *efx)
421 {
422 if (IS_ENABLED(CONFIG_SFC_SRIOV))
423 efx_tc_remove_rep_filters(efx);
424 down_write(&efx->filter_sem);
425 efx_mcdi_filter_del_vlan(efx, 0);
426 efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC);
427 efx_mcdi_filter_table_down(efx);
428 up_write(&efx->filter_sem);
429 }
430
431 /* Other
432 */
ef100_reconfigure_mac(struct efx_nic * efx,bool mtu_only)433 static int ef100_reconfigure_mac(struct efx_nic *efx, bool mtu_only)
434 {
435 WARN_ON(!mutex_is_locked(&efx->mac_lock));
436
437 efx_mcdi_filter_sync_rx_mode(efx);
438
439 if (mtu_only && efx_has_cap(efx, SET_MAC_ENHANCED))
440 return efx_mcdi_set_mtu(efx);
441 return efx_mcdi_set_mac(efx);
442 }
443
ef100_map_reset_reason(enum reset_type reason)444 static enum reset_type ef100_map_reset_reason(enum reset_type reason)
445 {
446 if (reason == RESET_TYPE_TX_WATCHDOG)
447 return reason;
448 return RESET_TYPE_DISABLE;
449 }
450
ef100_map_reset_flags(u32 * flags)451 static int ef100_map_reset_flags(u32 *flags)
452 {
453 /* Only perform a RESET_TYPE_ALL because we don't support MC_REBOOTs */
454 if ((*flags & EF100_RESET_PORT)) {
455 *flags &= ~EF100_RESET_PORT;
456 return RESET_TYPE_ALL;
457 }
458 if (*flags & ETH_RESET_MGMT) {
459 *flags &= ~ETH_RESET_MGMT;
460 return RESET_TYPE_DISABLE;
461 }
462
463 return -EINVAL;
464 }
465
ef100_reset(struct efx_nic * efx,enum reset_type reset_type)466 static int ef100_reset(struct efx_nic *efx, enum reset_type reset_type)
467 {
468 int rc;
469
470 dev_close(efx->net_dev);
471
472 if (reset_type == RESET_TYPE_TX_WATCHDOG) {
473 netif_device_attach(efx->net_dev);
474 __clear_bit(reset_type, &efx->reset_pending);
475 rc = dev_open(efx->net_dev, NULL);
476 } else if (reset_type == RESET_TYPE_ALL) {
477 rc = efx_mcdi_reset(efx, reset_type);
478 if (rc)
479 return rc;
480
481 netif_device_attach(efx->net_dev);
482
483 rc = dev_open(efx->net_dev, NULL);
484 } else {
485 rc = 1; /* Leave the device closed */
486 }
487 return rc;
488 }
489
ef100_common_stat_mask(unsigned long * mask)490 static void ef100_common_stat_mask(unsigned long *mask)
491 {
492 __set_bit(EF100_STAT_port_rx_packets, mask);
493 __set_bit(EF100_STAT_port_tx_packets, mask);
494 __set_bit(EF100_STAT_port_rx_bytes, mask);
495 __set_bit(EF100_STAT_port_tx_bytes, mask);
496 __set_bit(EF100_STAT_port_rx_multicast, mask);
497 __set_bit(EF100_STAT_port_rx_bad, mask);
498 __set_bit(EF100_STAT_port_rx_align_error, mask);
499 __set_bit(EF100_STAT_port_rx_overflow, mask);
500 }
501
ef100_ethtool_stat_mask(unsigned long * mask)502 static void ef100_ethtool_stat_mask(unsigned long *mask)
503 {
504 __set_bit(EF100_STAT_port_tx_pause, mask);
505 __set_bit(EF100_STAT_port_tx_unicast, mask);
506 __set_bit(EF100_STAT_port_tx_multicast, mask);
507 __set_bit(EF100_STAT_port_tx_broadcast, mask);
508 __set_bit(EF100_STAT_port_tx_lt64, mask);
509 __set_bit(EF100_STAT_port_tx_64, mask);
510 __set_bit(EF100_STAT_port_tx_65_to_127, mask);
511 __set_bit(EF100_STAT_port_tx_128_to_255, mask);
512 __set_bit(EF100_STAT_port_tx_256_to_511, mask);
513 __set_bit(EF100_STAT_port_tx_512_to_1023, mask);
514 __set_bit(EF100_STAT_port_tx_1024_to_15xx, mask);
515 __set_bit(EF100_STAT_port_tx_15xx_to_jumbo, mask);
516 __set_bit(EF100_STAT_port_rx_good, mask);
517 __set_bit(EF100_STAT_port_rx_pause, mask);
518 __set_bit(EF100_STAT_port_rx_unicast, mask);
519 __set_bit(EF100_STAT_port_rx_broadcast, mask);
520 __set_bit(EF100_STAT_port_rx_lt64, mask);
521 __set_bit(EF100_STAT_port_rx_64, mask);
522 __set_bit(EF100_STAT_port_rx_65_to_127, mask);
523 __set_bit(EF100_STAT_port_rx_128_to_255, mask);
524 __set_bit(EF100_STAT_port_rx_256_to_511, mask);
525 __set_bit(EF100_STAT_port_rx_512_to_1023, mask);
526 __set_bit(EF100_STAT_port_rx_1024_to_15xx, mask);
527 __set_bit(EF100_STAT_port_rx_15xx_to_jumbo, mask);
528 __set_bit(EF100_STAT_port_rx_gtjumbo, mask);
529 __set_bit(EF100_STAT_port_rx_bad_gtjumbo, mask);
530 __set_bit(EF100_STAT_port_rx_length_error, mask);
531 __set_bit(EF100_STAT_port_rx_nodesc_drops, mask);
532 __set_bit(GENERIC_STAT_rx_nodesc_trunc, mask);
533 __set_bit(GENERIC_STAT_rx_noskb_drops, mask);
534 }
535
536 #define EF100_DMA_STAT(ext_name, mcdi_name) \
537 [EF100_STAT_ ## ext_name] = \
538 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
539
540 static const struct efx_hw_stat_desc ef100_stat_desc[EF100_STAT_COUNT] = {
541 EF100_DMA_STAT(port_tx_bytes, TX_BYTES),
542 EF100_DMA_STAT(port_tx_packets, TX_PKTS),
543 EF100_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
544 EF100_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
545 EF100_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
546 EF100_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
547 EF100_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
548 EF100_DMA_STAT(port_tx_64, TX_64_PKTS),
549 EF100_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
550 EF100_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
551 EF100_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
552 EF100_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
553 EF100_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
554 EF100_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
555 EF100_DMA_STAT(port_rx_bytes, RX_BYTES),
556 EF100_DMA_STAT(port_rx_packets, RX_PKTS),
557 EF100_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
558 EF100_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
559 EF100_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
560 EF100_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
561 EF100_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
562 EF100_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
563 EF100_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
564 EF100_DMA_STAT(port_rx_64, RX_64_PKTS),
565 EF100_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
566 EF100_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
567 EF100_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
568 EF100_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
569 EF100_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
570 EF100_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
571 EF100_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
572 EF100_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
573 EF100_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
574 EF100_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
575 EF100_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
576 EF100_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
577 EFX_GENERIC_SW_STAT(rx_nodesc_trunc),
578 EFX_GENERIC_SW_STAT(rx_noskb_drops),
579 };
580
ef100_describe_stats(struct efx_nic * efx,u8 * names)581 static size_t ef100_describe_stats(struct efx_nic *efx, u8 *names)
582 {
583 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
584
585 ef100_ethtool_stat_mask(mask);
586 return efx_nic_describe_stats(ef100_stat_desc, EF100_STAT_COUNT,
587 mask, names);
588 }
589
ef100_update_stats_common(struct efx_nic * efx,u64 * full_stats,struct rtnl_link_stats64 * core_stats)590 static size_t ef100_update_stats_common(struct efx_nic *efx, u64 *full_stats,
591 struct rtnl_link_stats64 *core_stats)
592 {
593 struct ef100_nic_data *nic_data = efx->nic_data;
594 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
595 size_t stats_count = 0, index;
596 u64 *stats = nic_data->stats;
597
598 ef100_ethtool_stat_mask(mask);
599
600 if (full_stats) {
601 for_each_set_bit(index, mask, EF100_STAT_COUNT) {
602 if (ef100_stat_desc[index].name) {
603 *full_stats++ = stats[index];
604 ++stats_count;
605 }
606 }
607 }
608
609 if (!core_stats)
610 return stats_count;
611
612 core_stats->rx_packets = stats[EF100_STAT_port_rx_packets];
613 core_stats->tx_packets = stats[EF100_STAT_port_tx_packets];
614 core_stats->rx_bytes = stats[EF100_STAT_port_rx_bytes];
615 core_stats->tx_bytes = stats[EF100_STAT_port_tx_bytes];
616 core_stats->rx_dropped = stats[EF100_STAT_port_rx_nodesc_drops] +
617 stats[GENERIC_STAT_rx_nodesc_trunc] +
618 stats[GENERIC_STAT_rx_noskb_drops];
619 core_stats->multicast = stats[EF100_STAT_port_rx_multicast];
620 core_stats->rx_length_errors =
621 stats[EF100_STAT_port_rx_gtjumbo] +
622 stats[EF100_STAT_port_rx_length_error];
623 core_stats->rx_crc_errors = stats[EF100_STAT_port_rx_bad];
624 core_stats->rx_frame_errors =
625 stats[EF100_STAT_port_rx_align_error];
626 core_stats->rx_fifo_errors = stats[EF100_STAT_port_rx_overflow];
627 core_stats->rx_errors = (core_stats->rx_length_errors +
628 core_stats->rx_crc_errors +
629 core_stats->rx_frame_errors);
630
631 return stats_count;
632 }
633
ef100_update_stats(struct efx_nic * efx,u64 * full_stats,struct rtnl_link_stats64 * core_stats)634 static size_t ef100_update_stats(struct efx_nic *efx,
635 u64 *full_stats,
636 struct rtnl_link_stats64 *core_stats)
637 {
638 __le64 *mc_stats = kmalloc(array_size(efx->num_mac_stats, sizeof(__le64)), GFP_ATOMIC);
639 struct ef100_nic_data *nic_data = efx->nic_data;
640 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {};
641 u64 *stats = nic_data->stats;
642
643 ef100_common_stat_mask(mask);
644 ef100_ethtool_stat_mask(mask);
645
646 if (!mc_stats)
647 return 0;
648
649 efx_nic_copy_stats(efx, mc_stats);
650 efx_nic_update_stats(ef100_stat_desc, EF100_STAT_COUNT, mask,
651 stats, mc_stats, false);
652
653 kfree(mc_stats);
654
655 return ef100_update_stats_common(efx, full_stats, core_stats);
656 }
657
efx_ef100_get_phys_port_id(struct efx_nic * efx,struct netdev_phys_item_id * ppid)658 static int efx_ef100_get_phys_port_id(struct efx_nic *efx,
659 struct netdev_phys_item_id *ppid)
660 {
661 struct ef100_nic_data *nic_data = efx->nic_data;
662
663 if (!is_valid_ether_addr(nic_data->port_id))
664 return -EOPNOTSUPP;
665
666 ppid->id_len = ETH_ALEN;
667 memcpy(ppid->id, nic_data->port_id, ppid->id_len);
668
669 return 0;
670 }
671
efx_ef100_irq_test_generate(struct efx_nic * efx)672 static int efx_ef100_irq_test_generate(struct efx_nic *efx)
673 {
674 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
675
676 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
677
678 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
679 return efx_mcdi_rpc_quiet(efx, MC_CMD_TRIGGER_INTERRUPT,
680 inbuf, sizeof(inbuf), NULL, 0, NULL);
681 }
682
683 #define EFX_EF100_TEST 1
684
efx_ef100_ev_test_generate(struct efx_channel * channel)685 static void efx_ef100_ev_test_generate(struct efx_channel *channel)
686 {
687 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
688 struct efx_nic *efx = channel->efx;
689 efx_qword_t event;
690 int rc;
691
692 EFX_POPULATE_QWORD_2(event,
693 ESF_GZ_E_TYPE, ESE_GZ_EF100_EV_DRIVER,
694 ESF_GZ_DRIVER_DATA, EFX_EF100_TEST);
695
696 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
697
698 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
699 * already swapped the data to little-endian order.
700 */
701 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
702 sizeof(efx_qword_t));
703
704 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
705 NULL, 0, NULL);
706 if (rc && (rc != -ENETDOWN))
707 goto fail;
708
709 return;
710
711 fail:
712 WARN_ON(true);
713 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
714 }
715
ef100_check_caps(const struct efx_nic * efx,u8 flag,u32 offset)716 static unsigned int ef100_check_caps(const struct efx_nic *efx,
717 u8 flag, u32 offset)
718 {
719 const struct ef100_nic_data *nic_data = efx->nic_data;
720
721 switch (offset) {
722 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST:
723 return nic_data->datapath_caps & BIT_ULL(flag);
724 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_OFST:
725 return nic_data->datapath_caps2 & BIT_ULL(flag);
726 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_OFST:
727 return nic_data->datapath_caps3 & BIT_ULL(flag);
728 default:
729 return 0;
730 }
731 }
732
efx_ef100_recycle_ring_size(const struct efx_nic * efx)733 static unsigned int efx_ef100_recycle_ring_size(const struct efx_nic *efx)
734 {
735 /* Maximum link speed for Riverhead is 100G */
736 return 10 * EFX_RECYCLE_RING_SIZE_10G;
737 }
738
efx_ef100_get_base_mport(struct efx_nic * efx)739 static int efx_ef100_get_base_mport(struct efx_nic *efx)
740 {
741 struct ef100_nic_data *nic_data = efx->nic_data;
742 u32 selector, id;
743 int rc;
744
745 /* Construct mport selector for "physical network port" */
746 efx_mae_mport_wire(efx, &selector);
747 /* Look up actual mport ID */
748 rc = efx_mae_fw_lookup_mport(efx, selector, &id);
749 if (rc)
750 return rc;
751 /* The ID should always fit in 16 bits, because that's how wide the
752 * corresponding fields in the RX prefix & TX override descriptor are
753 */
754 if (id >> 16)
755 netif_warn(efx, probe, efx->net_dev, "Bad base m-port id %#x\n",
756 id);
757 nic_data->base_mport = id;
758 nic_data->have_mport = true;
759
760 /* Construct mport selector for "calling PF" */
761 efx_mae_mport_uplink(efx, &selector);
762 /* Look up actual mport ID */
763 rc = efx_mae_fw_lookup_mport(efx, selector, &id);
764 if (rc)
765 return rc;
766 if (id >> 16)
767 netif_warn(efx, probe, efx->net_dev, "Bad own m-port id %#x\n",
768 id);
769 nic_data->own_mport = id;
770 nic_data->have_own_mport = true;
771
772 return 0;
773 }
774
compare_versions(const char * a,const char * b)775 static int compare_versions(const char *a, const char *b)
776 {
777 int a_major, a_minor, a_point, a_patch;
778 int b_major, b_minor, b_point, b_patch;
779 int a_matched, b_matched;
780
781 a_matched = sscanf(a, "%d.%d.%d.%d", &a_major, &a_minor, &a_point, &a_patch);
782 b_matched = sscanf(b, "%d.%d.%d.%d", &b_major, &b_minor, &b_point, &b_patch);
783
784 if (a_matched == 4 && b_matched != 4)
785 return +1;
786
787 if (a_matched != 4 && b_matched == 4)
788 return -1;
789
790 if (a_matched != 4 && b_matched != 4)
791 return 0;
792
793 if (a_major != b_major)
794 return a_major - b_major;
795
796 if (a_minor != b_minor)
797 return a_minor - b_minor;
798
799 if (a_point != b_point)
800 return a_point - b_point;
801
802 return a_patch - b_patch;
803 }
804
805 enum ef100_tlv_state_machine {
806 EF100_TLV_TYPE,
807 EF100_TLV_TYPE_CONT,
808 EF100_TLV_LENGTH,
809 EF100_TLV_VALUE
810 };
811
812 struct ef100_tlv_state {
813 enum ef100_tlv_state_machine state;
814 u64 value;
815 u32 value_offset;
816 u16 type;
817 u8 len;
818 };
819
ef100_tlv_feed(struct ef100_tlv_state * state,u8 byte)820 static int ef100_tlv_feed(struct ef100_tlv_state *state, u8 byte)
821 {
822 switch (state->state) {
823 case EF100_TLV_TYPE:
824 state->type = byte & 0x7f;
825 state->state = (byte & 0x80) ? EF100_TLV_TYPE_CONT
826 : EF100_TLV_LENGTH;
827 /* Clear ready to read in a new entry */
828 state->value = 0;
829 state->value_offset = 0;
830 return 0;
831 case EF100_TLV_TYPE_CONT:
832 state->type |= byte << 7;
833 state->state = EF100_TLV_LENGTH;
834 return 0;
835 case EF100_TLV_LENGTH:
836 state->len = byte;
837 /* We only handle TLVs that fit in a u64 */
838 if (state->len > sizeof(state->value))
839 return -EOPNOTSUPP;
840 /* len may be zero, implying a value of zero */
841 state->state = state->len ? EF100_TLV_VALUE : EF100_TLV_TYPE;
842 return 0;
843 case EF100_TLV_VALUE:
844 state->value |= ((u64)byte) << (state->value_offset * 8);
845 state->value_offset++;
846 if (state->value_offset >= state->len)
847 state->state = EF100_TLV_TYPE;
848 return 0;
849 default: /* state machine error, can't happen */
850 WARN_ON_ONCE(1);
851 return -EIO;
852 }
853 }
854
ef100_process_design_param(struct efx_nic * efx,const struct ef100_tlv_state * reader)855 static int ef100_process_design_param(struct efx_nic *efx,
856 const struct ef100_tlv_state *reader)
857 {
858 struct ef100_nic_data *nic_data = efx->nic_data;
859
860 switch (reader->type) {
861 case ESE_EF100_DP_GZ_PAD: /* padding, skip it */
862 return 0;
863 case ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS:
864 /* Driver doesn't support timestamping yet, so we don't care */
865 return 0;
866 case ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS:
867 /* Driver doesn't support unsolicited-event credits yet, so
868 * we don't care
869 */
870 return 0;
871 case ESE_EF100_DP_GZ_NMMU_GROUP_SIZE:
872 /* Driver doesn't manage the NMMU (so we don't care) */
873 return 0;
874 case ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS:
875 /* Driver uses CHECKSUM_COMPLETE, so we don't care about
876 * protocol checksum validation
877 */
878 return 0;
879 case ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN:
880 nic_data->tso_max_hdr_len = min_t(u64, reader->value, 0xffff);
881 return 0;
882 case ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS:
883 /* We always put HDR_NUM_SEGS=1 in our TSO descriptors */
884 if (!reader->value) {
885 netif_err(efx, probe, efx->net_dev,
886 "TSO_MAX_HDR_NUM_SEGS < 1\n");
887 return -EOPNOTSUPP;
888 }
889 return 0;
890 case ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY:
891 case ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY:
892 /* Our TXQ and RXQ sizes are always power-of-two and thus divisible by
893 * EFX_MIN_DMAQ_SIZE, so we just need to check that
894 * EFX_MIN_DMAQ_SIZE is divisible by GRANULARITY.
895 * This is very unlikely to fail.
896 */
897 if (!reader->value || reader->value > EFX_MIN_DMAQ_SIZE ||
898 EFX_MIN_DMAQ_SIZE % (u32)reader->value) {
899 netif_err(efx, probe, efx->net_dev,
900 "%s size granularity is %llu, can't guarantee safety\n",
901 reader->type == ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY ? "RXQ" : "TXQ",
902 reader->value);
903 return -EOPNOTSUPP;
904 }
905 return 0;
906 case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN:
907 nic_data->tso_max_payload_len = min_t(u64, reader->value,
908 GSO_LEGACY_MAX_SIZE);
909 netif_set_tso_max_size(efx->net_dev,
910 nic_data->tso_max_payload_len);
911 return 0;
912 case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS:
913 nic_data->tso_max_payload_num_segs = min_t(u64, reader->value, 0xffff);
914 netif_set_tso_max_segs(efx->net_dev,
915 nic_data->tso_max_payload_num_segs);
916 return 0;
917 case ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES:
918 nic_data->tso_max_frames = min_t(u64, reader->value, 0xffff);
919 return 0;
920 case ESE_EF100_DP_GZ_COMPAT:
921 if (reader->value) {
922 netif_err(efx, probe, efx->net_dev,
923 "DP_COMPAT has unknown bits %#llx, driver not compatible with this hw\n",
924 reader->value);
925 return -EOPNOTSUPP;
926 }
927 return 0;
928 case ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN:
929 /* Driver doesn't use mem2mem transfers */
930 return 0;
931 case ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS:
932 /* Driver doesn't currently use EVQ_TIMER */
933 return 0;
934 case ESE_EF100_DP_GZ_NMMU_PAGE_SIZES:
935 /* Driver doesn't manage the NMMU (so we don't care) */
936 return 0;
937 case ESE_EF100_DP_GZ_VI_STRIDES:
938 /* We never try to set the VI stride, and we don't rely on
939 * being able to find VIs past VI 0 until after we've learned
940 * the current stride from MC_CMD_GET_CAPABILITIES.
941 * So the value of this shouldn't matter.
942 */
943 if (reader->value != ESE_EF100_DP_GZ_VI_STRIDES_DEFAULT)
944 netif_dbg(efx, probe, efx->net_dev,
945 "NIC has other than default VI_STRIDES (mask "
946 "%#llx), early probing might use wrong one\n",
947 reader->value);
948 return 0;
949 case ESE_EF100_DP_GZ_RX_MAX_RUNT:
950 /* Driver doesn't look at L2_STATUS:LEN_ERR bit, so we don't
951 * care whether it indicates runt or overlength for any given
952 * packet, so we don't care about this parameter.
953 */
954 return 0;
955 default:
956 /* Host interface says "Drivers should ignore design parameters
957 * that they do not recognise."
958 */
959 netif_dbg(efx, probe, efx->net_dev,
960 "Ignoring unrecognised design parameter %u\n",
961 reader->type);
962 return 0;
963 }
964 }
965
ef100_check_design_params(struct efx_nic * efx)966 static int ef100_check_design_params(struct efx_nic *efx)
967 {
968 struct ef100_tlv_state reader = {};
969 u32 total_len, offset = 0;
970 efx_dword_t reg;
971 int rc = 0, i;
972 u32 data;
973
974 efx_readd(efx, ®, ER_GZ_PARAMS_TLV_LEN);
975 total_len = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
976 pci_dbg(efx->pci_dev, "%u bytes of design parameters\n", total_len);
977 while (offset < total_len) {
978 efx_readd(efx, ®, ER_GZ_PARAMS_TLV + offset);
979 data = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
980 for (i = 0; i < sizeof(data); i++) {
981 rc = ef100_tlv_feed(&reader, data);
982 /* Got a complete value? */
983 if (!rc && reader.state == EF100_TLV_TYPE)
984 rc = ef100_process_design_param(efx, &reader);
985 if (rc)
986 goto out;
987 data >>= 8;
988 offset++;
989 }
990 }
991 /* Check we didn't end halfway through a TLV entry, which could either
992 * mean that the TLV stream is truncated or just that it's corrupted
993 * and our state machine is out of sync.
994 */
995 if (reader.state != EF100_TLV_TYPE) {
996 if (reader.state == EF100_TLV_TYPE_CONT)
997 netif_err(efx, probe, efx->net_dev,
998 "truncated design parameter (incomplete type %u)\n",
999 reader.type);
1000 else
1001 netif_err(efx, probe, efx->net_dev,
1002 "truncated design parameter %u\n",
1003 reader.type);
1004 rc = -EIO;
1005 }
1006 out:
1007 return rc;
1008 }
1009
1010 /* NIC probe and remove
1011 */
ef100_probe_main(struct efx_nic * efx)1012 static int ef100_probe_main(struct efx_nic *efx)
1013 {
1014 unsigned int bar_size = resource_size(&efx->pci_dev->resource[efx->mem_bar]);
1015 struct ef100_nic_data *nic_data;
1016 char fw_version[32];
1017 u32 priv_mask = 0;
1018 int i, rc;
1019
1020 if (WARN_ON(bar_size == 0))
1021 return -EIO;
1022
1023 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
1024 if (!nic_data)
1025 return -ENOMEM;
1026 efx->nic_data = nic_data;
1027 nic_data->efx = efx;
1028 efx->max_vis = EF100_MAX_VIS;
1029
1030 /* Populate design-parameter defaults */
1031 nic_data->tso_max_hdr_len = ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN_DEFAULT;
1032 nic_data->tso_max_frames = ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES_DEFAULT;
1033 nic_data->tso_max_payload_num_segs = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS_DEFAULT;
1034 nic_data->tso_max_payload_len = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN_DEFAULT;
1035
1036 /* Read design parameters */
1037 rc = ef100_check_design_params(efx);
1038 if (rc) {
1039 pci_err(efx->pci_dev, "Unsupported design parameters\n");
1040 goto fail;
1041 }
1042
1043 /* we assume later that we can copy from this buffer in dwords */
1044 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
1045
1046 /* MCDI buffers must be 256 byte aligned. */
1047 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, MCDI_BUF_LEN,
1048 GFP_KERNEL);
1049 if (rc)
1050 goto fail;
1051
1052 /* Get the MC's warm boot count. In case it's rebooting right
1053 * now, be prepared to retry.
1054 */
1055 i = 0;
1056 for (;;) {
1057 rc = ef100_get_warm_boot_count(efx);
1058 if (rc >= 0)
1059 break;
1060 if (++i == 5)
1061 goto fail;
1062 ssleep(1);
1063 }
1064 nic_data->warm_boot_count = rc;
1065
1066 /* In case we're recovering from a crash (kexec), we want to
1067 * cancel any outstanding request by the previous user of this
1068 * function. We send a special message using the least
1069 * significant bits of the 'high' (doorbell) register.
1070 */
1071 _efx_writed(efx, cpu_to_le32(1), efx_reg(efx, ER_GZ_MC_DB_HWRD));
1072
1073 /* Post-IO section. */
1074
1075 rc = efx_mcdi_init(efx);
1076 if (rc)
1077 goto fail;
1078 /* Reset (most) configuration for this function */
1079 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
1080 if (rc)
1081 goto fail;
1082 /* Enable event logging */
1083 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
1084 if (rc)
1085 goto fail;
1086
1087 rc = efx_get_pf_index(efx, &nic_data->pf_index);
1088 if (rc)
1089 goto fail;
1090
1091 rc = efx_mcdi_port_get_number(efx);
1092 if (rc < 0)
1093 goto fail;
1094 efx->port_num = rc;
1095
1096 efx_mcdi_print_fwver(efx, fw_version, sizeof(fw_version));
1097 pci_dbg(efx->pci_dev, "Firmware version %s\n", fw_version);
1098
1099 rc = efx_mcdi_get_privilege_mask(efx, &priv_mask);
1100 if (rc) /* non-fatal, and priv_mask will still be 0 */
1101 pci_info(efx->pci_dev,
1102 "Failed to get privilege mask from FW, rc %d\n", rc);
1103 nic_data->grp_mae = !!(priv_mask & MC_CMD_PRIVILEGE_MASK_IN_GRP_MAE);
1104
1105 if (compare_versions(fw_version, "1.1.0.1000") < 0) {
1106 pci_info(efx->pci_dev, "Firmware uses old event descriptors\n");
1107 rc = -EINVAL;
1108 goto fail;
1109 }
1110
1111 if (efx_has_cap(efx, UNSOL_EV_CREDIT_SUPPORTED)) {
1112 pci_info(efx->pci_dev, "Firmware uses unsolicited-event credits\n");
1113 rc = -EINVAL;
1114 goto fail;
1115 }
1116
1117 return 0;
1118 fail:
1119 return rc;
1120 }
1121
1122 /* MCDI commands are related to the same device issuing them. This function
1123 * allows to do an MCDI command on behalf of another device, mainly PFs setting
1124 * things for VFs.
1125 */
efx_ef100_lookup_client_id(struct efx_nic * efx,efx_qword_t pciefn,u32 * id)1126 int efx_ef100_lookup_client_id(struct efx_nic *efx, efx_qword_t pciefn, u32 *id)
1127 {
1128 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLIENT_HANDLE_OUT_LEN);
1129 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_CLIENT_HANDLE_IN_LEN);
1130 u64 pciefn_flat = le64_to_cpu(pciefn.u64[0]);
1131 size_t outlen;
1132 int rc;
1133
1134 MCDI_SET_DWORD(inbuf, GET_CLIENT_HANDLE_IN_TYPE,
1135 MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_FUNC);
1136 MCDI_SET_QWORD(inbuf, GET_CLIENT_HANDLE_IN_FUNC,
1137 pciefn_flat);
1138
1139 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLIENT_HANDLE, inbuf, sizeof(inbuf),
1140 outbuf, sizeof(outbuf), &outlen);
1141 if (rc)
1142 return rc;
1143 if (outlen < sizeof(outbuf))
1144 return -EIO;
1145 *id = MCDI_DWORD(outbuf, GET_CLIENT_HANDLE_OUT_HANDLE);
1146 return 0;
1147 }
1148
ef100_probe_netdev_pf(struct efx_nic * efx)1149 int ef100_probe_netdev_pf(struct efx_nic *efx)
1150 {
1151 struct ef100_nic_data *nic_data = efx->nic_data;
1152 struct net_device *net_dev = efx->net_dev;
1153 int rc;
1154
1155 if (!IS_ENABLED(CONFIG_SFC_SRIOV) || !nic_data->grp_mae)
1156 return 0;
1157
1158 rc = efx_init_struct_tc(efx);
1159 if (rc)
1160 return rc;
1161
1162 rc = efx_ef100_get_base_mport(efx);
1163 if (rc) {
1164 netif_warn(efx, probe, net_dev,
1165 "Failed to probe base mport rc %d; representors will not function\n",
1166 rc);
1167 }
1168
1169 rc = efx_init_mae(efx);
1170 if (rc)
1171 netif_warn(efx, probe, net_dev,
1172 "Failed to init MAE rc %d; representors will not function\n",
1173 rc);
1174 else
1175 efx_ef100_init_reps(efx);
1176
1177 rc = efx_init_tc(efx);
1178 if (rc) {
1179 /* Either we don't have an MAE at all (i.e. legacy v-switching),
1180 * or we do but we failed to probe it. In the latter case, we
1181 * may not have set up default rules, in which case we won't be
1182 * able to pass any traffic. However, we don't fail the probe,
1183 * because the user might need to use the netdevice to apply
1184 * configuration changes to fix whatever's wrong with the MAE.
1185 */
1186 netif_warn(efx, probe, net_dev, "Failed to probe MAE rc %d\n",
1187 rc);
1188 } else {
1189 net_dev->features |= NETIF_F_HW_TC;
1190 efx->fixed_features |= NETIF_F_HW_TC;
1191 }
1192 return rc;
1193 }
1194
ef100_probe_vf(struct efx_nic * efx)1195 int ef100_probe_vf(struct efx_nic *efx)
1196 {
1197 return ef100_probe_main(efx);
1198 }
1199
ef100_remove(struct efx_nic * efx)1200 void ef100_remove(struct efx_nic *efx)
1201 {
1202 struct ef100_nic_data *nic_data = efx->nic_data;
1203
1204 if (IS_ENABLED(CONFIG_SFC_SRIOV) && efx->mae) {
1205 efx_ef100_fini_reps(efx);
1206 efx_fini_mae(efx);
1207 }
1208
1209 efx_mcdi_detach(efx);
1210 efx_mcdi_fini(efx);
1211 if (nic_data)
1212 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
1213 kfree(nic_data);
1214 efx->nic_data = NULL;
1215 }
1216
1217 /* NIC level access functions
1218 */
1219 #define EF100_OFFLOAD_FEATURES (NETIF_F_HW_CSUM | NETIF_F_RXCSUM | \
1220 NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_NTUPLE | \
1221 NETIF_F_RXHASH | NETIF_F_RXFCS | NETIF_F_TSO_ECN | NETIF_F_RXALL | \
1222 NETIF_F_HW_VLAN_CTAG_TX)
1223
1224 const struct efx_nic_type ef100_pf_nic_type = {
1225 .revision = EFX_REV_EF100,
1226 .is_vf = false,
1227 .probe = ef100_probe_main,
1228 .offload_features = EF100_OFFLOAD_FEATURES,
1229 .mcdi_max_ver = 2,
1230 .mcdi_request = ef100_mcdi_request,
1231 .mcdi_poll_response = ef100_mcdi_poll_response,
1232 .mcdi_read_response = ef100_mcdi_read_response,
1233 .mcdi_poll_reboot = ef100_mcdi_poll_reboot,
1234 .mcdi_reboot_detected = ef100_mcdi_reboot_detected,
1235 .irq_enable_master = efx_port_dummy_op_void,
1236 .irq_test_generate = efx_ef100_irq_test_generate,
1237 .irq_disable_non_ev = efx_port_dummy_op_void,
1238 .push_irq_moderation = efx_channel_dummy_op_void,
1239 .min_interrupt_mode = EFX_INT_MODE_MSIX,
1240 .map_reset_reason = ef100_map_reset_reason,
1241 .map_reset_flags = ef100_map_reset_flags,
1242 .reset = ef100_reset,
1243
1244 .check_caps = ef100_check_caps,
1245
1246 .ev_probe = ef100_ev_probe,
1247 .ev_init = ef100_ev_init,
1248 .ev_fini = efx_mcdi_ev_fini,
1249 .ev_remove = efx_mcdi_ev_remove,
1250 .irq_handle_msi = ef100_msi_interrupt,
1251 .ev_process = ef100_ev_process,
1252 .ev_read_ack = ef100_ev_read_ack,
1253 .ev_test_generate = efx_ef100_ev_test_generate,
1254 .tx_probe = ef100_tx_probe,
1255 .tx_init = ef100_tx_init,
1256 .tx_write = ef100_tx_write,
1257 .tx_enqueue = ef100_enqueue_skb,
1258 .rx_probe = efx_mcdi_rx_probe,
1259 .rx_init = efx_mcdi_rx_init,
1260 .rx_remove = efx_mcdi_rx_remove,
1261 .rx_write = ef100_rx_write,
1262 .rx_packet = __ef100_rx_packet,
1263 .rx_buf_hash_valid = ef100_rx_buf_hash_valid,
1264 .fini_dmaq = efx_fini_dmaq,
1265 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS,
1266 .filter_table_probe = ef100_filter_table_up,
1267 .filter_table_restore = efx_mcdi_filter_table_restore,
1268 .filter_table_remove = ef100_filter_table_down,
1269 .filter_insert = efx_mcdi_filter_insert,
1270 .filter_remove_safe = efx_mcdi_filter_remove_safe,
1271 .filter_get_safe = efx_mcdi_filter_get_safe,
1272 .filter_clear_rx = efx_mcdi_filter_clear_rx,
1273 .filter_count_rx_used = efx_mcdi_filter_count_rx_used,
1274 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit,
1275 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids,
1276 #ifdef CONFIG_RFS_ACCEL
1277 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one,
1278 #endif
1279
1280 .get_phys_port_id = efx_ef100_get_phys_port_id,
1281
1282 .rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN,
1283 .rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8,
1284 .rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8,
1285 .rx_hash_key_size = 40,
1286 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config,
1287 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config,
1288 .rx_push_rss_context_config = efx_mcdi_rx_push_rss_context_config,
1289 .rx_pull_rss_context_config = efx_mcdi_rx_pull_rss_context_config,
1290 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts,
1291 .rx_recycle_ring_size = efx_ef100_recycle_ring_size,
1292
1293 .reconfigure_mac = ef100_reconfigure_mac,
1294 .reconfigure_port = efx_mcdi_port_reconfigure,
1295 .test_nvram = efx_new_mcdi_nvram_test_all,
1296 .describe_stats = ef100_describe_stats,
1297 .start_stats = efx_mcdi_mac_start_stats,
1298 .update_stats = ef100_update_stats,
1299 .pull_stats = efx_mcdi_mac_pull_stats,
1300 .stop_stats = efx_mcdi_mac_stop_stats,
1301 .sriov_configure = IS_ENABLED(CONFIG_SFC_SRIOV) ?
1302 efx_ef100_sriov_configure : NULL,
1303
1304 /* Per-type bar/size configuration not used on ef100. Location of
1305 * registers is defined by extended capabilities.
1306 */
1307 .mem_bar = NULL,
1308 .mem_map_size = NULL,
1309
1310 };
1311
1312 const struct efx_nic_type ef100_vf_nic_type = {
1313 .revision = EFX_REV_EF100,
1314 .is_vf = true,
1315 .probe = ef100_probe_vf,
1316 .offload_features = EF100_OFFLOAD_FEATURES,
1317 .mcdi_max_ver = 2,
1318 .mcdi_request = ef100_mcdi_request,
1319 .mcdi_poll_response = ef100_mcdi_poll_response,
1320 .mcdi_read_response = ef100_mcdi_read_response,
1321 .mcdi_poll_reboot = ef100_mcdi_poll_reboot,
1322 .mcdi_reboot_detected = ef100_mcdi_reboot_detected,
1323 .irq_enable_master = efx_port_dummy_op_void,
1324 .irq_test_generate = efx_ef100_irq_test_generate,
1325 .irq_disable_non_ev = efx_port_dummy_op_void,
1326 .push_irq_moderation = efx_channel_dummy_op_void,
1327 .min_interrupt_mode = EFX_INT_MODE_MSIX,
1328 .map_reset_reason = ef100_map_reset_reason,
1329 .map_reset_flags = ef100_map_reset_flags,
1330 .reset = ef100_reset,
1331 .check_caps = ef100_check_caps,
1332 .ev_probe = ef100_ev_probe,
1333 .ev_init = ef100_ev_init,
1334 .ev_fini = efx_mcdi_ev_fini,
1335 .ev_remove = efx_mcdi_ev_remove,
1336 .irq_handle_msi = ef100_msi_interrupt,
1337 .ev_process = ef100_ev_process,
1338 .ev_read_ack = ef100_ev_read_ack,
1339 .ev_test_generate = efx_ef100_ev_test_generate,
1340 .tx_probe = ef100_tx_probe,
1341 .tx_init = ef100_tx_init,
1342 .tx_write = ef100_tx_write,
1343 .tx_enqueue = ef100_enqueue_skb,
1344 .rx_probe = efx_mcdi_rx_probe,
1345 .rx_init = efx_mcdi_rx_init,
1346 .rx_remove = efx_mcdi_rx_remove,
1347 .rx_write = ef100_rx_write,
1348 .rx_packet = __ef100_rx_packet,
1349 .rx_buf_hash_valid = ef100_rx_buf_hash_valid,
1350 .fini_dmaq = efx_fini_dmaq,
1351 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS,
1352 .filter_table_probe = ef100_filter_table_up,
1353 .filter_table_restore = efx_mcdi_filter_table_restore,
1354 .filter_table_remove = ef100_filter_table_down,
1355 .filter_insert = efx_mcdi_filter_insert,
1356 .filter_remove_safe = efx_mcdi_filter_remove_safe,
1357 .filter_get_safe = efx_mcdi_filter_get_safe,
1358 .filter_clear_rx = efx_mcdi_filter_clear_rx,
1359 .filter_count_rx_used = efx_mcdi_filter_count_rx_used,
1360 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit,
1361 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids,
1362 #ifdef CONFIG_RFS_ACCEL
1363 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one,
1364 #endif
1365
1366 .rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN,
1367 .rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8,
1368 .rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8,
1369 .rx_hash_key_size = 40,
1370 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config,
1371 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config,
1372 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts,
1373 .rx_recycle_ring_size = efx_ef100_recycle_ring_size,
1374
1375 .reconfigure_mac = ef100_reconfigure_mac,
1376 .test_nvram = efx_new_mcdi_nvram_test_all,
1377 .describe_stats = ef100_describe_stats,
1378 .start_stats = efx_mcdi_mac_start_stats,
1379 .update_stats = ef100_update_stats,
1380 .pull_stats = efx_mcdi_mac_pull_stats,
1381 .stop_stats = efx_mcdi_mac_stop_stats,
1382
1383 .mem_bar = NULL,
1384 .mem_map_size = NULL,
1385
1386 };
1387