1 /*
2  * Copyright 2012-14 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef DC_INTERFACE_H_
27 #define DC_INTERFACE_H_
28 
29 #include "dc_types.h"
30 #include "grph_object_defs.h"
31 #include "logger_types.h"
32 #if defined(CONFIG_DRM_AMD_DC_HDCP)
33 #include "hdcp_types.h"
34 #endif
35 #include "gpio_types.h"
36 #include "link_service_types.h"
37 #include "grph_object_ctrl_defs.h"
38 #include <inc/hw/opp.h>
39 
40 #include "inc/hw_sequencer.h"
41 #include "inc/compressor.h"
42 #include "inc/hw/dmcu.h"
43 #include "dml/display_mode_lib.h"
44 
45 /* forward declaration */
46 struct aux_payload;
47 struct set_config_cmd_payload;
48 struct dmub_notification;
49 
50 #define DC_VER "3.2.223"
51 
52 #define MAX_SURFACES 3
53 #define MAX_PLANES 6
54 #define MAX_STREAMS 6
55 #define MIN_VIEWPORT_SIZE 12
56 #define MAX_NUM_EDP 2
57 
58 /* Display Core Interfaces */
59 struct dc_versions {
60 	const char *dc_ver;
61 	struct dmcu_version dmcu_version;
62 };
63 
64 enum dp_protocol_version {
65 	DP_VERSION_1_4,
66 };
67 
68 enum dc_plane_type {
69 	DC_PLANE_TYPE_INVALID,
70 	DC_PLANE_TYPE_DCE_RGB,
71 	DC_PLANE_TYPE_DCE_UNDERLAY,
72 	DC_PLANE_TYPE_DCN_UNIVERSAL,
73 };
74 
75 // Sizes defined as multiples of 64KB
76 enum det_size {
77 	DET_SIZE_DEFAULT = 0,
78 	DET_SIZE_192KB = 3,
79 	DET_SIZE_256KB = 4,
80 	DET_SIZE_320KB = 5,
81 	DET_SIZE_384KB = 6
82 };
83 
84 
85 struct dc_plane_cap {
86 	enum dc_plane_type type;
87 	uint32_t blends_with_above : 1;
88 	uint32_t blends_with_below : 1;
89 	uint32_t per_pixel_alpha : 1;
90 	struct {
91 		uint32_t argb8888 : 1;
92 		uint32_t nv12 : 1;
93 		uint32_t fp16 : 1;
94 		uint32_t p010 : 1;
95 		uint32_t ayuv : 1;
96 	} pixel_format_support;
97 	// max upscaling factor x1000
98 	// upscaling factors are always >= 1
99 	// for example, 1080p -> 8K is 4.0, or 4000 raw value
100 	struct {
101 		uint32_t argb8888;
102 		uint32_t nv12;
103 		uint32_t fp16;
104 	} max_upscale_factor;
105 	// max downscale factor x1000
106 	// downscale factors are always <= 1
107 	// for example, 8K -> 1080p is 0.25, or 250 raw value
108 	struct {
109 		uint32_t argb8888;
110 		uint32_t nv12;
111 		uint32_t fp16;
112 	} max_downscale_factor;
113 	// minimal width/height
114 	uint32_t min_width;
115 	uint32_t min_height;
116 };
117 
118 /**
119  * DOC: color-management-caps
120  *
121  * **Color management caps (DPP and MPC)**
122  *
123  * Modules/color calculates various color operations which are translated to
124  * abstracted HW. DCE 5-12 had almost no important changes, but starting with
125  * DCN1, every new generation comes with fairly major differences in color
126  * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can
127  * decide mapping to HW block based on logical capabilities.
128  */
129 
130 /**
131  * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
132  * @srgb: RGB color space transfer func
133  * @bt2020: BT.2020 transfer func
134  * @gamma2_2: standard gamma
135  * @pq: perceptual quantizer transfer function
136  * @hlg: hybrid log–gamma transfer function
137  */
138 struct rom_curve_caps {
139 	uint16_t srgb : 1;
140 	uint16_t bt2020 : 1;
141 	uint16_t gamma2_2 : 1;
142 	uint16_t pq : 1;
143 	uint16_t hlg : 1;
144 };
145 
146 /**
147  * struct dpp_color_caps - color pipeline capabilities for display pipe and
148  * plane blocks
149  *
150  * @dcn_arch: all DCE generations treated the same
151  * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs,
152  * just plain 256-entry lookup
153  * @icsc: input color space conversion
154  * @dgam_ram: programmable degamma LUT
155  * @post_csc: post color space conversion, before gamut remap
156  * @gamma_corr: degamma correction
157  * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared
158  * with MPC by setting mpc:shared_3d_lut flag
159  * @ogam_ram: programmable out/blend gamma LUT
160  * @ocsc: output color space conversion
161  * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes
162  * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT
163  * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
164  *
165  * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order)
166  */
167 struct dpp_color_caps {
168 	uint16_t dcn_arch : 1;
169 	uint16_t input_lut_shared : 1;
170 	uint16_t icsc : 1;
171 	uint16_t dgam_ram : 1;
172 	uint16_t post_csc : 1;
173 	uint16_t gamma_corr : 1;
174 	uint16_t hw_3d_lut : 1;
175 	uint16_t ogam_ram : 1;
176 	uint16_t ocsc : 1;
177 	uint16_t dgam_rom_for_yuv : 1;
178 	struct rom_curve_caps dgam_rom_caps;
179 	struct rom_curve_caps ogam_rom_caps;
180 };
181 
182 /**
183  * struct mpc_color_caps - color pipeline capabilities for multiple pipe and
184  * plane combined blocks
185  *
186  * @gamut_remap: color transformation matrix
187  * @ogam_ram: programmable out gamma LUT
188  * @ocsc: output color space conversion matrix
189  * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT
190  * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single
191  * instance
192  * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
193  */
194 struct mpc_color_caps {
195 	uint16_t gamut_remap : 1;
196 	uint16_t ogam_ram : 1;
197 	uint16_t ocsc : 1;
198 	uint16_t num_3dluts : 3;
199 	uint16_t shared_3d_lut:1;
200 	struct rom_curve_caps ogam_rom_caps;
201 };
202 
203 /**
204  * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks
205  * @dpp: color pipes caps for DPP
206  * @mpc: color pipes caps for MPC
207  */
208 struct dc_color_caps {
209 	struct dpp_color_caps dpp;
210 	struct mpc_color_caps mpc;
211 };
212 
213 struct dc_dmub_caps {
214 	bool psr;
215 	bool mclk_sw;
216 };
217 
218 struct dc_caps {
219 	uint32_t max_streams;
220 	uint32_t max_links;
221 	uint32_t max_audios;
222 	uint32_t max_slave_planes;
223 	uint32_t max_slave_yuv_planes;
224 	uint32_t max_slave_rgb_planes;
225 	uint32_t max_planes;
226 	uint32_t max_downscale_ratio;
227 	uint32_t i2c_speed_in_khz;
228 	uint32_t i2c_speed_in_khz_hdcp;
229 	uint32_t dmdata_alloc_size;
230 	unsigned int max_cursor_size;
231 	unsigned int max_video_width;
232 	unsigned int min_horizontal_blanking_period;
233 	int linear_pitch_alignment;
234 	bool dcc_const_color;
235 	bool dynamic_audio;
236 	bool is_apu;
237 	bool dual_link_dvi;
238 	bool post_blend_color_processing;
239 	bool force_dp_tps4_for_cp2520;
240 	bool disable_dp_clk_share;
241 	bool psp_setup_panel_mode;
242 	bool extended_aux_timeout_support;
243 	bool dmcub_support;
244 	bool zstate_support;
245 	uint32_t num_of_internal_disp;
246 	enum dp_protocol_version max_dp_protocol_version;
247 	unsigned int mall_size_per_mem_channel;
248 	unsigned int mall_size_total;
249 	unsigned int cursor_cache_size;
250 	struct dc_plane_cap planes[MAX_PLANES];
251 	struct dc_color_caps color;
252 	struct dc_dmub_caps dmub_caps;
253 	bool dp_hpo;
254 	bool dp_hdmi21_pcon_support;
255 	bool edp_dsc_support;
256 	bool vbios_lttpr_aware;
257 	bool vbios_lttpr_enable;
258 	uint32_t max_otg_num;
259 	uint32_t max_cab_allocation_bytes;
260 	uint32_t cache_line_size;
261 	uint32_t cache_num_ways;
262 	uint16_t subvp_fw_processing_delay_us;
263 	uint8_t subvp_drr_max_vblank_margin_us;
264 	uint16_t subvp_prefetch_end_to_mall_start_us;
265 	uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height
266 	uint16_t subvp_pstate_allow_width_us;
267 	uint16_t subvp_vertical_int_margin_us;
268 	bool seamless_odm;
269 	uint8_t subvp_drr_vblank_start_margin_us;
270 };
271 
272 struct dc_bug_wa {
273 	bool no_connect_phy_config;
274 	bool dedcn20_305_wa;
275 	bool skip_clock_update;
276 	bool lt_early_cr_pattern;
277 };
278 
279 struct dc_dcc_surface_param {
280 	struct dc_size surface_size;
281 	enum surface_pixel_format format;
282 	enum swizzle_mode_values swizzle_mode;
283 	enum dc_scan_direction scan;
284 };
285 
286 struct dc_dcc_setting {
287 	unsigned int max_compressed_blk_size;
288 	unsigned int max_uncompressed_blk_size;
289 	bool independent_64b_blks;
290 	//These bitfields to be used starting with DCN
291 	struct {
292 		uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case)
293 		uint32_t dcc_128_128_uncontrained : 1;  //available in ASICs before DCN
294 		uint32_t dcc_256_128_128 : 1;		//available starting with DCN
295 		uint32_t dcc_256_256_unconstrained : 1;  //available in ASICs before DCN (the best compression case)
296 	} dcc_controls;
297 };
298 
299 struct dc_surface_dcc_cap {
300 	union {
301 		struct {
302 			struct dc_dcc_setting rgb;
303 		} grph;
304 
305 		struct {
306 			struct dc_dcc_setting luma;
307 			struct dc_dcc_setting chroma;
308 		} video;
309 	};
310 
311 	bool capable;
312 	bool const_color_support;
313 };
314 
315 struct dc_static_screen_params {
316 	struct {
317 		bool force_trigger;
318 		bool cursor_update;
319 		bool surface_update;
320 		bool overlay_update;
321 	} triggers;
322 	unsigned int num_frames;
323 };
324 
325 
326 /* Surface update type is used by dc_update_surfaces_and_stream
327  * The update type is determined at the very beginning of the function based
328  * on parameters passed in and decides how much programming (or updating) is
329  * going to be done during the call.
330  *
331  * UPDATE_TYPE_FAST is used for really fast updates that do not require much
332  * logical calculations or hardware register programming. This update MUST be
333  * ISR safe on windows. Currently fast update will only be used to flip surface
334  * address.
335  *
336  * UPDATE_TYPE_MED is used for slower updates which require significant hw
337  * re-programming however do not affect bandwidth consumption or clock
338  * requirements. At present, this is the level at which front end updates
339  * that do not require us to run bw_calcs happen. These are in/out transfer func
340  * updates, viewport offset changes, recout size changes and pixel depth changes.
341  * This update can be done at ISR, but we want to minimize how often this happens.
342  *
343  * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
344  * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
345  * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
346  * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
347  * a full update. This cannot be done at ISR level and should be a rare event.
348  * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
349  * underscan we don't expect to see this call at all.
350  */
351 
352 enum surface_update_type {
353 	UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
354 	UPDATE_TYPE_MED,  /* ISR safe, most of programming needed, no bw/clk change*/
355 	UPDATE_TYPE_FULL, /* may need to shuffle resources */
356 };
357 
358 /* Forward declaration*/
359 struct dc;
360 struct dc_plane_state;
361 struct dc_state;
362 
363 
364 struct dc_cap_funcs {
365 	bool (*get_dcc_compression_cap)(const struct dc *dc,
366 			const struct dc_dcc_surface_param *input,
367 			struct dc_surface_dcc_cap *output);
368 };
369 
370 struct link_training_settings;
371 
372 union allow_lttpr_non_transparent_mode {
373 	struct {
374 		bool DP1_4A : 1;
375 		bool DP2_0 : 1;
376 	} bits;
377 	unsigned char raw;
378 };
379 
380 /* Structure to hold configuration flags set by dm at dc creation. */
381 struct dc_config {
382 	bool gpu_vm_support;
383 	bool disable_disp_pll_sharing;
384 	bool fbc_support;
385 	bool disable_fractional_pwm;
386 	bool allow_seamless_boot_optimization;
387 	bool seamless_boot_edp_requested;
388 	bool edp_not_connected;
389 	bool edp_no_power_sequencing;
390 	bool force_enum_edp;
391 	bool forced_clocks;
392 	union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode;
393 	bool multi_mon_pp_mclk_switch;
394 	bool disable_dmcu;
395 	bool enable_4to1MPC;
396 	bool enable_windowed_mpo_odm;
397 	bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520
398 	uint32_t allow_edp_hotplug_detection;
399 	bool clamp_min_dcfclk;
400 	uint64_t vblank_alignment_dto_params;
401 	uint8_t  vblank_alignment_max_frame_time_diff;
402 	bool is_asymmetric_memory;
403 	bool is_single_rank_dimm;
404 	bool is_vmin_only_asic;
405 	bool use_pipe_ctx_sync_logic;
406 	bool ignore_dpref_ss;
407 	bool enable_mipi_converter_optimization;
408 	bool use_default_clock_table;
409 	bool force_bios_enable_lttpr;
410 	uint8_t force_bios_fixed_vs;
411 	int sdpif_request_limit_words_per_umc;
412 	bool disable_subvp_drr;
413 };
414 
415 enum visual_confirm {
416 	VISUAL_CONFIRM_DISABLE = 0,
417 	VISUAL_CONFIRM_SURFACE = 1,
418 	VISUAL_CONFIRM_HDR = 2,
419 	VISUAL_CONFIRM_MPCTREE = 4,
420 	VISUAL_CONFIRM_PSR = 5,
421 	VISUAL_CONFIRM_SWAPCHAIN = 6,
422 	VISUAL_CONFIRM_FAMS = 7,
423 	VISUAL_CONFIRM_SWIZZLE = 9,
424 	VISUAL_CONFIRM_SUBVP = 14,
425 };
426 
427 enum dc_psr_power_opts {
428 	psr_power_opt_invalid = 0x0,
429 	psr_power_opt_smu_opt_static_screen = 0x1,
430 	psr_power_opt_z10_static_screen = 0x10,
431 	psr_power_opt_ds_disable_allow = 0x100,
432 };
433 
434 enum dml_hostvm_override_opts {
435 	DML_HOSTVM_NO_OVERRIDE = 0x0,
436 	DML_HOSTVM_OVERRIDE_FALSE = 0x1,
437 	DML_HOSTVM_OVERRIDE_TRUE = 0x2,
438 };
439 
440 enum dcc_option {
441 	DCC_ENABLE = 0,
442 	DCC_DISABLE = 1,
443 	DCC_HALF_REQ_DISALBE = 2,
444 };
445 
446 /**
447  * enum pipe_split_policy - Pipe split strategy supported by DCN
448  *
449  * This enum is used to define the pipe split policy supported by DCN. By
450  * default, DC favors MPC_SPLIT_DYNAMIC.
451  */
452 enum pipe_split_policy {
453 	/**
454 	 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the
455 	 * pipe in order to bring the best trade-off between performance and
456 	 * power consumption. This is the recommended option.
457 	 */
458 	MPC_SPLIT_DYNAMIC = 0,
459 
460 	/**
461 	 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not
462 	 * try any sort of split optimization.
463 	 */
464 	MPC_SPLIT_AVOID = 1,
465 
466 	/**
467 	 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to
468 	 * optimize the pipe utilization when using a single display; if the
469 	 * user connects to a second display, DC will avoid pipe split.
470 	 */
471 	MPC_SPLIT_AVOID_MULT_DISP = 2,
472 };
473 
474 enum wm_report_mode {
475 	WM_REPORT_DEFAULT = 0,
476 	WM_REPORT_OVERRIDE = 1,
477 };
478 enum dtm_pstate{
479 	dtm_level_p0 = 0,/*highest voltage*/
480 	dtm_level_p1,
481 	dtm_level_p2,
482 	dtm_level_p3,
483 	dtm_level_p4,/*when active_display_count = 0*/
484 };
485 
486 enum dcn_pwr_state {
487 	DCN_PWR_STATE_UNKNOWN = -1,
488 	DCN_PWR_STATE_MISSION_MODE = 0,
489 	DCN_PWR_STATE_LOW_POWER = 3,
490 };
491 
492 enum dcn_zstate_support_state {
493 	DCN_ZSTATE_SUPPORT_UNKNOWN,
494 	DCN_ZSTATE_SUPPORT_ALLOW,
495 	DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY,
496 	DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY,
497 	DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,
498 	DCN_ZSTATE_SUPPORT_DISALLOW,
499 };
500 
501 /**
502  * struct dc_clocks - DC pipe clocks
503  *
504  * For any clocks that may differ per pipe only the max is stored in this
505  * structure
506  */
507 struct dc_clocks {
508 	int dispclk_khz;
509 	int actual_dispclk_khz;
510 	int dppclk_khz;
511 	int actual_dppclk_khz;
512 	int disp_dpp_voltage_level_khz;
513 	int dcfclk_khz;
514 	int socclk_khz;
515 	int dcfclk_deep_sleep_khz;
516 	int fclk_khz;
517 	int phyclk_khz;
518 	int dramclk_khz;
519 	bool p_state_change_support;
520 	enum dcn_zstate_support_state zstate_support;
521 	bool dtbclk_en;
522 	int ref_dtbclk_khz;
523 	bool fclk_p_state_change_support;
524 	enum dcn_pwr_state pwr_state;
525 	/*
526 	 * Elements below are not compared for the purposes of
527 	 * optimization required
528 	 */
529 	bool prev_p_state_change_support;
530 	bool fclk_prev_p_state_change_support;
531 	int num_ways;
532 
533 	/*
534 	 * @fw_based_mclk_switching
535 	 *
536 	 * DC has a mechanism that leverage the variable refresh rate to switch
537 	 * memory clock in cases that we have a large latency to achieve the
538 	 * memory clock change and a short vblank window. DC has some
539 	 * requirements to enable this feature, and this field describes if the
540 	 * system support or not such a feature.
541 	 */
542 	bool fw_based_mclk_switching;
543 	bool fw_based_mclk_switching_shut_down;
544 	int prev_num_ways;
545 	enum dtm_pstate dtm_level;
546 	int max_supported_dppclk_khz;
547 	int max_supported_dispclk_khz;
548 	int bw_dppclk_khz; /*a copy of dppclk_khz*/
549 	int bw_dispclk_khz;
550 };
551 
552 struct dc_bw_validation_profile {
553 	bool enable;
554 
555 	unsigned long long total_ticks;
556 	unsigned long long voltage_level_ticks;
557 	unsigned long long watermark_ticks;
558 	unsigned long long rq_dlg_ticks;
559 
560 	unsigned long long total_count;
561 	unsigned long long skip_fast_count;
562 	unsigned long long skip_pass_count;
563 	unsigned long long skip_fail_count;
564 };
565 
566 #define BW_VAL_TRACE_SETUP() \
567 		unsigned long long end_tick = 0; \
568 		unsigned long long voltage_level_tick = 0; \
569 		unsigned long long watermark_tick = 0; \
570 		unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
571 				dm_get_timestamp(dc->ctx) : 0
572 
573 #define BW_VAL_TRACE_COUNT() \
574 		if (dc->debug.bw_val_profile.enable) \
575 			dc->debug.bw_val_profile.total_count++
576 
577 #define BW_VAL_TRACE_SKIP(status) \
578 		if (dc->debug.bw_val_profile.enable) { \
579 			if (!voltage_level_tick) \
580 				voltage_level_tick = dm_get_timestamp(dc->ctx); \
581 			dc->debug.bw_val_profile.skip_ ## status ## _count++; \
582 		}
583 
584 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
585 		if (dc->debug.bw_val_profile.enable) \
586 			voltage_level_tick = dm_get_timestamp(dc->ctx)
587 
588 #define BW_VAL_TRACE_END_WATERMARKS() \
589 		if (dc->debug.bw_val_profile.enable) \
590 			watermark_tick = dm_get_timestamp(dc->ctx)
591 
592 #define BW_VAL_TRACE_FINISH() \
593 		if (dc->debug.bw_val_profile.enable) { \
594 			end_tick = dm_get_timestamp(dc->ctx); \
595 			dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
596 			dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
597 			if (watermark_tick) { \
598 				dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
599 				dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
600 			} \
601 		}
602 
603 union mem_low_power_enable_options {
604 	struct {
605 		bool vga: 1;
606 		bool i2c: 1;
607 		bool dmcu: 1;
608 		bool dscl: 1;
609 		bool cm: 1;
610 		bool mpc: 1;
611 		bool optc: 1;
612 		bool vpg: 1;
613 		bool afmt: 1;
614 	} bits;
615 	uint32_t u32All;
616 };
617 
618 union root_clock_optimization_options {
619 	struct {
620 		bool dpp: 1;
621 		bool dsc: 1;
622 		bool hdmistream: 1;
623 		bool hdmichar: 1;
624 		bool dpstream: 1;
625 		bool symclk32_se: 1;
626 		bool symclk32_le: 1;
627 		bool symclk_fe: 1;
628 		bool physymclk: 1;
629 		bool dpiasymclk: 1;
630 		uint32_t reserved: 22;
631 	} bits;
632 	uint32_t u32All;
633 };
634 
635 union dpia_debug_options {
636 	struct {
637 		uint32_t disable_dpia:1; /* bit 0 */
638 		uint32_t force_non_lttpr:1; /* bit 1 */
639 		uint32_t extend_aux_rd_interval:1; /* bit 2 */
640 		uint32_t disable_mst_dsc_work_around:1; /* bit 3 */
641 		uint32_t enable_force_tbt3_work_around:1; /* bit 4 */
642 		uint32_t reserved:27;
643 	} bits;
644 	uint32_t raw;
645 };
646 
647 /* AUX wake work around options
648  * 0: enable/disable work around
649  * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS
650  * 15-2: reserved
651  * 31-16: timeout in ms
652  */
653 union aux_wake_wa_options {
654 	struct {
655 		uint32_t enable_wa : 1;
656 		uint32_t use_default_timeout : 1;
657 		uint32_t rsvd: 14;
658 		uint32_t timeout_ms : 16;
659 	} bits;
660 	uint32_t raw;
661 };
662 
663 struct dc_debug_data {
664 	uint32_t ltFailCount;
665 	uint32_t i2cErrorCount;
666 	uint32_t auxErrorCount;
667 };
668 
669 struct dc_phy_addr_space_config {
670 	struct {
671 		uint64_t start_addr;
672 		uint64_t end_addr;
673 		uint64_t fb_top;
674 		uint64_t fb_offset;
675 		uint64_t fb_base;
676 		uint64_t agp_top;
677 		uint64_t agp_bot;
678 		uint64_t agp_base;
679 	} system_aperture;
680 
681 	struct {
682 		uint64_t page_table_start_addr;
683 		uint64_t page_table_end_addr;
684 		uint64_t page_table_base_addr;
685 		bool base_addr_is_mc_addr;
686 	} gart_config;
687 
688 	bool valid;
689 	bool is_hvm_enabled;
690 	uint64_t page_table_default_page_addr;
691 };
692 
693 struct dc_virtual_addr_space_config {
694 	uint64_t	page_table_base_addr;
695 	uint64_t	page_table_start_addr;
696 	uint64_t	page_table_end_addr;
697 	uint32_t	page_table_block_size_in_bytes;
698 	uint8_t		page_table_depth; // 1 = 1 level, 2 = 2 level, etc.  0 = invalid
699 };
700 
701 struct dc_bounding_box_overrides {
702 	int sr_exit_time_ns;
703 	int sr_enter_plus_exit_time_ns;
704 	int urgent_latency_ns;
705 	int percent_of_ideal_drambw;
706 	int dram_clock_change_latency_ns;
707 	int dummy_clock_change_latency_ns;
708 	int fclk_clock_change_latency_ns;
709 	/* This forces a hard min on the DCFCLK we use
710 	 * for DML.  Unlike the debug option for forcing
711 	 * DCFCLK, this override affects watermark calculations
712 	 */
713 	int min_dcfclk_mhz;
714 };
715 
716 struct dc_state;
717 struct resource_pool;
718 struct dce_hwseq;
719 
720 /**
721  * struct dc_debug_options - DC debug struct
722  *
723  * This struct provides a simple mechanism for developers to change some
724  * configurations, enable/disable features, and activate extra debug options.
725  * This can be very handy to narrow down whether some specific feature is
726  * causing an issue or not.
727  */
728 struct dc_debug_options {
729 	bool native422_support;
730 	bool disable_dsc;
731 	enum visual_confirm visual_confirm;
732 	int visual_confirm_rect_height;
733 
734 	bool sanity_checks;
735 	bool max_disp_clk;
736 	bool surface_trace;
737 	bool timing_trace;
738 	bool clock_trace;
739 	bool validation_trace;
740 	bool bandwidth_calcs_trace;
741 	int max_downscale_src_width;
742 
743 	/* stutter efficiency related */
744 	bool disable_stutter;
745 	bool use_max_lb;
746 	enum dcc_option disable_dcc;
747 
748 	/**
749 	 * @pipe_split_policy: Define which pipe split policy is used by the
750 	 * display core.
751 	 */
752 	enum pipe_split_policy pipe_split_policy;
753 	bool force_single_disp_pipe_split;
754 	bool voltage_align_fclk;
755 	bool disable_min_fclk;
756 
757 	bool disable_dfs_bypass;
758 	bool disable_dpp_power_gate;
759 	bool disable_hubp_power_gate;
760 	bool disable_dsc_power_gate;
761 	int dsc_min_slice_height_override;
762 	int dsc_bpp_increment_div;
763 	bool disable_pplib_wm_range;
764 	enum wm_report_mode pplib_wm_report_mode;
765 	unsigned int min_disp_clk_khz;
766 	unsigned int min_dpp_clk_khz;
767 	unsigned int min_dram_clk_khz;
768 	int sr_exit_time_dpm0_ns;
769 	int sr_enter_plus_exit_time_dpm0_ns;
770 	int sr_exit_time_ns;
771 	int sr_enter_plus_exit_time_ns;
772 	int urgent_latency_ns;
773 	uint32_t underflow_assert_delay_us;
774 	int percent_of_ideal_drambw;
775 	int dram_clock_change_latency_ns;
776 	bool optimized_watermark;
777 	int always_scale;
778 	bool disable_pplib_clock_request;
779 	bool disable_clock_gate;
780 	bool disable_mem_low_power;
781 	bool pstate_enabled;
782 	bool disable_dmcu;
783 	bool force_abm_enable;
784 	bool disable_stereo_support;
785 	bool vsr_support;
786 	bool performance_trace;
787 	bool az_endpoint_mute_only;
788 	bool always_use_regamma;
789 	bool recovery_enabled;
790 	bool avoid_vbios_exec_table;
791 	bool scl_reset_length10;
792 	bool hdmi20_disable;
793 	bool skip_detection_link_training;
794 	uint32_t edid_read_retry_times;
795 	unsigned int force_odm_combine; //bit vector based on otg inst
796 	unsigned int seamless_boot_odm_combine;
797 	unsigned int force_odm_combine_4to1; //bit vector based on otg inst
798 	bool disable_z9_mpc;
799 	unsigned int force_fclk_khz;
800 	bool enable_tri_buf;
801 	bool dmub_offload_enabled;
802 	bool dmcub_emulation;
803 	bool disable_idle_power_optimizations;
804 	unsigned int mall_size_override;
805 	unsigned int mall_additional_timer_percent;
806 	bool mall_error_as_fatal;
807 	bool dmub_command_table; /* for testing only */
808 	struct dc_bw_validation_profile bw_val_profile;
809 	bool disable_fec;
810 	bool disable_48mhz_pwrdwn;
811 	/* This forces a hard min on the DCFCLK requested to SMU/PP
812 	 * watermarks are not affected.
813 	 */
814 	unsigned int force_min_dcfclk_mhz;
815 	int dwb_fi_phase;
816 	bool disable_timing_sync;
817 	bool cm_in_bypass;
818 	int force_clock_mode;/*every mode change.*/
819 
820 	bool disable_dram_clock_change_vactive_support;
821 	bool validate_dml_output;
822 	bool enable_dmcub_surface_flip;
823 	bool usbc_combo_phy_reset_wa;
824 	bool enable_dram_clock_change_one_display_vactive;
825 	/* TODO - remove once tested */
826 	bool legacy_dp2_lt;
827 	bool set_mst_en_for_sst;
828 	bool disable_uhbr;
829 	bool force_dp2_lt_fallback_method;
830 	bool ignore_cable_id;
831 	union mem_low_power_enable_options enable_mem_low_power;
832 	union root_clock_optimization_options root_clock_optimization;
833 	bool hpo_optimization;
834 	bool force_vblank_alignment;
835 
836 	/* Enable dmub aux for legacy ddc */
837 	bool enable_dmub_aux_for_legacy_ddc;
838 	bool disable_fams;
839 	/* FEC/PSR1 sequence enable delay in 100us */
840 	uint8_t fec_enable_delay_in100us;
841 	bool enable_driver_sequence_debug;
842 	enum det_size crb_alloc_policy;
843 	int crb_alloc_policy_min_disp_count;
844 	bool disable_z10;
845 	bool enable_z9_disable_interface;
846 	bool psr_skip_crtc_disable;
847 	union dpia_debug_options dpia_debug;
848 	bool disable_fixed_vs_aux_timeout_wa;
849 	bool force_disable_subvp;
850 	bool force_subvp_mclk_switch;
851 	bool allow_sw_cursor_fallback;
852 	unsigned int force_subvp_num_ways;
853 	unsigned int force_mall_ss_num_ways;
854 	bool alloc_extra_way_for_cursor;
855 	uint32_t subvp_extra_lines;
856 	bool force_usr_allow;
857 	/* uses value at boot and disables switch */
858 	bool disable_dtb_ref_clk_switch;
859 	uint32_t fixed_vs_aux_delay_config_wa;
860 	bool extended_blank_optimization;
861 	union aux_wake_wa_options aux_wake_wa;
862 	uint32_t mst_start_top_delay;
863 	uint8_t psr_power_use_phy_fsm;
864 	enum dml_hostvm_override_opts dml_hostvm_override;
865 	bool dml_disallow_alternate_prefetch_modes;
866 	bool use_legacy_soc_bb_mechanism;
867 	bool exit_idle_opt_for_cursor_updates;
868 	bool enable_single_display_2to1_odm_policy;
869 	bool enable_double_buffered_dsc_pg_support;
870 	bool enable_dp_dig_pixel_rate_div_policy;
871 	enum lttpr_mode lttpr_mode_override;
872 	unsigned int dsc_delay_factor_wa_x1000;
873 	unsigned int min_prefetch_in_strobe_ns;
874 	bool disable_unbounded_requesting;
875 	bool dig_fifo_off_in_blank;
876 	bool temp_mst_deallocation_sequence;
877 };
878 
879 struct gpu_info_soc_bounding_box_v1_0;
880 struct dc {
881 	struct dc_debug_options debug;
882 	struct dc_versions versions;
883 	struct dc_caps caps;
884 	struct dc_cap_funcs cap_funcs;
885 	struct dc_config config;
886 	struct dc_bounding_box_overrides bb_overrides;
887 	struct dc_bug_wa work_arounds;
888 	struct dc_context *ctx;
889 	struct dc_phy_addr_space_config vm_pa_config;
890 
891 	uint8_t link_count;
892 	struct dc_link *links[MAX_PIPES * 2];
893 
894 	struct dc_state *current_state;
895 	struct resource_pool *res_pool;
896 
897 	struct clk_mgr *clk_mgr;
898 
899 	/* Display Engine Clock levels */
900 	struct dm_pp_clock_levels sclk_lvls;
901 
902 	/* Inputs into BW and WM calculations. */
903 	struct bw_calcs_dceip *bw_dceip;
904 	struct bw_calcs_vbios *bw_vbios;
905 	struct dcn_soc_bounding_box *dcn_soc;
906 	struct dcn_ip_params *dcn_ip;
907 	struct display_mode_lib dml;
908 
909 	/* HW functions */
910 	struct hw_sequencer_funcs hwss;
911 	struct dce_hwseq *hwseq;
912 
913 	/* Require to optimize clocks and bandwidth for added/removed planes */
914 	bool optimized_required;
915 	bool wm_optimized_required;
916 	bool idle_optimizations_allowed;
917 	bool enable_c20_dtm_b0;
918 
919 	/* Require to maintain clocks and bandwidth for UEFI enabled HW */
920 
921 	/* FBC compressor */
922 	struct compressor *fbc_compressor;
923 
924 	struct dc_debug_data debug_data;
925 	struct dpcd_vendor_signature vendor_signature;
926 
927 	const char *build_id;
928 	struct vm_helper *vm_helper;
929 
930 	uint32_t *dcn_reg_offsets;
931 	uint32_t *nbio_reg_offsets;
932 
933 	/* Scratch memory */
934 	struct {
935 		struct {
936 			/*
937 			 * For matching clock_limits table in driver with table
938 			 * from PMFW.
939 			 */
940 			struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
941 		} update_bw_bounding_box;
942 	} scratch;
943 };
944 
945 enum frame_buffer_mode {
946 	FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
947 	FRAME_BUFFER_MODE_ZFB_ONLY,
948 	FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
949 } ;
950 
951 struct dchub_init_data {
952 	int64_t zfb_phys_addr_base;
953 	int64_t zfb_mc_base_addr;
954 	uint64_t zfb_size_in_byte;
955 	enum frame_buffer_mode fb_mode;
956 	bool dchub_initialzied;
957 	bool dchub_info_valid;
958 };
959 
960 struct dc_init_data {
961 	struct hw_asic_id asic_id;
962 	void *driver; /* ctx */
963 	struct cgs_device *cgs_device;
964 	struct dc_bounding_box_overrides bb_overrides;
965 
966 	int num_virtual_links;
967 	/*
968 	 * If 'vbios_override' not NULL, it will be called instead
969 	 * of the real VBIOS. Intended use is Diagnostics on FPGA.
970 	 */
971 	struct dc_bios *vbios_override;
972 	enum dce_environment dce_environment;
973 
974 	struct dmub_offload_funcs *dmub_if;
975 	struct dc_reg_helper_state *dmub_offload;
976 
977 	struct dc_config flags;
978 	uint64_t log_mask;
979 
980 	struct dpcd_vendor_signature vendor_signature;
981 	bool force_smu_not_present;
982 	/*
983 	 * IP offset for run time initializaion of register addresses
984 	 *
985 	 * DCN3.5+ will fail dc_create() if these fields are null for them. They are
986 	 * applicable starting with DCN32/321 and are not used for ASICs upstreamed
987 	 * before them.
988 	 */
989 	uint32_t *dcn_reg_offsets;
990 	uint32_t *nbio_reg_offsets;
991 };
992 
993 struct dc_callback_init {
994 #ifdef CONFIG_DRM_AMD_DC_HDCP
995 	struct cp_psp cp_psp;
996 #else
997 	uint8_t reserved;
998 #endif
999 };
1000 
1001 struct dc *dc_create(const struct dc_init_data *init_params);
1002 void dc_hardware_init(struct dc *dc);
1003 
1004 int dc_get_vmid_use_vector(struct dc *dc);
1005 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
1006 /* Returns the number of vmids supported */
1007 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
1008 void dc_init_callbacks(struct dc *dc,
1009 		const struct dc_callback_init *init_params);
1010 void dc_deinit_callbacks(struct dc *dc);
1011 void dc_destroy(struct dc **dc);
1012 
1013 /* Surface Interfaces */
1014 
1015 enum {
1016 	TRANSFER_FUNC_POINTS = 1025
1017 };
1018 
1019 struct dc_hdr_static_metadata {
1020 	/* display chromaticities and white point in units of 0.00001 */
1021 	unsigned int chromaticity_green_x;
1022 	unsigned int chromaticity_green_y;
1023 	unsigned int chromaticity_blue_x;
1024 	unsigned int chromaticity_blue_y;
1025 	unsigned int chromaticity_red_x;
1026 	unsigned int chromaticity_red_y;
1027 	unsigned int chromaticity_white_point_x;
1028 	unsigned int chromaticity_white_point_y;
1029 
1030 	uint32_t min_luminance;
1031 	uint32_t max_luminance;
1032 	uint32_t maximum_content_light_level;
1033 	uint32_t maximum_frame_average_light_level;
1034 };
1035 
1036 enum dc_transfer_func_type {
1037 	TF_TYPE_PREDEFINED,
1038 	TF_TYPE_DISTRIBUTED_POINTS,
1039 	TF_TYPE_BYPASS,
1040 	TF_TYPE_HWPWL
1041 };
1042 
1043 struct dc_transfer_func_distributed_points {
1044 	struct fixed31_32 red[TRANSFER_FUNC_POINTS];
1045 	struct fixed31_32 green[TRANSFER_FUNC_POINTS];
1046 	struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
1047 
1048 	uint16_t end_exponent;
1049 	uint16_t x_point_at_y1_red;
1050 	uint16_t x_point_at_y1_green;
1051 	uint16_t x_point_at_y1_blue;
1052 };
1053 
1054 enum dc_transfer_func_predefined {
1055 	TRANSFER_FUNCTION_SRGB,
1056 	TRANSFER_FUNCTION_BT709,
1057 	TRANSFER_FUNCTION_PQ,
1058 	TRANSFER_FUNCTION_LINEAR,
1059 	TRANSFER_FUNCTION_UNITY,
1060 	TRANSFER_FUNCTION_HLG,
1061 	TRANSFER_FUNCTION_HLG12,
1062 	TRANSFER_FUNCTION_GAMMA22,
1063 	TRANSFER_FUNCTION_GAMMA24,
1064 	TRANSFER_FUNCTION_GAMMA26
1065 };
1066 
1067 
1068 struct dc_transfer_func {
1069 	struct kref refcount;
1070 	enum dc_transfer_func_type type;
1071 	enum dc_transfer_func_predefined tf;
1072 	/* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
1073 	uint32_t sdr_ref_white_level;
1074 	union {
1075 		struct pwl_params pwl;
1076 		struct dc_transfer_func_distributed_points tf_pts;
1077 	};
1078 };
1079 
1080 
1081 union dc_3dlut_state {
1082 	struct {
1083 		uint32_t initialized:1;		/*if 3dlut is went through color module for initialization */
1084 		uint32_t rmu_idx_valid:1;	/*if mux settings are valid*/
1085 		uint32_t rmu_mux_num:3;		/*index of mux to use*/
1086 		uint32_t mpc_rmu0_mux:4;	/*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
1087 		uint32_t mpc_rmu1_mux:4;
1088 		uint32_t mpc_rmu2_mux:4;
1089 		uint32_t reserved:15;
1090 	} bits;
1091 	uint32_t raw;
1092 };
1093 
1094 
1095 struct dc_3dlut {
1096 	struct kref refcount;
1097 	struct tetrahedral_params lut_3d;
1098 	struct fixed31_32 hdr_multiplier;
1099 	union dc_3dlut_state state;
1100 };
1101 /*
1102  * This structure is filled in by dc_surface_get_status and contains
1103  * the last requested address and the currently active address so the called
1104  * can determine if there are any outstanding flips
1105  */
1106 struct dc_plane_status {
1107 	struct dc_plane_address requested_address;
1108 	struct dc_plane_address current_address;
1109 	bool is_flip_pending;
1110 	bool is_right_eye;
1111 };
1112 
1113 union surface_update_flags {
1114 
1115 	struct {
1116 		uint32_t addr_update:1;
1117 		/* Medium updates */
1118 		uint32_t dcc_change:1;
1119 		uint32_t color_space_change:1;
1120 		uint32_t horizontal_mirror_change:1;
1121 		uint32_t per_pixel_alpha_change:1;
1122 		uint32_t global_alpha_change:1;
1123 		uint32_t hdr_mult:1;
1124 		uint32_t rotation_change:1;
1125 		uint32_t swizzle_change:1;
1126 		uint32_t scaling_change:1;
1127 		uint32_t position_change:1;
1128 		uint32_t in_transfer_func_change:1;
1129 		uint32_t input_csc_change:1;
1130 		uint32_t coeff_reduction_change:1;
1131 		uint32_t output_tf_change:1;
1132 		uint32_t pixel_format_change:1;
1133 		uint32_t plane_size_change:1;
1134 		uint32_t gamut_remap_change:1;
1135 
1136 		/* Full updates */
1137 		uint32_t new_plane:1;
1138 		uint32_t bpp_change:1;
1139 		uint32_t gamma_change:1;
1140 		uint32_t bandwidth_change:1;
1141 		uint32_t clock_change:1;
1142 		uint32_t stereo_format_change:1;
1143 		uint32_t lut_3d:1;
1144 		uint32_t tmz_changed:1;
1145 		uint32_t full_update:1;
1146 	} bits;
1147 
1148 	uint32_t raw;
1149 };
1150 
1151 struct dc_plane_state {
1152 	struct dc_plane_address address;
1153 	struct dc_plane_flip_time time;
1154 	bool triplebuffer_flips;
1155 	struct scaling_taps scaling_quality;
1156 	struct rect src_rect;
1157 	struct rect dst_rect;
1158 	struct rect clip_rect;
1159 
1160 	struct plane_size plane_size;
1161 	union dc_tiling_info tiling_info;
1162 
1163 	struct dc_plane_dcc_param dcc;
1164 
1165 	struct dc_gamma *gamma_correction;
1166 	struct dc_transfer_func *in_transfer_func;
1167 	struct dc_bias_and_scale *bias_and_scale;
1168 	struct dc_csc_transform input_csc_color_matrix;
1169 	struct fixed31_32 coeff_reduction_factor;
1170 	struct fixed31_32 hdr_mult;
1171 	struct colorspace_transform gamut_remap_matrix;
1172 
1173 	// TODO: No longer used, remove
1174 	struct dc_hdr_static_metadata hdr_static_ctx;
1175 
1176 	enum dc_color_space color_space;
1177 
1178 	struct dc_3dlut *lut3d_func;
1179 	struct dc_transfer_func *in_shaper_func;
1180 	struct dc_transfer_func *blend_tf;
1181 
1182 	struct dc_transfer_func *gamcor_tf;
1183 	enum surface_pixel_format format;
1184 	enum dc_rotation_angle rotation;
1185 	enum plane_stereo_format stereo_format;
1186 
1187 	bool is_tiling_rotated;
1188 	bool per_pixel_alpha;
1189 	bool pre_multiplied_alpha;
1190 	bool global_alpha;
1191 	int  global_alpha_value;
1192 	bool visible;
1193 	bool flip_immediate;
1194 	bool horizontal_mirror;
1195 	int layer_index;
1196 
1197 	union surface_update_flags update_flags;
1198 	bool flip_int_enabled;
1199 	bool skip_manual_trigger;
1200 
1201 	/* private to DC core */
1202 	struct dc_plane_status status;
1203 	struct dc_context *ctx;
1204 
1205 	/* HACK: Workaround for forcing full reprogramming under some conditions */
1206 	bool force_full_update;
1207 
1208 	bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead
1209 
1210 	/* private to dc_surface.c */
1211 	enum dc_irq_source irq_source;
1212 	struct kref refcount;
1213 	struct tg_color visual_confirm_color;
1214 
1215 	bool is_statically_allocated;
1216 };
1217 
1218 struct dc_plane_info {
1219 	struct plane_size plane_size;
1220 	union dc_tiling_info tiling_info;
1221 	struct dc_plane_dcc_param dcc;
1222 	enum surface_pixel_format format;
1223 	enum dc_rotation_angle rotation;
1224 	enum plane_stereo_format stereo_format;
1225 	enum dc_color_space color_space;
1226 	bool horizontal_mirror;
1227 	bool visible;
1228 	bool per_pixel_alpha;
1229 	bool pre_multiplied_alpha;
1230 	bool global_alpha;
1231 	int  global_alpha_value;
1232 	bool input_csc_enabled;
1233 	int layer_index;
1234 };
1235 
1236 struct dc_scaling_info {
1237 	struct rect src_rect;
1238 	struct rect dst_rect;
1239 	struct rect clip_rect;
1240 	struct scaling_taps scaling_quality;
1241 };
1242 
1243 struct dc_surface_update {
1244 	struct dc_plane_state *surface;
1245 
1246 	/* isr safe update parameters.  null means no updates */
1247 	const struct dc_flip_addrs *flip_addr;
1248 	const struct dc_plane_info *plane_info;
1249 	const struct dc_scaling_info *scaling_info;
1250 	struct fixed31_32 hdr_mult;
1251 	/* following updates require alloc/sleep/spin that is not isr safe,
1252 	 * null means no updates
1253 	 */
1254 	const struct dc_gamma *gamma;
1255 	const struct dc_transfer_func *in_transfer_func;
1256 
1257 	const struct dc_csc_transform *input_csc_color_matrix;
1258 	const struct fixed31_32 *coeff_reduction_factor;
1259 	const struct dc_transfer_func *func_shaper;
1260 	const struct dc_3dlut *lut3d_func;
1261 	const struct dc_transfer_func *blend_tf;
1262 	const struct colorspace_transform *gamut_remap_matrix;
1263 };
1264 
1265 /*
1266  * Create a new surface with default parameters;
1267  */
1268 struct dc_plane_state *dc_create_plane_state(struct dc *dc);
1269 const struct dc_plane_status *dc_plane_get_status(
1270 		const struct dc_plane_state *plane_state);
1271 
1272 void dc_plane_state_retain(struct dc_plane_state *plane_state);
1273 void dc_plane_state_release(struct dc_plane_state *plane_state);
1274 
1275 void dc_gamma_retain(struct dc_gamma *dc_gamma);
1276 void dc_gamma_release(struct dc_gamma **dc_gamma);
1277 struct dc_gamma *dc_create_gamma(void);
1278 
1279 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
1280 void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
1281 struct dc_transfer_func *dc_create_transfer_func(void);
1282 
1283 struct dc_3dlut *dc_create_3dlut_func(void);
1284 void dc_3dlut_func_release(struct dc_3dlut *lut);
1285 void dc_3dlut_func_retain(struct dc_3dlut *lut);
1286 
1287 void dc_post_update_surfaces_to_stream(
1288 		struct dc *dc);
1289 
1290 #include "dc_stream.h"
1291 
1292 /**
1293  * struct dc_validation_set - Struct to store surface/stream associations for validation
1294  */
1295 struct dc_validation_set {
1296 	/**
1297 	 * @stream: Stream state properties
1298 	 */
1299 	struct dc_stream_state *stream;
1300 
1301 	/**
1302 	 * @plane_state: Surface state
1303 	 */
1304 	struct dc_plane_state *plane_states[MAX_SURFACES];
1305 
1306 	/**
1307 	 * @plane_count: Total of active planes
1308 	 */
1309 	uint8_t plane_count;
1310 };
1311 
1312 bool dc_validate_boot_timing(const struct dc *dc,
1313 				const struct dc_sink *sink,
1314 				struct dc_crtc_timing *crtc_timing);
1315 
1316 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
1317 
1318 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
1319 
1320 enum dc_status dc_validate_with_context(struct dc *dc,
1321 					const struct dc_validation_set set[],
1322 					int set_count,
1323 					struct dc_state *context,
1324 					bool fast_validate);
1325 
1326 bool dc_set_generic_gpio_for_stereo(bool enable,
1327 		struct gpio_service *gpio_service);
1328 
1329 /*
1330  * fast_validate: we return after determining if we can support the new state,
1331  * but before we populate the programming info
1332  */
1333 enum dc_status dc_validate_global_state(
1334 		struct dc *dc,
1335 		struct dc_state *new_ctx,
1336 		bool fast_validate);
1337 
1338 
1339 void dc_resource_state_construct(
1340 		const struct dc *dc,
1341 		struct dc_state *dst_ctx);
1342 
1343 bool dc_acquire_release_mpc_3dlut(
1344 		struct dc *dc, bool acquire,
1345 		struct dc_stream_state *stream,
1346 		struct dc_3dlut **lut,
1347 		struct dc_transfer_func **shaper);
1348 
1349 void dc_resource_state_copy_construct(
1350 		const struct dc_state *src_ctx,
1351 		struct dc_state *dst_ctx);
1352 
1353 void dc_resource_state_copy_construct_current(
1354 		const struct dc *dc,
1355 		struct dc_state *dst_ctx);
1356 
1357 void dc_resource_state_destruct(struct dc_state *context);
1358 
1359 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
1360 
1361 enum dc_status dc_commit_streams(struct dc *dc,
1362 				 struct dc_stream_state *streams[],
1363 				 uint8_t stream_count);
1364 
1365 /* TODO: When the transition to the new commit sequence is done, remove this
1366  * function in favor of dc_commit_streams. */
1367 bool dc_commit_state(struct dc *dc, struct dc_state *context);
1368 
1369 struct dc_state *dc_create_state(struct dc *dc);
1370 struct dc_state *dc_copy_state(struct dc_state *src_ctx);
1371 void dc_retain_state(struct dc_state *context);
1372 void dc_release_state(struct dc_state *context);
1373 
1374 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc,
1375 		struct dc_stream_state *stream,
1376 		int mpcc_inst);
1377 
1378 
1379 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
1380 
1381 /* Link Interfaces */
1382 /* TODO: remove this after resolving external dependencies */
1383 #include "dc_link.h"
1384 
1385 /* The function initiates detection handshake over the given link. It first
1386  * determines if there are display connections over the link. If so it initiates
1387  * detection protocols supported by the connected receiver device. The function
1388  * contains protocol specific handshake sequences which are sometimes mandatory
1389  * to establish a proper connection between TX and RX. So it is always
1390  * recommended to call this function as the first link operation upon HPD event
1391  * or power up event. Upon completion, the function will update link structure
1392  * in place based on latest RX capabilities. The function may also cause dpms
1393  * to be reset to off for all currently enabled streams to the link. It is DM's
1394  * responsibility to serialize detection and DPMS updates.
1395  *
1396  * @reason - Indicate which event triggers this detection. dc may customize
1397  * detection flow depending on the triggering events.
1398  * return false - if detection is not fully completed. This could happen when
1399  * there is an unrecoverable error during detection or detection is partially
1400  * completed (detection has been delegated to dm mst manager ie.
1401  * link->connection_type == dc_connection_mst_branch when returning false).
1402  * return true - detection is completed, link has been fully updated with latest
1403  * detection result.
1404  */
1405 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason);
1406 
1407 /* determine if there is a sink connected to the link
1408  *
1409  * @type - dc_connection_single if connected, dc_connection_none otherwise.
1410  * return - false if an unexpected error occurs, true otherwise.
1411  *
1412  * NOTE: This function doesn't detect downstream sink connections i.e
1413  * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will
1414  * return dc_connection_single if the branch device is connected despite of
1415  * downstream sink's connection status.
1416  */
1417 bool dc_link_detect_connection_type(struct dc_link *link,
1418 		enum dc_connection_type *type);
1419 
1420 /* Getter for cached link status from given link */
1421 const struct dc_link_status *dc_link_get_status(const struct dc_link *link);
1422 
1423 #ifdef CONFIG_DRM_AMD_DC_HDCP
1424 /* return true if the connected receiver supports the hdcp version */
1425 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal);
1426 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal);
1427 #endif
1428 
1429 /* The function clears recorded DP RX states in the link. DM should call this
1430  * function when it is resuming from S3 power state to previously connected links.
1431  *
1432  * TODO - in the future we should consider to expand link resume interface to
1433  * support clearing previous rx states. So we don't have to rely on dm to call
1434  * this interface explicitly.
1435  */
1436 void dc_link_clear_dprx_states(struct dc_link *link);
1437 
1438 /* Destruct the mst topology of the link and reset the allocated payload table
1439  *
1440  * NOTE: this should only be called if DM chooses not to call dc_link_detect but
1441  * still wants to reset MST topology on an unplug event */
1442 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link);
1443 
1444 /* The function calculates effective DP link bandwidth when a given link is
1445  * using the given link settings.
1446  *
1447  * return - total effective link bandwidth in kbps.
1448  */
1449 uint32_t dc_link_bandwidth_kbps(
1450 	const struct dc_link *link,
1451 	const struct dc_link_settings *link_setting);
1452 
1453 /* The function returns minimum bandwidth required to drive a given timing
1454  * return - minimum required timing bandwidth in kbps.
1455  */
1456 uint32_t dc_bandwidth_in_kbps_from_timing(
1457 	const struct dc_crtc_timing *timing);
1458 
1459 /* The function takes a snapshot of current link resource allocation state
1460  * @dc: pointer to dc of the dm calling this
1461  * @map: a dc link resource snapshot defined internally to dc.
1462  *
1463  * DM needs to capture a snapshot of current link resource allocation mapping
1464  * and store it in its persistent storage.
1465  *
1466  * Some of the link resource is using first come first serve policy.
1467  * The allocation mapping depends on original hotplug order. This information
1468  * is lost after driver is loaded next time. The snapshot is used in order to
1469  * restore link resource to its previous state so user will get consistent
1470  * link capability allocation across reboot.
1471  *
1472  */
1473 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map);
1474 
1475 /* This function restores link resource allocation state from a snapshot
1476  * @dc: pointer to dc of the dm calling this
1477  * @map: a dc link resource snapshot defined internally to dc.
1478  *
1479  * DM needs to call this function after initial link detection on boot and
1480  * before first commit streams to restore link resource allocation state
1481  * from previous boot session.
1482  *
1483  * Some of the link resource is using first come first serve policy.
1484  * The allocation mapping depends on original hotplug order. This information
1485  * is lost after driver is loaded next time. The snapshot is used in order to
1486  * restore link resource to its previous state so user will get consistent
1487  * link capability allocation across reboot.
1488  *
1489  */
1490 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map);
1491 
1492 /* TODO: this is not meant to be exposed to DM. Should switch to stream update
1493  * interface i.e stream_update->dsc_config
1494  */
1495 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx);
1496 /* Sink Interfaces - A sink corresponds to a display output device */
1497 
1498 struct dc_container_id {
1499 	// 128bit GUID in binary form
1500 	unsigned char  guid[16];
1501 	// 8 byte port ID -> ELD.PortID
1502 	unsigned int   portId[2];
1503 	// 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
1504 	unsigned short manufacturerName;
1505 	// 2 byte product code -> ELD.ProductCode
1506 	unsigned short productCode;
1507 };
1508 
1509 
1510 struct dc_sink_dsc_caps {
1511 	// 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
1512 	// 'false' if they are sink's DSC caps
1513 	bool is_virtual_dpcd_dsc;
1514 #if defined(CONFIG_DRM_AMD_DC_DCN)
1515 	// 'true' if MST topology supports DSC passthrough for sink
1516 	// 'false' if MST topology does not support DSC passthrough
1517 	bool is_dsc_passthrough_supported;
1518 #endif
1519 	struct dsc_dec_dpcd_caps dsc_dec_caps;
1520 };
1521 
1522 struct dc_sink_fec_caps {
1523 	bool is_rx_fec_supported;
1524 	bool is_topology_fec_supported;
1525 };
1526 
1527 struct scdc_caps {
1528 	union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI;
1529 	union hdmi_scdc_device_id_data device_id;
1530 };
1531 
1532 /*
1533  * The sink structure contains EDID and other display device properties
1534  */
1535 struct dc_sink {
1536 	enum signal_type sink_signal;
1537 	struct dc_edid dc_edid; /* raw edid */
1538 	struct dc_edid_caps edid_caps; /* parse display caps */
1539 	struct dc_container_id *dc_container_id;
1540 	uint32_t dongle_max_pix_clk;
1541 	void *priv;
1542 	struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
1543 	bool converter_disable_audio;
1544 
1545 	struct scdc_caps scdc_caps;
1546 	struct dc_sink_dsc_caps dsc_caps;
1547 	struct dc_sink_fec_caps fec_caps;
1548 
1549 	bool is_vsc_sdp_colorimetry_supported;
1550 
1551 	/* private to DC core */
1552 	struct dc_link *link;
1553 	struct dc_context *ctx;
1554 
1555 	uint32_t sink_id;
1556 
1557 	/* private to dc_sink.c */
1558 	// refcount must be the last member in dc_sink, since we want the
1559 	// sink structure to be logically cloneable up to (but not including)
1560 	// refcount
1561 	struct kref refcount;
1562 };
1563 
1564 void dc_sink_retain(struct dc_sink *sink);
1565 void dc_sink_release(struct dc_sink *sink);
1566 
1567 struct dc_sink_init_data {
1568 	enum signal_type sink_signal;
1569 	struct dc_link *link;
1570 	uint32_t dongle_max_pix_clk;
1571 	bool converter_disable_audio;
1572 };
1573 
1574 bool dc_extended_blank_supported(struct dc *dc);
1575 
1576 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
1577 
1578 /* Newer interfaces  */
1579 struct dc_cursor {
1580 	struct dc_plane_address address;
1581 	struct dc_cursor_attributes attributes;
1582 };
1583 
1584 
1585 /* Interrupt interfaces */
1586 enum dc_irq_source dc_interrupt_to_irq_source(
1587 		struct dc *dc,
1588 		uint32_t src_id,
1589 		uint32_t ext_id);
1590 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
1591 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
1592 enum dc_irq_source dc_get_hpd_irq_source_at_index(
1593 		struct dc *dc, uint32_t link_index);
1594 
1595 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable);
1596 
1597 /* Power Interfaces */
1598 
1599 void dc_set_power_state(
1600 		struct dc *dc,
1601 		enum dc_acpi_cm_power_state power_state);
1602 void dc_resume(struct dc *dc);
1603 
1604 void dc_power_down_on_boot(struct dc *dc);
1605 
1606 #if defined(CONFIG_DRM_AMD_DC_HDCP)
1607 /*
1608  * HDCP Interfaces
1609  */
1610 enum hdcp_message_status dc_process_hdcp_msg(
1611 		enum signal_type signal,
1612 		struct dc_link *link,
1613 		struct hdcp_protection_message *message_info);
1614 #endif
1615 bool dc_is_dmcu_initialized(struct dc *dc);
1616 
1617 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
1618 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
1619 
1620 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
1621 				struct dc_cursor_attributes *cursor_attr);
1622 
1623 void dc_allow_idle_optimizations(struct dc *dc, bool allow);
1624 
1625 /* set min and max memory clock to lowest and highest DPM level, respectively */
1626 void dc_unlock_memory_clock_frequency(struct dc *dc);
1627 
1628 /* set min memory clock to the min required for current mode, max to maxDPM */
1629 void dc_lock_memory_clock_frequency(struct dc *dc);
1630 
1631 /* set soft max for memclk, to be used for AC/DC switching clock limitations */
1632 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
1633 
1634 /* cleanup on driver unload */
1635 void dc_hardware_release(struct dc *dc);
1636 
1637 /* disables fw based mclk switch */
1638 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc);
1639 
1640 bool dc_set_psr_allow_active(struct dc *dc, bool enable);
1641 void dc_z10_restore(const struct dc *dc);
1642 void dc_z10_save_init(struct dc *dc);
1643 
1644 bool dc_is_dmub_outbox_supported(struct dc *dc);
1645 bool dc_enable_dmub_notifications(struct dc *dc);
1646 
1647 void dc_enable_dmub_outbox(struct dc *dc);
1648 
1649 bool dc_process_dmub_aux_transfer_async(struct dc *dc,
1650 				uint32_t link_index,
1651 				struct aux_payload *payload);
1652 
1653 /* Get dc link index from dpia port index */
1654 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
1655 				uint8_t dpia_port_index);
1656 
1657 bool dc_process_dmub_set_config_async(struct dc *dc,
1658 				uint32_t link_index,
1659 				struct set_config_cmd_payload *payload,
1660 				struct dmub_notification *notify);
1661 
1662 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
1663 				uint32_t link_index,
1664 				uint8_t mst_alloc_slots,
1665 				uint8_t *mst_slots_in_use);
1666 
1667 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,
1668 				uint32_t hpd_int_enable);
1669 
1670 /* DSC Interfaces */
1671 #include "dc_dsc.h"
1672 
1673 /* Disable acc mode Interfaces */
1674 void dc_disable_accelerated_mode(struct dc *dc);
1675 
1676 #endif /* DC_INTERFACE_H_ */
1677